279 строки
6.9 KiB
C
279 строки
6.9 KiB
C
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Copyright (C) Sunplus Technology Co., Ltd.
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* All rights reserved.
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*/
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#define SP_INTC_HWIRQ_MIN 0
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#define SP_INTC_HWIRQ_MAX 223
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#define SP_INTC_NR_IRQS (SP_INTC_HWIRQ_MAX - SP_INTC_HWIRQ_MIN + 1)
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#define SP_INTC_NR_GROUPS DIV_ROUND_UP(SP_INTC_NR_IRQS, 32)
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#define SP_INTC_REG_SIZE (SP_INTC_NR_GROUPS * 4)
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/* REG_GROUP_0 regs */
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#define REG_INTR_TYPE (sp_intc.g0)
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#define REG_INTR_POLARITY (REG_INTR_TYPE + SP_INTC_REG_SIZE)
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#define REG_INTR_PRIORITY (REG_INTR_POLARITY + SP_INTC_REG_SIZE)
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#define REG_INTR_MASK (REG_INTR_PRIORITY + SP_INTC_REG_SIZE)
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/* REG_GROUP_1 regs */
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#define REG_INTR_CLEAR (sp_intc.g1)
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#define REG_MASKED_EXT1 (REG_INTR_CLEAR + SP_INTC_REG_SIZE)
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#define REG_MASKED_EXT0 (REG_MASKED_EXT1 + SP_INTC_REG_SIZE)
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#define REG_INTR_GROUP (REG_INTR_CLEAR + 31 * 4)
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#define GROUP_MASK (BIT(SP_INTC_NR_GROUPS) - 1)
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#define GROUP_SHIFT_EXT1 (0)
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#define GROUP_SHIFT_EXT0 (8)
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/*
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* When GPIO_INT0~7 set to edge trigger, doesn't work properly.
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* WORKAROUND: change it to level trigger, and toggle the polarity
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* at ACK/Handler to make the HW work.
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*/
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#define GPIO_INT0_HWIRQ 120
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#define GPIO_INT7_HWIRQ 127
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#define IS_GPIO_INT(irq) \
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({ \
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u32 i = irq; \
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(i >= GPIO_INT0_HWIRQ) && (i <= GPIO_INT7_HWIRQ); \
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})
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/* index of states */
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enum {
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_IS_EDGE = 0,
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_IS_LOW,
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_IS_ACTIVE
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};
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#define STATE_BIT(irq, idx) (((irq) - GPIO_INT0_HWIRQ) * 3 + (idx))
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#define ASSIGN_STATE(irq, idx, v) assign_bit(STATE_BIT(irq, idx), sp_intc.states, v)
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#define TEST_STATE(irq, idx) test_bit(STATE_BIT(irq, idx), sp_intc.states)
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static struct sp_intctl {
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/*
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* REG_GROUP_0: include type/polarity/priority/mask regs.
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* REG_GROUP_1: include clear/masked_ext0/masked_ext1/group regs.
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*/
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void __iomem *g0; // REG_GROUP_0 base
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void __iomem *g1; // REG_GROUP_1 base
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struct irq_domain *domain;
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raw_spinlock_t lock;
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/*
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* store GPIO_INT states
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* each interrupt has 3 states: is_edge, is_low, is_active
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*/
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DECLARE_BITMAP(states, (GPIO_INT7_HWIRQ - GPIO_INT0_HWIRQ + 1) * 3);
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} sp_intc;
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static struct irq_chip sp_intc_chip;
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static void sp_intc_assign_bit(u32 hwirq, void __iomem *base, bool value)
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{
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u32 offset, mask;
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unsigned long flags;
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void __iomem *reg;
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offset = (hwirq / 32) * 4;
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reg = base + offset;
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raw_spin_lock_irqsave(&sp_intc.lock, flags);
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mask = readl_relaxed(reg);
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if (value)
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mask |= BIT(hwirq % 32);
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else
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mask &= ~BIT(hwirq % 32);
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writel_relaxed(mask, reg);
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raw_spin_unlock_irqrestore(&sp_intc.lock, flags);
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}
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static void sp_intc_ack_irq(struct irq_data *d)
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{
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u32 hwirq = d->hwirq;
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if (unlikely(IS_GPIO_INT(hwirq) && TEST_STATE(hwirq, _IS_EDGE))) { // WORKAROUND
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sp_intc_assign_bit(hwirq, REG_INTR_POLARITY, !TEST_STATE(hwirq, _IS_LOW));
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ASSIGN_STATE(hwirq, _IS_ACTIVE, true);
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}
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sp_intc_assign_bit(hwirq, REG_INTR_CLEAR, 1);
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}
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static void sp_intc_mask_irq(struct irq_data *d)
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{
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sp_intc_assign_bit(d->hwirq, REG_INTR_MASK, 0);
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}
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static void sp_intc_unmask_irq(struct irq_data *d)
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{
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sp_intc_assign_bit(d->hwirq, REG_INTR_MASK, 1);
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}
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static int sp_intc_set_type(struct irq_data *d, unsigned int type)
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{
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u32 hwirq = d->hwirq;
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bool is_edge = !(type & IRQ_TYPE_LEVEL_MASK);
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bool is_low = (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_EDGE_FALLING);
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irq_set_handler_locked(d, is_edge ? handle_edge_irq : handle_level_irq);
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if (unlikely(IS_GPIO_INT(hwirq) && is_edge)) { // WORKAROUND
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/* store states */
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ASSIGN_STATE(hwirq, _IS_EDGE, is_edge);
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ASSIGN_STATE(hwirq, _IS_LOW, is_low);
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ASSIGN_STATE(hwirq, _IS_ACTIVE, false);
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/* change to level */
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is_edge = false;
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}
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sp_intc_assign_bit(hwirq, REG_INTR_TYPE, is_edge);
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sp_intc_assign_bit(hwirq, REG_INTR_POLARITY, is_low);
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return 0;
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}
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static int sp_intc_get_ext_irq(int ext_num)
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{
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void __iomem *base = ext_num ? REG_MASKED_EXT1 : REG_MASKED_EXT0;
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u32 shift = ext_num ? GROUP_SHIFT_EXT1 : GROUP_SHIFT_EXT0;
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u32 groups;
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u32 pending_group;
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u32 group;
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u32 pending_irq;
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groups = readl_relaxed(REG_INTR_GROUP);
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pending_group = (groups >> shift) & GROUP_MASK;
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if (!pending_group)
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return -1;
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group = fls(pending_group) - 1;
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pending_irq = readl_relaxed(base + group * 4);
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if (!pending_irq)
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return -1;
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return (group * 32) + fls(pending_irq) - 1;
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}
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static void sp_intc_handle_ext_cascaded(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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int ext_num = (uintptr_t)irq_desc_get_handler_data(desc);
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int hwirq;
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chained_irq_enter(chip, desc);
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while ((hwirq = sp_intc_get_ext_irq(ext_num)) >= 0) {
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if (unlikely(IS_GPIO_INT(hwirq) && TEST_STATE(hwirq, _IS_ACTIVE))) { // WORKAROUND
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ASSIGN_STATE(hwirq, _IS_ACTIVE, false);
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sp_intc_assign_bit(hwirq, REG_INTR_POLARITY, TEST_STATE(hwirq, _IS_LOW));
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} else {
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generic_handle_domain_irq(sp_intc.domain, hwirq);
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}
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}
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chained_irq_exit(chip, desc);
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}
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static struct irq_chip sp_intc_chip = {
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.name = "sp_intc",
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.irq_ack = sp_intc_ack_irq,
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.irq_mask = sp_intc_mask_irq,
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.irq_unmask = sp_intc_unmask_irq,
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.irq_set_type = sp_intc_set_type,
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};
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static int sp_intc_irq_domain_map(struct irq_domain *domain,
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unsigned int irq, irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &sp_intc_chip, handle_level_irq);
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irq_set_chip_data(irq, &sp_intc_chip);
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irq_set_noprobe(irq);
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return 0;
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}
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static const struct irq_domain_ops sp_intc_dm_ops = {
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.xlate = irq_domain_xlate_twocell,
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.map = sp_intc_irq_domain_map,
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};
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static int sp_intc_irq_map(struct device_node *node, int i)
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{
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unsigned int irq;
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irq = irq_of_parse_and_map(node, i);
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if (!irq)
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return -ENOENT;
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irq_set_chained_handler_and_data(irq, sp_intc_handle_ext_cascaded, (void *)(uintptr_t)i);
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return 0;
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}
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static int __init sp_intc_init_dt(struct device_node *node, struct device_node *parent)
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{
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int i, ret;
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sp_intc.g0 = of_iomap(node, 0);
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if (!sp_intc.g0)
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return -ENXIO;
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sp_intc.g1 = of_iomap(node, 1);
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if (!sp_intc.g1) {
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ret = -ENXIO;
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goto out_unmap0;
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}
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ret = sp_intc_irq_map(node, 0); // EXT_INT0
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if (ret)
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goto out_unmap1;
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ret = sp_intc_irq_map(node, 1); // EXT_INT1
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if (ret)
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goto out_unmap1;
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/* initial regs */
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for (i = 0; i < SP_INTC_NR_GROUPS; i++) {
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/* all mask */
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writel_relaxed(0, REG_INTR_MASK + i * 4);
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/* all edge */
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writel_relaxed(~0, REG_INTR_TYPE + i * 4);
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/* all high-active */
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writel_relaxed(0, REG_INTR_POLARITY + i * 4);
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/* all EXT_INT0 */
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writel_relaxed(~0, REG_INTR_PRIORITY + i * 4);
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/* all clear */
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writel_relaxed(~0, REG_INTR_CLEAR + i * 4);
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}
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sp_intc.domain = irq_domain_add_linear(node, SP_INTC_NR_IRQS,
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&sp_intc_dm_ops, &sp_intc);
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if (!sp_intc.domain) {
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ret = -ENOMEM;
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goto out_unmap1;
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}
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raw_spin_lock_init(&sp_intc.lock);
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return 0;
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out_unmap1:
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iounmap(sp_intc.g1);
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out_unmap0:
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iounmap(sp_intc.g0);
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return ret;
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}
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IRQCHIP_DECLARE(sp_intc, "sunplus,sp7021-intc", sp_intc_init_dt);
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