682 строки
17 KiB
C
682 строки
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2006-2010 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Authors: Shlomi Gridish <gridish@freescale.com>
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* Li Yang <leoli@freescale.com>
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* Based on cpm2_common.c from Dan Malek (dmalek@jlc.net)
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*
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* Description:
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* General Purpose functions for the global management of the
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* QUICC Engine (QE).
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*/
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#include <linux/bitmap.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <linux/spinlock.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/ioport.h>
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#include <linux/iopoll.h>
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#include <linux/crc32.h>
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#include <linux/mod_devicetable.h>
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#include <linux/of_platform.h>
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#include <soc/fsl/qe/immap_qe.h>
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#include <soc/fsl/qe/qe.h>
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static void qe_snums_init(void);
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static int qe_sdma_init(void);
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static DEFINE_SPINLOCK(qe_lock);
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DEFINE_SPINLOCK(cmxgcr_lock);
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EXPORT_SYMBOL(cmxgcr_lock);
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/* We allocate this here because it is used almost exclusively for
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* the communication processor devices.
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*/
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struct qe_immap __iomem *qe_immr;
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EXPORT_SYMBOL(qe_immr);
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static u8 snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */
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static DECLARE_BITMAP(snum_state, QE_NUM_OF_SNUM);
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static unsigned int qe_num_of_snum;
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static phys_addr_t qebase = -1;
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static struct device_node *qe_get_device_node(void)
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{
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struct device_node *qe;
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/*
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* Newer device trees have an "fsl,qe" compatible property for the QE
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* node, but we still need to support older device trees.
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*/
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qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
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if (qe)
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return qe;
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return of_find_node_by_type(NULL, "qe");
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}
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static phys_addr_t get_qe_base(void)
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{
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struct device_node *qe;
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int ret;
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struct resource res;
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if (qebase != -1)
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return qebase;
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qe = qe_get_device_node();
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if (!qe)
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return qebase;
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ret = of_address_to_resource(qe, 0, &res);
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if (!ret)
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qebase = res.start;
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of_node_put(qe);
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return qebase;
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}
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void qe_reset(void)
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{
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if (qe_immr == NULL)
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qe_immr = ioremap(get_qe_base(), QE_IMMAP_SIZE);
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qe_snums_init();
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qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
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QE_CR_PROTOCOL_UNSPECIFIED, 0);
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/* Reclaim the MURAM memory for our use. */
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qe_muram_init();
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if (qe_sdma_init())
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panic("sdma init failed!");
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}
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int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
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{
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unsigned long flags;
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u8 mcn_shift = 0, dev_shift = 0;
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u32 val;
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int ret;
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spin_lock_irqsave(&qe_lock, flags);
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if (cmd == QE_RESET) {
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iowrite32be((u32)(cmd | QE_CR_FLG), &qe_immr->cp.cecr);
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} else {
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if (cmd == QE_ASSIGN_PAGE) {
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/* Here device is the SNUM, not sub-block */
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dev_shift = QE_CR_SNUM_SHIFT;
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} else if (cmd == QE_ASSIGN_RISC) {
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/* Here device is the SNUM, and mcnProtocol is
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* e_QeCmdRiscAssignment value */
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dev_shift = QE_CR_SNUM_SHIFT;
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mcn_shift = QE_CR_MCN_RISC_ASSIGN_SHIFT;
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} else {
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if (device == QE_CR_SUBBLOCK_USB)
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mcn_shift = QE_CR_MCN_USB_SHIFT;
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else
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mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
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}
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iowrite32be(cmd_input, &qe_immr->cp.cecdr);
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iowrite32be((cmd | QE_CR_FLG | ((u32)device << dev_shift) | (u32)mcn_protocol << mcn_shift),
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&qe_immr->cp.cecr);
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}
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/* wait for the QE_CR_FLG to clear */
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ret = readx_poll_timeout_atomic(ioread32be, &qe_immr->cp.cecr, val,
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(val & QE_CR_FLG) == 0, 0, 100);
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/* On timeout, ret is -ETIMEDOUT, otherwise it will be 0. */
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spin_unlock_irqrestore(&qe_lock, flags);
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return ret == 0;
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}
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EXPORT_SYMBOL(qe_issue_cmd);
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/* Set a baud rate generator. This needs lots of work. There are
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* 16 BRGs, which can be connected to the QE channels or output
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* as clocks. The BRGs are in two different block of internal
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* memory mapped space.
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* The BRG clock is the QE clock divided by 2.
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* It was set up long ago during the initial boot phase and is
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* given to us.
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* Baud rate clocks are zero-based in the driver code (as that maps
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* to port numbers). Documentation uses 1-based numbering.
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*/
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static unsigned int brg_clk = 0;
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#define CLK_GRAN (1000)
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#define CLK_GRAN_LIMIT (5)
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unsigned int qe_get_brg_clk(void)
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{
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struct device_node *qe;
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u32 brg;
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unsigned int mod;
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if (brg_clk)
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return brg_clk;
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qe = qe_get_device_node();
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if (!qe)
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return brg_clk;
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if (!of_property_read_u32(qe, "brg-frequency", &brg))
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brg_clk = brg;
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of_node_put(qe);
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/* round this if near to a multiple of CLK_GRAN */
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mod = brg_clk % CLK_GRAN;
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if (mod) {
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if (mod < CLK_GRAN_LIMIT)
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brg_clk -= mod;
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else if (mod > (CLK_GRAN - CLK_GRAN_LIMIT))
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brg_clk += CLK_GRAN - mod;
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}
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return brg_clk;
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}
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EXPORT_SYMBOL(qe_get_brg_clk);
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#define PVR_VER_836x 0x8083
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#define PVR_VER_832x 0x8084
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static bool qe_general4_errata(void)
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{
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#ifdef CONFIG_PPC32
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return pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x);
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#endif
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return false;
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}
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/* Program the BRG to the given sampling rate and multiplier
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*
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* @brg: the BRG, QE_BRG1 - QE_BRG16
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* @rate: the desired sampling rate
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* @multiplier: corresponds to the value programmed in GUMR_L[RDCR] or
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* GUMR_L[TDCR]. E.g., if this BRG is the RX clock, and GUMR_L[RDCR]=01,
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* then 'multiplier' should be 8.
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*/
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int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
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{
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u32 divisor, tempval;
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u32 div16 = 0;
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if ((brg < QE_BRG1) || (brg > QE_BRG16))
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return -EINVAL;
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divisor = qe_get_brg_clk() / (rate * multiplier);
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if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
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div16 = QE_BRGC_DIV16;
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divisor /= 16;
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}
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/* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
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that the BRG divisor must be even if you're not using divide-by-16
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mode. */
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if (qe_general4_errata())
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if (!div16 && (divisor & 1) && (divisor > 3))
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divisor++;
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tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
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QE_BRGC_ENABLE | div16;
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iowrite32be(tempval, &qe_immr->brg.brgc[brg - QE_BRG1]);
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return 0;
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}
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EXPORT_SYMBOL(qe_setbrg);
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/* Convert a string to a QE clock source enum
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*
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* This function takes a string, typically from a property in the device
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* tree, and returns the corresponding "enum qe_clock" value.
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*/
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enum qe_clock qe_clock_source(const char *source)
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{
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unsigned int i;
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if (strcasecmp(source, "none") == 0)
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return QE_CLK_NONE;
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if (strcmp(source, "tsync_pin") == 0)
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return QE_TSYNC_PIN;
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if (strcmp(source, "rsync_pin") == 0)
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return QE_RSYNC_PIN;
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if (strncasecmp(source, "brg", 3) == 0) {
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i = simple_strtoul(source + 3, NULL, 10);
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if ((i >= 1) && (i <= 16))
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return (QE_BRG1 - 1) + i;
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else
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return QE_CLK_DUMMY;
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}
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if (strncasecmp(source, "clk", 3) == 0) {
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i = simple_strtoul(source + 3, NULL, 10);
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if ((i >= 1) && (i <= 24))
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return (QE_CLK1 - 1) + i;
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else
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return QE_CLK_DUMMY;
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}
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return QE_CLK_DUMMY;
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}
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EXPORT_SYMBOL(qe_clock_source);
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/* Initialize SNUMs (thread serial numbers) according to
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* QE Module Control chapter, SNUM table
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*/
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static void qe_snums_init(void)
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{
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static const u8 snum_init_76[] = {
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0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
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0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
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0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
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0xD8, 0xD9, 0xE8, 0xE9, 0x44, 0x45, 0x4C, 0x4D,
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0x54, 0x55, 0x5C, 0x5D, 0x64, 0x65, 0x6C, 0x6D,
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0x74, 0x75, 0x7C, 0x7D, 0x84, 0x85, 0x8C, 0x8D,
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0x94, 0x95, 0x9C, 0x9D, 0xA4, 0xA5, 0xAC, 0xAD,
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0xB4, 0xB5, 0xBC, 0xBD, 0xC4, 0xC5, 0xCC, 0xCD,
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0xD4, 0xD5, 0xDC, 0xDD, 0xE4, 0xE5, 0xEC, 0xED,
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0xF4, 0xF5, 0xFC, 0xFD,
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};
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static const u8 snum_init_46[] = {
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0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
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0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
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0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
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0xD8, 0xD9, 0xE8, 0xE9, 0x08, 0x09, 0x18, 0x19,
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0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59,
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0x68, 0x69, 0x78, 0x79, 0x80, 0x81,
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};
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struct device_node *qe;
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const u8 *snum_init;
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int i;
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bitmap_zero(snum_state, QE_NUM_OF_SNUM);
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qe_num_of_snum = 28; /* The default number of snum for threads is 28 */
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qe = qe_get_device_node();
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if (qe) {
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i = of_property_read_variable_u8_array(qe, "fsl,qe-snums",
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snums, 1, QE_NUM_OF_SNUM);
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if (i > 0) {
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of_node_put(qe);
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qe_num_of_snum = i;
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return;
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}
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/*
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* Fall back to legacy binding of using the value of
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* fsl,qe-num-snums to choose one of the static arrays
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* above.
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*/
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of_property_read_u32(qe, "fsl,qe-num-snums", &qe_num_of_snum);
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of_node_put(qe);
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}
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if (qe_num_of_snum == 76) {
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snum_init = snum_init_76;
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} else if (qe_num_of_snum == 28 || qe_num_of_snum == 46) {
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snum_init = snum_init_46;
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} else {
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pr_err("QE: unsupported value of fsl,qe-num-snums: %u\n", qe_num_of_snum);
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return;
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}
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memcpy(snums, snum_init, qe_num_of_snum);
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}
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int qe_get_snum(void)
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{
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unsigned long flags;
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int snum = -EBUSY;
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int i;
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spin_lock_irqsave(&qe_lock, flags);
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i = find_first_zero_bit(snum_state, qe_num_of_snum);
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if (i < qe_num_of_snum) {
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set_bit(i, snum_state);
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snum = snums[i];
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}
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spin_unlock_irqrestore(&qe_lock, flags);
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return snum;
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}
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EXPORT_SYMBOL(qe_get_snum);
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void qe_put_snum(u8 snum)
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{
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const u8 *p = memchr(snums, snum, qe_num_of_snum);
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if (p)
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clear_bit(p - snums, snum_state);
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}
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EXPORT_SYMBOL(qe_put_snum);
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static int qe_sdma_init(void)
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{
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struct sdma __iomem *sdma = &qe_immr->sdma;
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static s32 sdma_buf_offset = -ENOMEM;
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/* allocate 2 internal temporary buffers (512 bytes size each) for
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* the SDMA */
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if (sdma_buf_offset < 0) {
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sdma_buf_offset = qe_muram_alloc(512 * 2, 4096);
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if (sdma_buf_offset < 0)
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return -ENOMEM;
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}
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iowrite32be((u32)sdma_buf_offset & QE_SDEBCR_BA_MASK,
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&sdma->sdebcr);
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iowrite32be((QE_SDMR_GLB_1_MSK | (0x1 << QE_SDMR_CEN_SHIFT)),
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&sdma->sdmr);
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return 0;
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}
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/* The maximum number of RISCs we support */
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#define MAX_QE_RISC 4
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/* Firmware information stored here for qe_get_firmware_info() */
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static struct qe_firmware_info qe_firmware_info;
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/*
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* Set to 1 if QE firmware has been uploaded, and therefore
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* qe_firmware_info contains valid data.
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*/
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static int qe_firmware_uploaded;
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/*
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* Upload a QE microcode
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*
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* This function is a worker function for qe_upload_firmware(). It does
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* the actual uploading of the microcode.
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*/
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static void qe_upload_microcode(const void *base,
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const struct qe_microcode *ucode)
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{
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const __be32 *code = base + be32_to_cpu(ucode->code_offset);
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unsigned int i;
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if (ucode->major || ucode->minor || ucode->revision)
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printk(KERN_INFO "qe-firmware: "
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"uploading microcode '%s' version %u.%u.%u\n",
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ucode->id, ucode->major, ucode->minor, ucode->revision);
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else
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printk(KERN_INFO "qe-firmware: "
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"uploading microcode '%s'\n", ucode->id);
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/* Use auto-increment */
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iowrite32be(be32_to_cpu(ucode->iram_offset) | QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR,
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&qe_immr->iram.iadd);
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for (i = 0; i < be32_to_cpu(ucode->count); i++)
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iowrite32be(be32_to_cpu(code[i]), &qe_immr->iram.idata);
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/* Set I-RAM Ready Register */
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iowrite32be(QE_IRAM_READY, &qe_immr->iram.iready);
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}
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/*
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* Upload a microcode to the I-RAM at a specific address.
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*
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* See Documentation/powerpc/qe_firmware.rst for information on QE microcode
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* uploading.
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*
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* Currently, only version 1 is supported, so the 'version' field must be
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* set to 1.
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*
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* The SOC model and revision are not validated, they are only displayed for
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* informational purposes.
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*
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* 'calc_size' is the calculated size, in bytes, of the firmware structure and
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* all of the microcode structures, minus the CRC.
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*
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* 'length' is the size that the structure says it is, including the CRC.
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*/
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int qe_upload_firmware(const struct qe_firmware *firmware)
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{
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unsigned int i;
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unsigned int j;
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u32 crc;
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size_t calc_size;
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size_t length;
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const struct qe_header *hdr;
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if (!firmware) {
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printk(KERN_ERR "qe-firmware: invalid pointer\n");
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return -EINVAL;
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}
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hdr = &firmware->header;
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length = be32_to_cpu(hdr->length);
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/* Check the magic */
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if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
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(hdr->magic[2] != 'F')) {
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printk(KERN_ERR "qe-firmware: not a microcode\n");
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return -EPERM;
|
|
}
|
|
|
|
/* Check the version */
|
|
if (hdr->version != 1) {
|
|
printk(KERN_ERR "qe-firmware: unsupported version\n");
|
|
return -EPERM;
|
|
}
|
|
|
|
/* Validate some of the fields */
|
|
if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
|
|
printk(KERN_ERR "qe-firmware: invalid data\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Validate the length and check if there's a CRC */
|
|
calc_size = struct_size(firmware, microcode, firmware->count);
|
|
|
|
for (i = 0; i < firmware->count; i++)
|
|
/*
|
|
* For situations where the second RISC uses the same microcode
|
|
* as the first, the 'code_offset' and 'count' fields will be
|
|
* zero, so it's okay to add those.
|
|
*/
|
|
calc_size += sizeof(__be32) *
|
|
be32_to_cpu(firmware->microcode[i].count);
|
|
|
|
/* Validate the length */
|
|
if (length != calc_size + sizeof(__be32)) {
|
|
printk(KERN_ERR "qe-firmware: invalid length\n");
|
|
return -EPERM;
|
|
}
|
|
|
|
/* Validate the CRC */
|
|
crc = be32_to_cpu(*(__be32 *)((void *)firmware + calc_size));
|
|
if (crc != crc32(0, firmware, calc_size)) {
|
|
printk(KERN_ERR "qe-firmware: firmware CRC is invalid\n");
|
|
return -EIO;
|
|
}
|
|
|
|
/*
|
|
* If the microcode calls for it, split the I-RAM.
|
|
*/
|
|
if (!firmware->split)
|
|
qe_setbits_be16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
|
|
|
|
if (firmware->soc.model)
|
|
printk(KERN_INFO
|
|
"qe-firmware: firmware '%s' for %u V%u.%u\n",
|
|
firmware->id, be16_to_cpu(firmware->soc.model),
|
|
firmware->soc.major, firmware->soc.minor);
|
|
else
|
|
printk(KERN_INFO "qe-firmware: firmware '%s'\n",
|
|
firmware->id);
|
|
|
|
/*
|
|
* The QE only supports one microcode per RISC, so clear out all the
|
|
* saved microcode information and put in the new.
|
|
*/
|
|
memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
|
|
strlcpy(qe_firmware_info.id, firmware->id, sizeof(qe_firmware_info.id));
|
|
qe_firmware_info.extended_modes = be64_to_cpu(firmware->extended_modes);
|
|
memcpy(qe_firmware_info.vtraps, firmware->vtraps,
|
|
sizeof(firmware->vtraps));
|
|
|
|
/* Loop through each microcode. */
|
|
for (i = 0; i < firmware->count; i++) {
|
|
const struct qe_microcode *ucode = &firmware->microcode[i];
|
|
|
|
/* Upload a microcode if it's present */
|
|
if (ucode->code_offset)
|
|
qe_upload_microcode(firmware, ucode);
|
|
|
|
/* Program the traps for this processor */
|
|
for (j = 0; j < 16; j++) {
|
|
u32 trap = be32_to_cpu(ucode->traps[j]);
|
|
|
|
if (trap)
|
|
iowrite32be(trap,
|
|
&qe_immr->rsp[i].tibcr[j]);
|
|
}
|
|
|
|
/* Enable traps */
|
|
iowrite32be(be32_to_cpu(ucode->eccr),
|
|
&qe_immr->rsp[i].eccr);
|
|
}
|
|
|
|
qe_firmware_uploaded = 1;
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(qe_upload_firmware);
|
|
|
|
/*
|
|
* Get info on the currently-loaded firmware
|
|
*
|
|
* This function also checks the device tree to see if the boot loader has
|
|
* uploaded a firmware already.
|
|
*/
|
|
struct qe_firmware_info *qe_get_firmware_info(void)
|
|
{
|
|
static int initialized;
|
|
struct device_node *qe;
|
|
struct device_node *fw = NULL;
|
|
const char *sprop;
|
|
|
|
/*
|
|
* If we haven't checked yet, and a driver hasn't uploaded a firmware
|
|
* yet, then check the device tree for information.
|
|
*/
|
|
if (qe_firmware_uploaded)
|
|
return &qe_firmware_info;
|
|
|
|
if (initialized)
|
|
return NULL;
|
|
|
|
initialized = 1;
|
|
|
|
qe = qe_get_device_node();
|
|
if (!qe)
|
|
return NULL;
|
|
|
|
/* Find the 'firmware' child node */
|
|
fw = of_get_child_by_name(qe, "firmware");
|
|
of_node_put(qe);
|
|
|
|
/* Did we find the 'firmware' node? */
|
|
if (!fw)
|
|
return NULL;
|
|
|
|
qe_firmware_uploaded = 1;
|
|
|
|
/* Copy the data into qe_firmware_info*/
|
|
sprop = of_get_property(fw, "id", NULL);
|
|
if (sprop)
|
|
strlcpy(qe_firmware_info.id, sprop,
|
|
sizeof(qe_firmware_info.id));
|
|
|
|
of_property_read_u64(fw, "extended-modes",
|
|
&qe_firmware_info.extended_modes);
|
|
|
|
of_property_read_u32_array(fw, "virtual-traps", qe_firmware_info.vtraps,
|
|
ARRAY_SIZE(qe_firmware_info.vtraps));
|
|
|
|
of_node_put(fw);
|
|
|
|
return &qe_firmware_info;
|
|
}
|
|
EXPORT_SYMBOL(qe_get_firmware_info);
|
|
|
|
unsigned int qe_get_num_of_risc(void)
|
|
{
|
|
struct device_node *qe;
|
|
unsigned int num_of_risc = 0;
|
|
|
|
qe = qe_get_device_node();
|
|
if (!qe)
|
|
return num_of_risc;
|
|
|
|
of_property_read_u32(qe, "fsl,qe-num-riscs", &num_of_risc);
|
|
|
|
of_node_put(qe);
|
|
|
|
return num_of_risc;
|
|
}
|
|
EXPORT_SYMBOL(qe_get_num_of_risc);
|
|
|
|
unsigned int qe_get_num_of_snums(void)
|
|
{
|
|
return qe_num_of_snum;
|
|
}
|
|
EXPORT_SYMBOL(qe_get_num_of_snums);
|
|
|
|
static int __init qe_init(void)
|
|
{
|
|
struct device_node *np;
|
|
|
|
np = of_find_compatible_node(NULL, NULL, "fsl,qe");
|
|
if (!np)
|
|
return -ENODEV;
|
|
qe_reset();
|
|
of_node_put(np);
|
|
return 0;
|
|
}
|
|
subsys_initcall(qe_init);
|
|
|
|
#if defined(CONFIG_SUSPEND) && defined(CONFIG_PPC_85xx)
|
|
static int qe_resume(struct platform_device *ofdev)
|
|
{
|
|
if (!qe_alive_during_sleep())
|
|
qe_reset();
|
|
return 0;
|
|
}
|
|
|
|
static int qe_probe(struct platform_device *ofdev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id qe_ids[] = {
|
|
{ .compatible = "fsl,qe", },
|
|
{ },
|
|
};
|
|
|
|
static struct platform_driver qe_driver = {
|
|
.driver = {
|
|
.name = "fsl-qe",
|
|
.of_match_table = qe_ids,
|
|
},
|
|
.probe = qe_probe,
|
|
.resume = qe_resume,
|
|
};
|
|
|
|
builtin_platform_driver(qe_driver);
|
|
#endif /* defined(CONFIG_SUSPEND) && defined(CONFIG_PPC_85xx) */
|