349 строки
7.4 KiB
C
349 строки
7.4 KiB
C
/*
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* linux/arch/arm/mach-tegra/include/mach/pinmux.h
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*
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* Copyright (C) 2010 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __MACH_TEGRA_PINMUX_H
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#define __MACH_TEGRA_PINMUX_H
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enum tegra_pingroup {
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TEGRA_PINGROUP_ATA = 0,
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TEGRA_PINGROUP_ATB,
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TEGRA_PINGROUP_ATC,
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TEGRA_PINGROUP_ATD,
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TEGRA_PINGROUP_ATE,
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TEGRA_PINGROUP_CDEV1,
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TEGRA_PINGROUP_CDEV2,
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TEGRA_PINGROUP_CRTP,
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TEGRA_PINGROUP_CSUS,
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TEGRA_PINGROUP_DAP1,
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TEGRA_PINGROUP_DAP2,
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TEGRA_PINGROUP_DAP3,
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TEGRA_PINGROUP_DAP4,
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TEGRA_PINGROUP_DDC,
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TEGRA_PINGROUP_DTA,
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TEGRA_PINGROUP_DTB,
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TEGRA_PINGROUP_DTC,
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TEGRA_PINGROUP_DTD,
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TEGRA_PINGROUP_DTE,
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TEGRA_PINGROUP_DTF,
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TEGRA_PINGROUP_GMA,
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TEGRA_PINGROUP_GMB,
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TEGRA_PINGROUP_GMC,
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TEGRA_PINGROUP_GMD,
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TEGRA_PINGROUP_GME,
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TEGRA_PINGROUP_GPU,
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TEGRA_PINGROUP_GPU7,
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TEGRA_PINGROUP_GPV,
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TEGRA_PINGROUP_HDINT,
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TEGRA_PINGROUP_I2CP,
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TEGRA_PINGROUP_IRRX,
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TEGRA_PINGROUP_IRTX,
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TEGRA_PINGROUP_KBCA,
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TEGRA_PINGROUP_KBCB,
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TEGRA_PINGROUP_KBCC,
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TEGRA_PINGROUP_KBCD,
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TEGRA_PINGROUP_KBCE,
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TEGRA_PINGROUP_KBCF,
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TEGRA_PINGROUP_LCSN,
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TEGRA_PINGROUP_LD0,
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TEGRA_PINGROUP_LD1,
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TEGRA_PINGROUP_LD10,
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TEGRA_PINGROUP_LD11,
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TEGRA_PINGROUP_LD12,
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TEGRA_PINGROUP_LD13,
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TEGRA_PINGROUP_LD14,
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TEGRA_PINGROUP_LD15,
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TEGRA_PINGROUP_LD16,
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TEGRA_PINGROUP_LD17,
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TEGRA_PINGROUP_LD2,
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TEGRA_PINGROUP_LD3,
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TEGRA_PINGROUP_LD4,
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TEGRA_PINGROUP_LD5,
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TEGRA_PINGROUP_LD6,
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TEGRA_PINGROUP_LD7,
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TEGRA_PINGROUP_LD8,
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TEGRA_PINGROUP_LD9,
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TEGRA_PINGROUP_LDC,
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TEGRA_PINGROUP_LDI,
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TEGRA_PINGROUP_LHP0,
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TEGRA_PINGROUP_LHP1,
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TEGRA_PINGROUP_LHP2,
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TEGRA_PINGROUP_LHS,
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TEGRA_PINGROUP_LM0,
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TEGRA_PINGROUP_LM1,
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TEGRA_PINGROUP_LPP,
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TEGRA_PINGROUP_LPW0,
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TEGRA_PINGROUP_LPW1,
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TEGRA_PINGROUP_LPW2,
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TEGRA_PINGROUP_LSC0,
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TEGRA_PINGROUP_LSC1,
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TEGRA_PINGROUP_LSCK,
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TEGRA_PINGROUP_LSDA,
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TEGRA_PINGROUP_LSDI,
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TEGRA_PINGROUP_LSPI,
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TEGRA_PINGROUP_LVP0,
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TEGRA_PINGROUP_LVP1,
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TEGRA_PINGROUP_LVS,
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TEGRA_PINGROUP_OWC,
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TEGRA_PINGROUP_PMC,
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TEGRA_PINGROUP_PTA,
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TEGRA_PINGROUP_RM,
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TEGRA_PINGROUP_SDB,
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TEGRA_PINGROUP_SDC,
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TEGRA_PINGROUP_SDD,
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TEGRA_PINGROUP_SDIO1,
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TEGRA_PINGROUP_SLXA,
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TEGRA_PINGROUP_SLXC,
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TEGRA_PINGROUP_SLXD,
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TEGRA_PINGROUP_SLXK,
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TEGRA_PINGROUP_SPDI,
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TEGRA_PINGROUP_SPDO,
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TEGRA_PINGROUP_SPIA,
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TEGRA_PINGROUP_SPIB,
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TEGRA_PINGROUP_SPIC,
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TEGRA_PINGROUP_SPID,
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TEGRA_PINGROUP_SPIE,
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TEGRA_PINGROUP_SPIF,
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TEGRA_PINGROUP_SPIG,
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TEGRA_PINGROUP_SPIH,
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TEGRA_PINGROUP_UAA,
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TEGRA_PINGROUP_UAB,
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TEGRA_PINGROUP_UAC,
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TEGRA_PINGROUP_UAD,
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TEGRA_PINGROUP_UCA,
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TEGRA_PINGROUP_UCB,
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TEGRA_PINGROUP_UDA,
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/* these pin groups only have pullup and pull down control */
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TEGRA_PINGROUP_CK32,
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TEGRA_PINGROUP_DDRC,
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TEGRA_PINGROUP_PMCA,
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TEGRA_PINGROUP_PMCB,
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TEGRA_PINGROUP_PMCC,
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TEGRA_PINGROUP_PMCD,
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TEGRA_PINGROUP_PMCE,
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TEGRA_PINGROUP_XM2C,
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TEGRA_PINGROUP_XM2D,
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TEGRA_MAX_PINGROUP,
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};
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enum tegra_mux_func {
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TEGRA_MUX_RSVD = 0x8000,
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TEGRA_MUX_RSVD1 = 0x8000,
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TEGRA_MUX_RSVD2 = 0x8001,
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TEGRA_MUX_RSVD3 = 0x8002,
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TEGRA_MUX_RSVD4 = 0x8003,
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TEGRA_MUX_NONE = -1,
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TEGRA_MUX_AHB_CLK,
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TEGRA_MUX_APB_CLK,
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TEGRA_MUX_AUDIO_SYNC,
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TEGRA_MUX_CRT,
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TEGRA_MUX_DAP1,
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TEGRA_MUX_DAP2,
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TEGRA_MUX_DAP3,
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TEGRA_MUX_DAP4,
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TEGRA_MUX_DAP5,
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TEGRA_MUX_DISPLAYA,
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TEGRA_MUX_DISPLAYB,
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TEGRA_MUX_EMC_TEST0_DLL,
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TEGRA_MUX_EMC_TEST1_DLL,
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TEGRA_MUX_GMI,
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TEGRA_MUX_GMI_INT,
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TEGRA_MUX_HDMI,
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TEGRA_MUX_I2C,
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TEGRA_MUX_I2C2,
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TEGRA_MUX_I2C3,
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TEGRA_MUX_IDE,
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TEGRA_MUX_IRDA,
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TEGRA_MUX_KBC,
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TEGRA_MUX_MIO,
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TEGRA_MUX_MIPI_HS,
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TEGRA_MUX_NAND,
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TEGRA_MUX_OSC,
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TEGRA_MUX_OWR,
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TEGRA_MUX_PCIE,
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TEGRA_MUX_PLLA_OUT,
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TEGRA_MUX_PLLC_OUT1,
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TEGRA_MUX_PLLM_OUT1,
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TEGRA_MUX_PLLP_OUT2,
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TEGRA_MUX_PLLP_OUT3,
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TEGRA_MUX_PLLP_OUT4,
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TEGRA_MUX_PWM,
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TEGRA_MUX_PWR_INTR,
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TEGRA_MUX_PWR_ON,
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TEGRA_MUX_RTCK,
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TEGRA_MUX_SDIO1,
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TEGRA_MUX_SDIO2,
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TEGRA_MUX_SDIO3,
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TEGRA_MUX_SDIO4,
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TEGRA_MUX_SFLASH,
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TEGRA_MUX_SPDIF,
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TEGRA_MUX_SPI1,
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TEGRA_MUX_SPI2,
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TEGRA_MUX_SPI2_ALT,
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TEGRA_MUX_SPI3,
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TEGRA_MUX_SPI4,
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TEGRA_MUX_TRACE,
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TEGRA_MUX_TWC,
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TEGRA_MUX_UARTA,
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TEGRA_MUX_UARTB,
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TEGRA_MUX_UARTC,
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TEGRA_MUX_UARTD,
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TEGRA_MUX_UARTE,
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TEGRA_MUX_ULPI,
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TEGRA_MUX_VI,
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TEGRA_MUX_VI_SENSOR_CLK,
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TEGRA_MUX_XIO,
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TEGRA_MAX_MUX,
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};
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enum tegra_pullupdown {
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TEGRA_PUPD_NORMAL = 0,
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TEGRA_PUPD_PULL_DOWN,
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TEGRA_PUPD_PULL_UP,
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};
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enum tegra_tristate {
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TEGRA_TRI_NORMAL = 0,
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TEGRA_TRI_TRISTATE = 1,
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};
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struct tegra_pingroup_config {
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enum tegra_pingroup pingroup;
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enum tegra_mux_func func;
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enum tegra_pullupdown pupd;
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enum tegra_tristate tristate;
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};
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enum tegra_slew {
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TEGRA_SLEW_FASTEST = 0,
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TEGRA_SLEW_FAST,
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TEGRA_SLEW_SLOW,
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TEGRA_SLEW_SLOWEST,
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TEGRA_MAX_SLEW,
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};
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enum tegra_pull_strength {
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TEGRA_PULL_0 = 0,
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TEGRA_PULL_1,
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TEGRA_PULL_2,
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TEGRA_PULL_3,
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TEGRA_PULL_4,
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TEGRA_PULL_5,
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TEGRA_PULL_6,
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TEGRA_PULL_7,
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TEGRA_PULL_8,
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TEGRA_PULL_9,
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TEGRA_PULL_10,
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TEGRA_PULL_11,
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TEGRA_PULL_12,
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TEGRA_PULL_13,
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TEGRA_PULL_14,
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TEGRA_PULL_15,
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TEGRA_PULL_16,
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TEGRA_PULL_17,
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TEGRA_PULL_18,
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TEGRA_PULL_19,
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TEGRA_PULL_20,
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TEGRA_PULL_21,
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TEGRA_PULL_22,
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TEGRA_PULL_23,
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TEGRA_PULL_24,
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TEGRA_PULL_25,
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TEGRA_PULL_26,
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TEGRA_PULL_27,
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TEGRA_PULL_28,
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TEGRA_PULL_29,
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TEGRA_PULL_30,
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TEGRA_PULL_31,
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TEGRA_MAX_PULL,
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};
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enum tegra_drive_pingroup {
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TEGRA_DRIVE_PINGROUP_AO1 = 0,
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TEGRA_DRIVE_PINGROUP_AO2,
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TEGRA_DRIVE_PINGROUP_AT1,
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TEGRA_DRIVE_PINGROUP_AT2,
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TEGRA_DRIVE_PINGROUP_CDEV1,
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TEGRA_DRIVE_PINGROUP_CDEV2,
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TEGRA_DRIVE_PINGROUP_CSUS,
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TEGRA_DRIVE_PINGROUP_DAP1,
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TEGRA_DRIVE_PINGROUP_DAP2,
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TEGRA_DRIVE_PINGROUP_DAP3,
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TEGRA_DRIVE_PINGROUP_DAP4,
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TEGRA_DRIVE_PINGROUP_DBG,
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TEGRA_DRIVE_PINGROUP_LCD1,
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TEGRA_DRIVE_PINGROUP_LCD2,
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TEGRA_DRIVE_PINGROUP_SDMMC2,
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TEGRA_DRIVE_PINGROUP_SDMMC3,
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TEGRA_DRIVE_PINGROUP_SPI,
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TEGRA_DRIVE_PINGROUP_UAA,
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TEGRA_DRIVE_PINGROUP_UAB,
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TEGRA_DRIVE_PINGROUP_UART2,
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TEGRA_DRIVE_PINGROUP_UART3,
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TEGRA_DRIVE_PINGROUP_VI1,
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TEGRA_DRIVE_PINGROUP_VI2,
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TEGRA_DRIVE_PINGROUP_XM2A,
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TEGRA_DRIVE_PINGROUP_XM2C,
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TEGRA_DRIVE_PINGROUP_XM2D,
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TEGRA_DRIVE_PINGROUP_XM2CLK,
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TEGRA_DRIVE_PINGROUP_MEMCOMP,
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TEGRA_MAX_DRIVE_PINGROUP,
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};
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enum tegra_drive {
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TEGRA_DRIVE_DIV_8 = 0,
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TEGRA_DRIVE_DIV_4,
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TEGRA_DRIVE_DIV_2,
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TEGRA_DRIVE_DIV_1,
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TEGRA_MAX_DRIVE,
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};
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enum tegra_hsm {
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TEGRA_HSM_DISABLE = 0,
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TEGRA_HSM_ENABLE,
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};
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enum tegra_schmitt {
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TEGRA_SCHMITT_DISABLE = 0,
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TEGRA_SCHMITT_ENABLE,
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};
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struct tegra_drive_pingroup_config {
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enum tegra_drive_pingroup pingroup;
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enum tegra_hsm hsm;
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enum tegra_schmitt schmitt;
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enum tegra_drive drive;
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enum tegra_pull_strength pull_down;
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enum tegra_pull_strength pull_up;
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enum tegra_slew slew_rising;
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enum tegra_slew slew_falling;
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};
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int tegra_pinmux_set_func(enum tegra_pingroup pg, enum tegra_mux_func func);
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int tegra_pinmux_set_tristate(enum tegra_pingroup pg, enum tegra_tristate tristate);
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int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg, enum tegra_pullupdown pupd);
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void tegra_pinmux_config_pingroup(enum tegra_pingroup pingroup,
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enum tegra_mux_func func, enum tegra_pullupdown pupd,
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enum tegra_tristate tristate);
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void tegra_pinmux_config_table(struct tegra_pingroup_config *config, int len);
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void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
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int len);
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#endif
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