461 строка
12 KiB
C
461 строка
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright (C) 2020 Daniel Palmer<daniel@thingy.jp> */
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#include <linux/bitops.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/gpio/driver.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/gpio/msc313-gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#define DRIVER_NAME "gpio-msc313"
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#define MSC313_GPIO_IN BIT(0)
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#define MSC313_GPIO_OUT BIT(4)
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#define MSC313_GPIO_OEN BIT(5)
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/*
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* These bits need to be saved to correctly restore the
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* gpio state when resuming from suspend to memory.
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*/
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#define MSC313_GPIO_BITSTOSAVE (MSC313_GPIO_OUT | MSC313_GPIO_OEN)
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/* pad names for fuart, same for all SoCs so far */
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#define MSC313_PINNAME_FUART_RX "fuart_rx"
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#define MSC313_PINNAME_FUART_TX "fuart_tx"
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#define MSC313_PINNAME_FUART_CTS "fuart_cts"
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#define MSC313_PINNAME_FUART_RTS "fuart_rts"
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/* pad names for sr, mercury5 is different */
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#define MSC313_PINNAME_SR_IO2 "sr_io2"
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#define MSC313_PINNAME_SR_IO3 "sr_io3"
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#define MSC313_PINNAME_SR_IO4 "sr_io4"
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#define MSC313_PINNAME_SR_IO5 "sr_io5"
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#define MSC313_PINNAME_SR_IO6 "sr_io6"
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#define MSC313_PINNAME_SR_IO7 "sr_io7"
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#define MSC313_PINNAME_SR_IO8 "sr_io8"
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#define MSC313_PINNAME_SR_IO9 "sr_io9"
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#define MSC313_PINNAME_SR_IO10 "sr_io10"
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#define MSC313_PINNAME_SR_IO11 "sr_io11"
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#define MSC313_PINNAME_SR_IO12 "sr_io12"
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#define MSC313_PINNAME_SR_IO13 "sr_io13"
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#define MSC313_PINNAME_SR_IO14 "sr_io14"
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#define MSC313_PINNAME_SR_IO15 "sr_io15"
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#define MSC313_PINNAME_SR_IO16 "sr_io16"
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#define MSC313_PINNAME_SR_IO17 "sr_io17"
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/* pad names for sd, same for all SoCs so far */
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#define MSC313_PINNAME_SD_CLK "sd_clk"
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#define MSC313_PINNAME_SD_CMD "sd_cmd"
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#define MSC313_PINNAME_SD_D0 "sd_d0"
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#define MSC313_PINNAME_SD_D1 "sd_d1"
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#define MSC313_PINNAME_SD_D2 "sd_d2"
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#define MSC313_PINNAME_SD_D3 "sd_d3"
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/* pad names for i2c1, same for all SoCs so for */
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#define MSC313_PINNAME_I2C1_SCL "i2c1_scl"
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#define MSC313_PINNAME_I2C1_SCA "i2c1_sda"
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/* pad names for spi0, same for all SoCs so far */
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#define MSC313_PINNAME_SPI0_CZ "spi0_cz"
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#define MSC313_PINNAME_SPI0_CK "spi0_ck"
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#define MSC313_PINNAME_SPI0_DI "spi0_di"
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#define MSC313_PINNAME_SPI0_DO "spi0_do"
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#define FUART_NAMES \
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MSC313_PINNAME_FUART_RX, \
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MSC313_PINNAME_FUART_TX, \
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MSC313_PINNAME_FUART_CTS, \
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MSC313_PINNAME_FUART_RTS
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#define OFF_FUART_RX 0x50
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#define OFF_FUART_TX 0x54
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#define OFF_FUART_CTS 0x58
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#define OFF_FUART_RTS 0x5c
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#define FUART_OFFSETS \
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OFF_FUART_RX, \
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OFF_FUART_TX, \
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OFF_FUART_CTS, \
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OFF_FUART_RTS
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#define SR_NAMES \
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MSC313_PINNAME_SR_IO2, \
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MSC313_PINNAME_SR_IO3, \
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MSC313_PINNAME_SR_IO4, \
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MSC313_PINNAME_SR_IO5, \
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MSC313_PINNAME_SR_IO6, \
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MSC313_PINNAME_SR_IO7, \
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MSC313_PINNAME_SR_IO8, \
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MSC313_PINNAME_SR_IO9, \
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MSC313_PINNAME_SR_IO10, \
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MSC313_PINNAME_SR_IO11, \
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MSC313_PINNAME_SR_IO12, \
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MSC313_PINNAME_SR_IO13, \
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MSC313_PINNAME_SR_IO14, \
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MSC313_PINNAME_SR_IO15, \
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MSC313_PINNAME_SR_IO16, \
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MSC313_PINNAME_SR_IO17
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#define OFF_SR_IO2 0x88
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#define OFF_SR_IO3 0x8c
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#define OFF_SR_IO4 0x90
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#define OFF_SR_IO5 0x94
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#define OFF_SR_IO6 0x98
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#define OFF_SR_IO7 0x9c
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#define OFF_SR_IO8 0xa0
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#define OFF_SR_IO9 0xa4
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#define OFF_SR_IO10 0xa8
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#define OFF_SR_IO11 0xac
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#define OFF_SR_IO12 0xb0
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#define OFF_SR_IO13 0xb4
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#define OFF_SR_IO14 0xb8
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#define OFF_SR_IO15 0xbc
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#define OFF_SR_IO16 0xc0
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#define OFF_SR_IO17 0xc4
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#define SR_OFFSETS \
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OFF_SR_IO2, \
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OFF_SR_IO3, \
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OFF_SR_IO4, \
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OFF_SR_IO5, \
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OFF_SR_IO6, \
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OFF_SR_IO7, \
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OFF_SR_IO8, \
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OFF_SR_IO9, \
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OFF_SR_IO10, \
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OFF_SR_IO11, \
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OFF_SR_IO12, \
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OFF_SR_IO13, \
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OFF_SR_IO14, \
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OFF_SR_IO15, \
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OFF_SR_IO16, \
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OFF_SR_IO17
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#define SD_NAMES \
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MSC313_PINNAME_SD_CLK, \
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MSC313_PINNAME_SD_CMD, \
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MSC313_PINNAME_SD_D0, \
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MSC313_PINNAME_SD_D1, \
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MSC313_PINNAME_SD_D2, \
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MSC313_PINNAME_SD_D3
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#define OFF_SD_CLK 0x140
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#define OFF_SD_CMD 0x144
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#define OFF_SD_D0 0x148
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#define OFF_SD_D1 0x14c
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#define OFF_SD_D2 0x150
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#define OFF_SD_D3 0x154
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#define SD_OFFSETS \
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OFF_SD_CLK, \
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OFF_SD_CMD, \
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OFF_SD_D0, \
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OFF_SD_D1, \
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OFF_SD_D2, \
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OFF_SD_D3
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#define I2C1_NAMES \
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MSC313_PINNAME_I2C1_SCL, \
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MSC313_PINNAME_I2C1_SCA
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#define OFF_I2C1_SCL 0x188
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#define OFF_I2C1_SCA 0x18c
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#define I2C1_OFFSETS \
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OFF_I2C1_SCL, \
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OFF_I2C1_SCA
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#define SPI0_NAMES \
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MSC313_PINNAME_SPI0_CZ, \
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MSC313_PINNAME_SPI0_CK, \
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MSC313_PINNAME_SPI0_DI, \
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MSC313_PINNAME_SPI0_DO
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#define OFF_SPI0_CZ 0x1c0
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#define OFF_SPI0_CK 0x1c4
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#define OFF_SPI0_DI 0x1c8
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#define OFF_SPI0_DO 0x1cc
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#define SPI0_OFFSETS \
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OFF_SPI0_CZ, \
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OFF_SPI0_CK, \
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OFF_SPI0_DI, \
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OFF_SPI0_DO
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struct msc313_gpio_data {
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const char * const *names;
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const unsigned int *offsets;
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const unsigned int num;
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};
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#define MSC313_GPIO_CHIPDATA(_chip) \
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static const struct msc313_gpio_data _chip##_data = { \
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.names = _chip##_names, \
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.offsets = _chip##_offsets, \
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.num = ARRAY_SIZE(_chip##_offsets), \
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}
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#ifdef CONFIG_MACH_INFINITY
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static const char * const msc313_names[] = {
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FUART_NAMES,
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SR_NAMES,
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SD_NAMES,
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I2C1_NAMES,
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SPI0_NAMES,
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};
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static const unsigned int msc313_offsets[] = {
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FUART_OFFSETS,
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SR_OFFSETS,
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SD_OFFSETS,
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I2C1_OFFSETS,
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SPI0_OFFSETS,
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};
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MSC313_GPIO_CHIPDATA(msc313);
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#endif
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struct msc313_gpio {
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void __iomem *base;
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const struct msc313_gpio_data *gpio_data;
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u8 *saved;
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};
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static void msc313_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
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{
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struct msc313_gpio *gpio = gpiochip_get_data(chip);
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u8 gpioreg = readb_relaxed(gpio->base + gpio->gpio_data->offsets[offset]);
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if (value)
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gpioreg |= MSC313_GPIO_OUT;
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else
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gpioreg &= ~MSC313_GPIO_OUT;
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writeb_relaxed(gpioreg, gpio->base + gpio->gpio_data->offsets[offset]);
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}
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static int msc313_gpio_get(struct gpio_chip *chip, unsigned int offset)
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{
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struct msc313_gpio *gpio = gpiochip_get_data(chip);
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return readb_relaxed(gpio->base + gpio->gpio_data->offsets[offset]) & MSC313_GPIO_IN;
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}
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static int msc313_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
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{
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struct msc313_gpio *gpio = gpiochip_get_data(chip);
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u8 gpioreg = readb_relaxed(gpio->base + gpio->gpio_data->offsets[offset]);
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gpioreg |= MSC313_GPIO_OEN;
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writeb_relaxed(gpioreg, gpio->base + gpio->gpio_data->offsets[offset]);
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return 0;
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}
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static int msc313_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value)
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{
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struct msc313_gpio *gpio = gpiochip_get_data(chip);
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u8 gpioreg = readb_relaxed(gpio->base + gpio->gpio_data->offsets[offset]);
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gpioreg &= ~MSC313_GPIO_OEN;
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if (value)
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gpioreg |= MSC313_GPIO_OUT;
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else
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gpioreg &= ~MSC313_GPIO_OUT;
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writeb_relaxed(gpioreg, gpio->base + gpio->gpio_data->offsets[offset]);
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return 0;
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}
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/*
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* The interrupt handling happens in the parent interrupt controller,
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* we don't do anything here.
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*/
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static struct irq_chip msc313_gpio_irqchip = {
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.name = "GPIO",
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.irq_eoi = irq_chip_eoi_parent,
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_set_type = irq_chip_set_type_parent,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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};
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/*
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* The parent interrupt controller needs the GIC interrupt type set to GIC_SPI
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* so we need to provide the fwspec. Essentially gpiochip_populate_parent_fwspec_twocell
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* that puts GIC_SPI into the first cell.
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*/
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static void *msc313_gpio_populate_parent_fwspec(struct gpio_chip *gc,
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unsigned int parent_hwirq,
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unsigned int parent_type)
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{
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struct irq_fwspec *fwspec;
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fwspec = kmalloc(sizeof(*fwspec), GFP_KERNEL);
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if (!fwspec)
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return NULL;
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fwspec->fwnode = gc->irq.parent_domain->fwnode;
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fwspec->param_count = 3;
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fwspec->param[0] = GIC_SPI;
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fwspec->param[1] = parent_hwirq;
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fwspec->param[2] = parent_type;
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return fwspec;
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}
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static int msc313e_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
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unsigned int child,
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unsigned int child_type,
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unsigned int *parent,
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unsigned int *parent_type)
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{
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struct msc313_gpio *priv = gpiochip_get_data(chip);
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unsigned int offset = priv->gpio_data->offsets[child];
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/*
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* only the spi0 pins have interrupts on the parent
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* on all of the known chips and so far they are all
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* mapped to the same place
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*/
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if (offset >= OFF_SPI0_CZ && offset <= OFF_SPI0_DO) {
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*parent_type = child_type;
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*parent = ((offset - OFF_SPI0_CZ) >> 2) + 28;
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return 0;
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}
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return -EINVAL;
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}
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static int msc313_gpio_probe(struct platform_device *pdev)
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{
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const struct msc313_gpio_data *match_data;
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struct msc313_gpio *gpio;
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struct gpio_chip *gpiochip;
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struct gpio_irq_chip *gpioirqchip;
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struct irq_domain *parent_domain;
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struct device_node *parent_node;
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struct device *dev = &pdev->dev;
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int ret;
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match_data = of_device_get_match_data(dev);
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if (!match_data)
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return -EINVAL;
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parent_node = of_irq_find_parent(dev->of_node);
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if (!parent_node)
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return -ENODEV;
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parent_domain = irq_find_host(parent_node);
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if (!parent_domain)
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return -ENODEV;
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gpio = devm_kzalloc(dev, sizeof(*gpio), GFP_KERNEL);
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if (!gpio)
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return -ENOMEM;
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gpio->gpio_data = match_data;
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gpio->saved = devm_kcalloc(dev, gpio->gpio_data->num, sizeof(*gpio->saved), GFP_KERNEL);
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if (!gpio->saved)
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return -ENOMEM;
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gpio->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(gpio->base))
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return PTR_ERR(gpio->base);
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platform_set_drvdata(pdev, gpio);
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gpiochip = devm_kzalloc(dev, sizeof(*gpiochip), GFP_KERNEL);
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if (!gpiochip)
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return -ENOMEM;
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gpiochip->label = DRIVER_NAME;
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gpiochip->parent = dev;
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gpiochip->request = gpiochip_generic_request;
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gpiochip->free = gpiochip_generic_free;
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gpiochip->direction_input = msc313_gpio_direction_input;
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gpiochip->direction_output = msc313_gpio_direction_output;
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gpiochip->get = msc313_gpio_get;
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gpiochip->set = msc313_gpio_set;
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gpiochip->base = -1;
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gpiochip->ngpio = gpio->gpio_data->num;
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gpiochip->names = gpio->gpio_data->names;
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gpioirqchip = &gpiochip->irq;
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gpioirqchip->chip = &msc313_gpio_irqchip;
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gpioirqchip->fwnode = of_node_to_fwnode(dev->of_node);
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gpioirqchip->parent_domain = parent_domain;
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gpioirqchip->child_to_parent_hwirq = msc313e_gpio_child_to_parent_hwirq;
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gpioirqchip->populate_parent_alloc_arg = msc313_gpio_populate_parent_fwspec;
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gpioirqchip->handler = handle_bad_irq;
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gpioirqchip->default_type = IRQ_TYPE_NONE;
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ret = devm_gpiochip_add_data(dev, gpiochip, gpio);
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return ret;
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}
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static int msc313_gpio_remove(struct platform_device *pdev)
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{
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return 0;
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}
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static const struct of_device_id msc313_gpio_of_match[] = {
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#ifdef CONFIG_MACH_INFINITY
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{
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.compatible = "mstar,msc313-gpio",
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.data = &msc313_data,
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},
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#endif
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{ }
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};
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/*
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* The GPIO controller loses the state of the registers when the
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* SoC goes into suspend to memory mode so we need to save some
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* of the register bits before suspending and put it back when resuming
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*/
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static int __maybe_unused msc313_gpio_suspend(struct device *dev)
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{
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struct msc313_gpio *gpio = dev_get_drvdata(dev);
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int i;
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for (i = 0; i < gpio->gpio_data->num; i++)
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gpio->saved[i] = readb_relaxed(gpio->base + gpio->gpio_data->offsets[i]) & MSC313_GPIO_BITSTOSAVE;
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return 0;
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}
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static int __maybe_unused msc313_gpio_resume(struct device *dev)
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{
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struct msc313_gpio *gpio = dev_get_drvdata(dev);
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int i;
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for (i = 0; i < gpio->gpio_data->num; i++)
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writeb_relaxed(gpio->saved[i], gpio->base + gpio->gpio_data->offsets[i]);
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return 0;
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}
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static SIMPLE_DEV_PM_OPS(msc313_gpio_ops, msc313_gpio_suspend, msc313_gpio_resume);
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static struct platform_driver msc313_gpio_driver = {
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.driver = {
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.name = DRIVER_NAME,
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.of_match_table = msc313_gpio_of_match,
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.pm = &msc313_gpio_ops,
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},
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.probe = msc313_gpio_probe,
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.remove = msc313_gpio_remove,
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};
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builtin_platform_driver(msc313_gpio_driver);
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