334 строки
9.4 KiB
C
334 строки
9.4 KiB
C
/*
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* Intel CPU Microcode Update Driver for Linux
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*
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* Copyright (C) 2000-2006 Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
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* 2006 Shaohua Li <shaohua.li@intel.com>
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*
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* This driver allows to upgrade microcode on Intel processors
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* belonging to IA-32 family - PentiumPro, Pentium II,
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* Pentium III, Xeon, Pentium 4, etc.
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*
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* Reference: Section 8.11 of Volume 3a, IA-32 Intel? Architecture
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* Software Developer's Manual
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* Order Number 253668 or free download from:
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*
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* http://developer.intel.com/Assets/PDF/manual/253668.pdf
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*
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* For more information, go to http://www.urbanmyth.org/microcode
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* 1.0 16 Feb 2000, Tigran Aivazian <tigran@sco.com>
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* Initial release.
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* 1.01 18 Feb 2000, Tigran Aivazian <tigran@sco.com>
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* Added read() support + cleanups.
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* 1.02 21 Feb 2000, Tigran Aivazian <tigran@sco.com>
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* Added 'device trimming' support. open(O_WRONLY) zeroes
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* and frees the saved copy of applied microcode.
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* 1.03 29 Feb 2000, Tigran Aivazian <tigran@sco.com>
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* Made to use devfs (/dev/cpu/microcode) + cleanups.
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* 1.04 06 Jun 2000, Simon Trimmer <simon@veritas.com>
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* Added misc device support (now uses both devfs and misc).
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* Added MICROCODE_IOCFREE ioctl to clear memory.
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* 1.05 09 Jun 2000, Simon Trimmer <simon@veritas.com>
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* Messages for error cases (non Intel & no suitable microcode).
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* 1.06 03 Aug 2000, Tigran Aivazian <tigran@veritas.com>
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* Removed ->release(). Removed exclusive open and status bitmap.
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* Added microcode_rwsem to serialize read()/write()/ioctl().
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* Removed global kernel lock usage.
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* 1.07 07 Sep 2000, Tigran Aivazian <tigran@veritas.com>
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* Write 0 to 0x8B msr and then cpuid before reading revision,
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* so that it works even if there were no update done by the
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* BIOS. Otherwise, reading from 0x8B gives junk (which happened
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* to be 0 on my machine which is why it worked even when I
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* disabled update by the BIOS)
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* Thanks to Eric W. Biederman <ebiederman@lnxi.com> for the fix.
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* 1.08 11 Dec 2000, Richard Schaal <richard.schaal@intel.com> and
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* Tigran Aivazian <tigran@veritas.com>
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* Intel Pentium 4 processor support and bugfixes.
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* 1.09 30 Oct 2001, Tigran Aivazian <tigran@veritas.com>
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* Bugfix for HT (Hyper-Threading) enabled processors
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* whereby processor resources are shared by all logical processors
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* in a single CPU package.
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* 1.10 28 Feb 2002 Asit K Mallick <asit.k.mallick@intel.com> and
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* Tigran Aivazian <tigran@veritas.com>,
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* Serialize updates as required on HT processors due to
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* speculative nature of implementation.
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* 1.11 22 Mar 2002 Tigran Aivazian <tigran@veritas.com>
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* Fix the panic when writing zero-length microcode chunk.
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* 1.12 29 Sep 2003 Nitin Kamble <nitin.a.kamble@intel.com>,
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* Jun Nakajima <jun.nakajima@intel.com>
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* Support for the microcode updates in the new format.
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* 1.13 10 Oct 2003 Tigran Aivazian <tigran@veritas.com>
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* Removed ->read() method and obsoleted MICROCODE_IOCFREE ioctl
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* because we no longer hold a copy of applied microcode
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* in kernel memory.
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* 1.14 25 Jun 2004 Tigran Aivazian <tigran@veritas.com>
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* Fix sigmatch() macro to handle old CPUs with pf == 0.
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* Thanks to Stuart Swales for pointing out this bug.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/firmware.h>
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#include <linux/uaccess.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/vmalloc.h>
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#include <asm/microcode_intel.h>
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#include <asm/processor.h>
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#include <asm/msr.h>
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MODULE_DESCRIPTION("Microcode Update Driver");
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MODULE_AUTHOR("Tigran Aivazian <tigran@aivazian.fsnet.co.uk>");
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MODULE_LICENSE("GPL");
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static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
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{
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struct cpuinfo_x86 *c = &cpu_data(cpu_num);
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unsigned int val[2];
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memset(csig, 0, sizeof(*csig));
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csig->sig = cpuid_eax(0x00000001);
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if ((c->x86_model >= 5) || (c->x86 > 6)) {
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/* get processor flags from MSR 0x17 */
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rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
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csig->pf = 1 << ((val[1] >> 18) & 7);
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}
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csig->rev = c->microcode;
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pr_info("CPU%d sig=0x%x, pf=0x%x, revision=0x%x\n",
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cpu_num, csig->sig, csig->pf, csig->rev);
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return 0;
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}
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/*
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* return 0 - no update found
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* return 1 - found update
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*/
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static int get_matching_mc(struct microcode_intel *mc_intel, int cpu)
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{
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struct cpu_signature cpu_sig;
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unsigned int csig, cpf, crev;
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collect_cpu_info(cpu, &cpu_sig);
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csig = cpu_sig.sig;
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cpf = cpu_sig.pf;
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crev = cpu_sig.rev;
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return get_matching_microcode(csig, cpf, mc_intel, crev);
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}
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int apply_microcode(int cpu)
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{
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struct microcode_intel *mc_intel;
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struct ucode_cpu_info *uci;
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unsigned int val[2];
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int cpu_num = raw_smp_processor_id();
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struct cpuinfo_x86 *c = &cpu_data(cpu_num);
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uci = ucode_cpu_info + cpu;
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mc_intel = uci->mc;
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/* We should bind the task to the CPU */
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BUG_ON(cpu_num != cpu);
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if (mc_intel == NULL)
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return 0;
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/*
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* Microcode on this CPU could be updated earlier. Only apply the
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* microcode patch in mc_intel when it is newer than the one on this
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* CPU.
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*/
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if (get_matching_mc(mc_intel, cpu) == 0)
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return 0;
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/* write microcode via MSR 0x79 */
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wrmsr(MSR_IA32_UCODE_WRITE,
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(unsigned long) mc_intel->bits,
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(unsigned long) mc_intel->bits >> 16 >> 16);
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wrmsr(MSR_IA32_UCODE_REV, 0, 0);
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/* As documented in the SDM: Do a CPUID 1 here */
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sync_core();
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/* get the current revision from MSR 0x8B */
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rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
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if (val[1] != mc_intel->hdr.rev) {
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pr_err("CPU%d update to revision 0x%x failed\n",
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cpu_num, mc_intel->hdr.rev);
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return -1;
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}
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pr_info("CPU%d updated to revision 0x%x, date = %04x-%02x-%02x\n",
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cpu_num, val[1],
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mc_intel->hdr.date & 0xffff,
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mc_intel->hdr.date >> 24,
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(mc_intel->hdr.date >> 16) & 0xff);
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uci->cpu_sig.rev = val[1];
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c->microcode = val[1];
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return 0;
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}
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static enum ucode_state generic_load_microcode(int cpu, void *data, size_t size,
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int (*get_ucode_data)(void *, const void *, size_t))
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{
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struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
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u8 *ucode_ptr = data, *new_mc = NULL, *mc = NULL;
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int new_rev = uci->cpu_sig.rev;
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unsigned int leftover = size;
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enum ucode_state state = UCODE_OK;
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unsigned int curr_mc_size = 0;
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unsigned int csig, cpf;
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while (leftover) {
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struct microcode_header_intel mc_header;
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unsigned int mc_size;
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if (get_ucode_data(&mc_header, ucode_ptr, sizeof(mc_header)))
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break;
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mc_size = get_totalsize(&mc_header);
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if (!mc_size || mc_size > leftover) {
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pr_err("error! Bad data in microcode data file\n");
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break;
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}
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/* For performance reasons, reuse mc area when possible */
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if (!mc || mc_size > curr_mc_size) {
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vfree(mc);
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mc = vmalloc(mc_size);
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if (!mc)
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break;
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curr_mc_size = mc_size;
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}
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if (get_ucode_data(mc, ucode_ptr, mc_size) ||
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microcode_sanity_check(mc, 1) < 0) {
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break;
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}
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csig = uci->cpu_sig.sig;
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cpf = uci->cpu_sig.pf;
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if (get_matching_microcode(csig, cpf, mc, new_rev)) {
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vfree(new_mc);
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new_rev = mc_header.rev;
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new_mc = mc;
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mc = NULL; /* trigger new vmalloc */
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}
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ucode_ptr += mc_size;
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leftover -= mc_size;
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}
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vfree(mc);
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if (leftover) {
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vfree(new_mc);
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state = UCODE_ERROR;
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goto out;
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}
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if (!new_mc) {
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state = UCODE_NFOUND;
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goto out;
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}
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vfree(uci->mc);
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uci->mc = (struct microcode_intel *)new_mc;
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/*
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* If early loading microcode is supported, save this mc into
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* permanent memory. So it will be loaded early when a CPU is hot added
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* or resumes.
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*/
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save_mc_for_early(new_mc);
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pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n",
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cpu, new_rev, uci->cpu_sig.rev);
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out:
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return state;
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}
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static int get_ucode_fw(void *to, const void *from, size_t n)
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{
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memcpy(to, from, n);
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return 0;
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}
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static enum ucode_state request_microcode_fw(int cpu, struct device *device,
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bool refresh_fw)
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{
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char name[30];
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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const struct firmware *firmware;
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enum ucode_state ret;
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sprintf(name, "intel-ucode/%02x-%02x-%02x",
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c->x86, c->x86_model, c->x86_mask);
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if (request_firmware(&firmware, name, device)) {
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pr_debug("data file %s load failed\n", name);
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return UCODE_NFOUND;
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}
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ret = generic_load_microcode(cpu, (void *)firmware->data,
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firmware->size, &get_ucode_fw);
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release_firmware(firmware);
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return ret;
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}
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static int get_ucode_user(void *to, const void *from, size_t n)
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{
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return copy_from_user(to, from, n);
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}
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static enum ucode_state
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request_microcode_user(int cpu, const void __user *buf, size_t size)
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{
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return generic_load_microcode(cpu, (void *)buf, size, &get_ucode_user);
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}
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static void microcode_fini_cpu(int cpu)
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{
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struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
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vfree(uci->mc);
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uci->mc = NULL;
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}
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static struct microcode_ops microcode_intel_ops = {
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.request_microcode_user = request_microcode_user,
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.request_microcode_fw = request_microcode_fw,
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.collect_cpu_info = collect_cpu_info,
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.apply_microcode = apply_microcode,
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.microcode_fini_cpu = microcode_fini_cpu,
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};
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struct microcode_ops * __init init_intel_microcode(void)
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{
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struct cpuinfo_x86 *c = &cpu_data(0);
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if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||
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cpu_has(c, X86_FEATURE_IA64)) {
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pr_err("Intel CPU family 0x%x not supported\n", c->x86);
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return NULL;
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}
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return µcode_intel_ops;
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}
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