478 строки
12 KiB
C
478 строки
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/pm_clock.h>
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "common.h"
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#include "gdsc.h"
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enum {
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P_BI_TCXO,
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P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD,
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P_SLEEP_CLK,
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};
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static struct pll_vco fabia_vco[] = {
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{ 249600000, 2000000000, 0 },
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};
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static const struct alpha_pll_config lpass_lpaaudio_dig_pll_config = {
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.l = 0x20,
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.alpha = 0x0,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00002067,
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.test_ctl_val = 0x40000000,
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.test_ctl_hi_val = 0x00000000,
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.user_ctl_val = 0x00005105,
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.user_ctl_hi_val = 0x00004805,
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};
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static const u8 clk_alpha_pll_regs_offset[][PLL_OFF_MAX_REGS] = {
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[CLK_ALPHA_PLL_TYPE_FABIA] = {
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[PLL_OFF_L_VAL] = 0x04,
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[PLL_OFF_CAL_L_VAL] = 0x8,
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[PLL_OFF_USER_CTL] = 0x0c,
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[PLL_OFF_USER_CTL_U] = 0x10,
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[PLL_OFF_USER_CTL_U1] = 0x14,
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[PLL_OFF_CONFIG_CTL] = 0x18,
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[PLL_OFF_CONFIG_CTL_U] = 0x1C,
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[PLL_OFF_CONFIG_CTL_U1] = 0x20,
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[PLL_OFF_TEST_CTL] = 0x24,
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[PLL_OFF_TEST_CTL_U] = 0x28,
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[PLL_OFF_STATUS] = 0x30,
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[PLL_OFF_OPMODE] = 0x38,
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[PLL_OFF_FRAC] = 0x40,
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},
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};
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static struct clk_alpha_pll lpass_lpaaudio_dig_pll = {
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.offset = 0x1000,
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.vco_table = fabia_vco,
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.num_vco = ARRAY_SIZE(fabia_vco),
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.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_FABIA],
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "lpass_lpaaudio_dig_pll",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "bi_tcxo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_fabia_ops,
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},
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},
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};
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static const struct clk_div_table
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post_div_table_lpass_lpaaudio_dig_pll_out_odd[] = {
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{ 0x5, 5 },
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{ }
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};
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static struct clk_alpha_pll_postdiv lpass_lpaaudio_dig_pll_out_odd = {
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.offset = 0x1000,
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.post_div_shift = 12,
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.post_div_table = post_div_table_lpass_lpaaudio_dig_pll_out_odd,
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.num_post_div =
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ARRAY_SIZE(post_div_table_lpass_lpaaudio_dig_pll_out_odd),
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.width = 4,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
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.clkr.hw.init = &(struct clk_init_data){
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.name = "lpass_lpaaudio_dig_pll_out_odd",
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.parent_data = &(const struct clk_parent_data){
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.hw = &lpass_lpaaudio_dig_pll.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_fabia_ops,
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},
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};
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static const struct parent_map lpass_core_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 5 },
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};
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static const struct clk_parent_data lpass_core_cc_parent_data_0[] = {
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{ .fw_name = "bi_tcxo" },
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{ .hw = &lpass_lpaaudio_dig_pll_out_odd.clkr.hw },
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};
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static const struct parent_map lpass_core_cc_parent_map_2[] = {
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{ P_BI_TCXO, 0 },
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};
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static struct clk_rcg2 core_clk_src = {
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.cmd_rcgr = 0x1d000,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = lpass_core_cc_parent_map_2,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "core_clk_src",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "bi_tcxo",
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},
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.num_parents = 1,
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.ops = &clk_rcg2_ops,
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},
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};
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static const struct freq_tbl ftbl_ext_mclk0_clk_src[] = {
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F(9600000, P_BI_TCXO, 2, 0, 0),
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F(19200000, P_BI_TCXO, 1, 0, 0),
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{ }
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};
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static const struct freq_tbl ftbl_ext_lpaif_clk_src[] = {
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F(256000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 15, 1, 32),
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F(512000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 15, 1, 16),
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F(768000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 10, 1, 16),
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F(1024000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 15, 1, 8),
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F(1536000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 10, 1, 8),
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F(2048000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 15, 1, 4),
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F(3072000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 10, 1, 4),
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F(4096000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 15, 1, 2),
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F(6144000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 10, 1, 2),
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F(8192000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 15, 0, 0),
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F(9600000, P_BI_TCXO, 2, 0, 0),
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F(12288000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 10, 0, 0),
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(24576000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 5, 0, 0),
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{ }
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};
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static struct clk_rcg2 ext_mclk0_clk_src = {
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.cmd_rcgr = 0x20000,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = lpass_core_cc_parent_map_0,
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.freq_tbl = ftbl_ext_mclk0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "ext_mclk0_clk_src",
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.parent_data = lpass_core_cc_parent_data_0,
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.num_parents = 2,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_rcg2 lpaif_pri_clk_src = {
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.cmd_rcgr = 0x10000,
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.mnd_width = 16,
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.hid_width = 5,
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.parent_map = lpass_core_cc_parent_map_0,
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.freq_tbl = ftbl_ext_lpaif_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "lpaif_pri_clk_src",
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.parent_data = lpass_core_cc_parent_data_0,
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.num_parents = 2,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_rcg2 lpaif_sec_clk_src = {
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.cmd_rcgr = 0x11000,
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.mnd_width = 16,
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.hid_width = 5,
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.parent_map = lpass_core_cc_parent_map_0,
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.freq_tbl = ftbl_ext_lpaif_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "lpaif_sec_clk_src",
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.parent_data = lpass_core_cc_parent_data_0,
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.num_parents = 2,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_branch lpass_audio_core_ext_mclk0_clk = {
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.halt_reg = 0x20014,
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.halt_check = BRANCH_HALT,
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.hwcg_reg = 0x20014,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x20014,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "lpass_audio_core_ext_mclk0_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &ext_mclk0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch lpass_audio_core_lpaif_pri_ibit_clk = {
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.halt_reg = 0x10018,
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.halt_check = BRANCH_HALT,
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.hwcg_reg = 0x10018,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x10018,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "lpass_audio_core_lpaif_pri_ibit_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &lpaif_pri_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch lpass_audio_core_lpaif_sec_ibit_clk = {
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.halt_reg = 0x11018,
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.halt_check = BRANCH_HALT,
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.hwcg_reg = 0x11018,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x11018,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "lpass_audio_core_lpaif_sec_ibit_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &lpaif_sec_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch lpass_audio_core_sysnoc_mport_core_clk = {
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.halt_reg = 0x23000,
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.halt_check = BRANCH_HALT,
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.hwcg_reg = 0x23000,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x23000,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "lpass_audio_core_sysnoc_mport_core_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &core_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_regmap *lpass_core_cc_sc7180_clocks[] = {
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[EXT_MCLK0_CLK_SRC] = &ext_mclk0_clk_src.clkr,
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[LPAIF_PRI_CLK_SRC] = &lpaif_pri_clk_src.clkr,
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[LPAIF_SEC_CLK_SRC] = &lpaif_sec_clk_src.clkr,
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[CORE_CLK_SRC] = &core_clk_src.clkr,
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[LPASS_AUDIO_CORE_EXT_MCLK0_CLK] = &lpass_audio_core_ext_mclk0_clk.clkr,
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[LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK] =
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&lpass_audio_core_lpaif_pri_ibit_clk.clkr,
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[LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK] =
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&lpass_audio_core_lpaif_sec_ibit_clk.clkr,
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[LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK] =
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&lpass_audio_core_sysnoc_mport_core_clk.clkr,
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[LPASS_LPAAUDIO_DIG_PLL] = &lpass_lpaaudio_dig_pll.clkr,
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[LPASS_LPAAUDIO_DIG_PLL_OUT_ODD] = &lpass_lpaaudio_dig_pll_out_odd.clkr,
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};
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static struct gdsc lpass_pdc_hm_gdsc = {
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.gdscr = 0x3090,
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.pd = {
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.name = "lpass_pdc_hm_gdsc",
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},
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.pwrsts = PWRSTS_OFF_ON,
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.flags = VOTABLE,
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};
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static struct gdsc lpass_audio_hm_gdsc = {
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.gdscr = 0x9090,
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.pd = {
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.name = "lpass_audio_hm_gdsc",
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},
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.pwrsts = PWRSTS_OFF_ON,
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};
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static struct gdsc lpass_core_hm_gdsc = {
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.gdscr = 0x0,
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.pd = {
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.name = "lpass_core_hm_gdsc",
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},
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.pwrsts = PWRSTS_OFF_ON,
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.flags = RETAIN_FF_ENABLE,
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};
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static struct gdsc *lpass_core_hm_sc7180_gdscs[] = {
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[LPASS_CORE_HM_GDSCR] = &lpass_core_hm_gdsc,
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};
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static struct gdsc *lpass_audio_hm_sc7180_gdscs[] = {
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[LPASS_PDC_HM_GDSCR] = &lpass_pdc_hm_gdsc,
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[LPASS_AUDIO_HM_GDSCR] = &lpass_audio_hm_gdsc,
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};
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static struct regmap_config lpass_core_cc_sc7180_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.fast_io = true,
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};
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static const struct qcom_cc_desc lpass_core_hm_sc7180_desc = {
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.config = &lpass_core_cc_sc7180_regmap_config,
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.gdscs = lpass_core_hm_sc7180_gdscs,
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.num_gdscs = ARRAY_SIZE(lpass_core_hm_sc7180_gdscs),
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};
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static const struct qcom_cc_desc lpass_core_cc_sc7180_desc = {
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.config = &lpass_core_cc_sc7180_regmap_config,
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.clks = lpass_core_cc_sc7180_clocks,
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.num_clks = ARRAY_SIZE(lpass_core_cc_sc7180_clocks),
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};
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static const struct qcom_cc_desc lpass_audio_hm_sc7180_desc = {
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.config = &lpass_core_cc_sc7180_regmap_config,
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.gdscs = lpass_audio_hm_sc7180_gdscs,
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.num_gdscs = ARRAY_SIZE(lpass_audio_hm_sc7180_gdscs),
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};
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static int lpass_core_cc_sc7180_probe(struct platform_device *pdev)
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{
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const struct qcom_cc_desc *desc;
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struct regmap *regmap;
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int ret;
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lpass_core_cc_sc7180_regmap_config.name = "lpass_audio_cc";
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desc = &lpass_audio_hm_sc7180_desc;
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ret = qcom_cc_probe_by_index(pdev, 1, desc);
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if (ret)
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return ret;
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lpass_core_cc_sc7180_regmap_config.name = "lpass_core_cc";
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regmap = qcom_cc_map(pdev, &lpass_core_cc_sc7180_desc);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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/*
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* Keep the CLK always-ON
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* LPASS_AUDIO_CORE_SYSNOC_SWAY_CORE_CLK
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*/
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regmap_update_bits(regmap, 0x24000, BIT(0), BIT(0));
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/* PLL settings */
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regmap_write(regmap, 0x1008, 0x20);
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regmap_update_bits(regmap, 0x1014, BIT(0), BIT(0));
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clk_fabia_pll_configure(&lpass_lpaaudio_dig_pll, regmap,
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&lpass_lpaaudio_dig_pll_config);
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return qcom_cc_really_probe(pdev, &lpass_core_cc_sc7180_desc, regmap);
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}
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static int lpass_hm_core_probe(struct platform_device *pdev)
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{
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const struct qcom_cc_desc *desc;
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lpass_core_cc_sc7180_regmap_config.name = "lpass_hm_core";
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desc = &lpass_core_hm_sc7180_desc;
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return qcom_cc_probe_by_index(pdev, 0, desc);
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}
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static const struct of_device_id lpass_core_cc_sc7180_match_table[] = {
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{
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.compatible = "qcom,sc7180-lpasshm",
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.data = lpass_hm_core_probe,
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},
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{
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.compatible = "qcom,sc7180-lpasscorecc",
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.data = lpass_core_cc_sc7180_probe,
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},
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{ }
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};
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MODULE_DEVICE_TABLE(of, lpass_core_cc_sc7180_match_table);
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static int lpass_core_sc7180_probe(struct platform_device *pdev)
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{
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int (*clk_probe)(struct platform_device *p);
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int ret;
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pm_runtime_enable(&pdev->dev);
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ret = pm_clk_create(&pdev->dev);
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if (ret)
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goto disable_pm_runtime;
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ret = pm_clk_add(&pdev->dev, "iface");
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to acquire iface clock\n");
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goto destroy_pm_clk;
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}
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ret = -EINVAL;
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clk_probe = of_device_get_match_data(&pdev->dev);
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if (!clk_probe)
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goto destroy_pm_clk;
|
|
|
|
ret = clk_probe(pdev);
|
|
if (ret)
|
|
goto destroy_pm_clk;
|
|
|
|
return 0;
|
|
|
|
destroy_pm_clk:
|
|
pm_clk_destroy(&pdev->dev);
|
|
|
|
disable_pm_runtime:
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct dev_pm_ops lpass_core_cc_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
|
|
};
|
|
|
|
static struct platform_driver lpass_core_cc_sc7180_driver = {
|
|
.probe = lpass_core_sc7180_probe,
|
|
.driver = {
|
|
.name = "lpass_core_cc-sc7180",
|
|
.of_match_table = lpass_core_cc_sc7180_match_table,
|
|
.pm = &lpass_core_cc_pm_ops,
|
|
},
|
|
};
|
|
|
|
static int __init lpass_core_cc_sc7180_init(void)
|
|
{
|
|
return platform_driver_register(&lpass_core_cc_sc7180_driver);
|
|
}
|
|
subsys_initcall(lpass_core_cc_sc7180_init);
|
|
|
|
static void __exit lpass_core_cc_sc7180_exit(void)
|
|
{
|
|
platform_driver_unregister(&lpass_core_cc_sc7180_driver);
|
|
}
|
|
module_exit(lpass_core_cc_sc7180_exit);
|
|
|
|
MODULE_DESCRIPTION("QTI LPASS_CORE_CC SC7180 Driver");
|
|
MODULE_LICENSE("GPL v2");
|