330 строки
8.0 KiB
C
330 строки
8.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* UFS PHY driver for Samsung SoC
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*
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* Copyright (C) 2020 Samsung Electronics Co., Ltd.
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* Author: Seungwon Jeon <essuuj@gmail.com>
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* Author: Alim Akhtar <alim.akhtar@samsung.com>
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*
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/of.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include "phy-samsung-ufs.h"
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#define for_each_phy_lane(phy, i) \
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for (i = 0; i < (phy)->lane_cnt; i++)
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#define for_each_phy_cfg(cfg) \
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for (; (cfg)->id; (cfg)++)
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#define PHY_DEF_LANE_CNT 1
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static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
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const struct samsung_ufs_phy_cfg *cfg,
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u8 lane)
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{
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enum {LANE_0, LANE_1}; /* lane index */
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switch (lane) {
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case LANE_0:
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writel(cfg->val, (phy)->reg_pma + cfg->off_0);
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break;
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case LANE_1:
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if (cfg->id == PHY_TRSV_BLK)
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writel(cfg->val, (phy)->reg_pma + cfg->off_1);
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break;
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}
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}
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static int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy)
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{
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struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
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const unsigned int timeout_us = 100000;
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const unsigned int sleep_us = 10;
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u32 val;
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int err;
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err = readl_poll_timeout(
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ufs_phy->reg_pma + PHY_APB_ADDR(PHY_PLL_LOCK_STATUS),
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val, (val & PHY_PLL_LOCK_BIT), sleep_us, timeout_us);
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if (err) {
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dev_err(ufs_phy->dev,
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"failed to get phy pll lock acquisition %d\n", err);
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goto out;
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}
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err = readl_poll_timeout(
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ufs_phy->reg_pma +
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PHY_APB_ADDR(ufs_phy->drvdata->cdr_lock_status_offset),
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val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us);
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if (err)
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dev_err(ufs_phy->dev,
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"failed to get phy cdr lock acquisition %d\n", err);
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out:
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return err;
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}
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static int samsung_ufs_phy_calibrate(struct phy *phy)
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{
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struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
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const struct samsung_ufs_phy_cfg * const *cfgs = ufs_phy->cfgs;
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const struct samsung_ufs_phy_cfg *cfg;
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int err = 0;
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int i;
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if (unlikely(ufs_phy->ufs_phy_state < CFG_PRE_INIT ||
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ufs_phy->ufs_phy_state >= CFG_TAG_MAX)) {
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dev_err(ufs_phy->dev, "invalid phy config index %d\n", ufs_phy->ufs_phy_state);
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return -EINVAL;
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}
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cfg = cfgs[ufs_phy->ufs_phy_state];
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if (!cfg)
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goto out;
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for_each_phy_cfg(cfg) {
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for_each_phy_lane(ufs_phy, i) {
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samsung_ufs_phy_config(ufs_phy, cfg, i);
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}
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}
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if (ufs_phy->ufs_phy_state == CFG_POST_PWR_HS)
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err = samsung_ufs_phy_wait_for_lock_acq(phy);
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/**
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* In Samsung ufshci, PHY need to be calibrated at different
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* stages / state mainly before Linkstartup, after Linkstartup,
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* before power mode change and after power mode change.
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* Below state machine to make sure to calibrate PHY in each
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* state. Here after configuring PHY in a given state, will
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* change the state to next state so that next state phy
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* calibration value can be programed
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*/
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out:
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switch (ufs_phy->ufs_phy_state) {
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case CFG_PRE_INIT:
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ufs_phy->ufs_phy_state = CFG_POST_INIT;
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break;
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case CFG_POST_INIT:
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ufs_phy->ufs_phy_state = CFG_PRE_PWR_HS;
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break;
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case CFG_PRE_PWR_HS:
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ufs_phy->ufs_phy_state = CFG_POST_PWR_HS;
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break;
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case CFG_POST_PWR_HS:
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/* Change back to INIT state */
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ufs_phy->ufs_phy_state = CFG_PRE_INIT;
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break;
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default:
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dev_err(ufs_phy->dev, "wrong state for phy calibration\n");
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}
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return err;
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}
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static int samsung_ufs_phy_clks_init(struct samsung_ufs_phy *phy)
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{
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int i;
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const struct samsung_ufs_phy_drvdata *drvdata = phy->drvdata;
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int num_clks = drvdata->num_clks;
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phy->clks = devm_kcalloc(phy->dev, num_clks, sizeof(*phy->clks),
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GFP_KERNEL);
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if (!phy->clks)
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return -ENOMEM;
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for (i = 0; i < num_clks; i++)
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phy->clks[i].id = drvdata->clk_list[i];
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return devm_clk_bulk_get(phy->dev, num_clks, phy->clks);
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}
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static int samsung_ufs_phy_init(struct phy *phy)
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{
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struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy);
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ss_phy->lane_cnt = phy->attrs.bus_width;
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ss_phy->ufs_phy_state = CFG_PRE_INIT;
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return 0;
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}
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static int samsung_ufs_phy_power_on(struct phy *phy)
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{
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struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy);
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int ret;
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samsung_ufs_phy_ctrl_isol(ss_phy, false);
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ret = clk_bulk_prepare_enable(ss_phy->drvdata->num_clks, ss_phy->clks);
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if (ret) {
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dev_err(ss_phy->dev, "failed to enable ufs phy clocks\n");
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return ret;
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}
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if (ss_phy->ufs_phy_state == CFG_PRE_INIT) {
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ret = samsung_ufs_phy_calibrate(phy);
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if (ret)
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dev_err(ss_phy->dev, "ufs phy calibration failed\n");
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}
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return ret;
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}
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static int samsung_ufs_phy_power_off(struct phy *phy)
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{
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struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy);
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clk_bulk_disable_unprepare(ss_phy->drvdata->num_clks, ss_phy->clks);
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samsung_ufs_phy_ctrl_isol(ss_phy, true);
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return 0;
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}
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static int samsung_ufs_phy_set_mode(struct phy *generic_phy,
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enum phy_mode mode, int submode)
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{
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struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(generic_phy);
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ss_phy->mode = PHY_MODE_INVALID;
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if (mode > 0)
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ss_phy->mode = mode;
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return 0;
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}
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static int samsung_ufs_phy_exit(struct phy *phy)
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{
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struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy);
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ss_phy->ufs_phy_state = CFG_TAG_MAX;
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return 0;
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}
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static const struct phy_ops samsung_ufs_phy_ops = {
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.init = samsung_ufs_phy_init,
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.exit = samsung_ufs_phy_exit,
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.power_on = samsung_ufs_phy_power_on,
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.power_off = samsung_ufs_phy_power_off,
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.calibrate = samsung_ufs_phy_calibrate,
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.set_mode = samsung_ufs_phy_set_mode,
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.owner = THIS_MODULE,
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};
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static const struct of_device_id samsung_ufs_phy_match[];
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static int samsung_ufs_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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const struct of_device_id *match;
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struct samsung_ufs_phy *phy;
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struct phy *gen_phy;
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struct phy_provider *phy_provider;
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const struct samsung_ufs_phy_drvdata *drvdata;
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u32 isol_offset;
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int err = 0;
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match = of_match_node(samsung_ufs_phy_match, dev->of_node);
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if (!match) {
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err = -EINVAL;
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dev_err(dev, "failed to get match_node\n");
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goto out;
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}
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phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
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if (!phy) {
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err = -ENOMEM;
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goto out;
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}
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phy->reg_pma = devm_platform_ioremap_resource_byname(pdev, "phy-pma");
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if (IS_ERR(phy->reg_pma)) {
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err = PTR_ERR(phy->reg_pma);
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goto out;
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}
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phy->reg_pmu = syscon_regmap_lookup_by_phandle(
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dev->of_node, "samsung,pmu-syscon");
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if (IS_ERR(phy->reg_pmu)) {
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err = PTR_ERR(phy->reg_pmu);
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dev_err(dev, "failed syscon remap for pmu\n");
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goto out;
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}
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gen_phy = devm_phy_create(dev, NULL, &samsung_ufs_phy_ops);
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if (IS_ERR(gen_phy)) {
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err = PTR_ERR(gen_phy);
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dev_err(dev, "failed to create PHY for ufs-phy\n");
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goto out;
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}
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drvdata = match->data;
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phy->dev = dev;
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phy->drvdata = drvdata;
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phy->cfgs = drvdata->cfgs;
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memcpy(&phy->isol, &drvdata->isol, sizeof(phy->isol));
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if (!of_property_read_u32_index(dev->of_node, "samsung,pmu-syscon", 1,
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&isol_offset))
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phy->isol.offset = isol_offset;
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phy->lane_cnt = PHY_DEF_LANE_CNT;
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err = samsung_ufs_phy_clks_init(phy);
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if (err) {
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dev_err(dev, "failed to get phy clocks\n");
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goto out;
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}
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phy_set_drvdata(gen_phy, phy);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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if (IS_ERR(phy_provider)) {
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err = PTR_ERR(phy_provider);
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dev_err(dev, "failed to register phy-provider\n");
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goto out;
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}
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out:
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return err;
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}
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static const struct of_device_id samsung_ufs_phy_match[] = {
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{
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.compatible = "samsung,exynos7-ufs-phy",
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.data = &exynos7_ufs_phy,
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}, {
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.compatible = "samsung,exynosautov9-ufs-phy",
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.data = &exynosautov9_ufs_phy,
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}, {
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.compatible = "tesla,fsd-ufs-phy",
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.data = &fsd_ufs_phy,
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, samsung_ufs_phy_match);
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static struct platform_driver samsung_ufs_phy_driver = {
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.probe = samsung_ufs_phy_probe,
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.driver = {
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.name = "samsung-ufs-phy",
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.of_match_table = samsung_ufs_phy_match,
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},
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};
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module_platform_driver(samsung_ufs_phy_driver);
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MODULE_DESCRIPTION("Samsung SoC UFS PHY Driver");
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MODULE_AUTHOR("Seungwon Jeon <essuuj@gmail.com>");
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MODULE_AUTHOR("Alim Akhtar <alim.akhtar@samsung.com>");
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MODULE_LICENSE("GPL v2");
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