457 строки
12 KiB
C
457 строки
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* pata_optidma.c - Opti DMA PATA for new ATA layer
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* (C) 2006 Red Hat Inc
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*
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* The Opti DMA controllers are related to the older PIO PCI controllers
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* and indeed the VLB ones. The main differences are that the timing
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* numbers are now based off PCI clocks not VLB and differ, and that
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* MWDMA is supported.
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*
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* This driver should support Viper-N+, FireStar, FireStar Plus.
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*
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* These devices support virtual DMA for read (aka the CS5520). Later
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* chips support UDMA33, but only if the rest of the board logic does,
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* so you have to get this right. We don't support the virtual DMA
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* but we do handle UDMA.
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*
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* Bits that are worth knowing
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* Most control registers are shadowed into I/O registers
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* 0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz
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* Virtual DMA registers *move* between rev 0x02 and rev 0x10
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* UDMA requires a 66MHz FSB
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_optidma"
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#define DRV_VERSION "0.3.2"
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enum {
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READ_REG = 0, /* index of Read cycle timing register */
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WRITE_REG = 1, /* index of Write cycle timing register */
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CNTRL_REG = 3, /* index of Control register */
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STRAP_REG = 5, /* index of Strap register */
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MISC_REG = 6 /* index of Miscellaneous register */
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};
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static int pci_clock; /* 0 = 33 1 = 25 */
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/**
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* optidma_pre_reset - probe begin
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* @link: ATA link
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* @deadline: deadline jiffies for the operation
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*
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* Set up cable type and use generic probe init
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*/
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static int optidma_pre_reset(struct ata_link *link, unsigned long deadline)
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{
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struct ata_port *ap = link->ap;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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static const struct pci_bits optidma_enable_bits = {
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0x40, 1, 0x08, 0x00
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};
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if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits))
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return -ENOENT;
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return ata_sff_prereset(link, deadline);
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}
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/**
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* optidma_unlock - unlock control registers
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* @ap: ATA port
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*
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* Unlock the control register block for this adapter. Registers must not
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* be unlocked in a situation where libata might look at them.
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*/
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static void optidma_unlock(struct ata_port *ap)
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{
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void __iomem *regio = ap->ioaddr.cmd_addr;
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/* These 3 unlock the control register access */
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ioread16(regio + 1);
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ioread16(regio + 1);
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iowrite8(3, regio + 2);
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}
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/**
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* optidma_lock - issue temporary relock
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* @ap: ATA port
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*
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* Re-lock the configuration register settings.
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*/
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static void optidma_lock(struct ata_port *ap)
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{
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void __iomem *regio = ap->ioaddr.cmd_addr;
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/* Relock */
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iowrite8(0x83, regio + 2);
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}
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/**
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* optidma_mode_setup - set mode data
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* @ap: ATA interface
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* @adev: ATA device
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* @mode: Mode to set
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*
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* Called to do the DMA or PIO mode setup. Timing numbers are all
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* pre computed to keep the code clean. There are two tables depending
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* on the hardware clock speed.
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*
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* WARNING: While we do this the IDE registers vanish. If we take an
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* IRQ here we depend on the host set locking to avoid catastrophe.
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*/
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static void optidma_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
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{
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struct ata_device *pair = ata_dev_pair(adev);
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int pio = adev->pio_mode - XFER_PIO_0;
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int dma = adev->dma_mode - XFER_MW_DMA_0;
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void __iomem *regio = ap->ioaddr.cmd_addr;
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u8 addr;
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/* Address table precomputed with a DCLK of 2 */
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static const u8 addr_timing[2][5] = {
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{ 0x30, 0x20, 0x20, 0x10, 0x10 },
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{ 0x20, 0x20, 0x10, 0x10, 0x10 }
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};
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static const u8 data_rec_timing[2][5] = {
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{ 0x59, 0x46, 0x30, 0x20, 0x20 },
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{ 0x46, 0x32, 0x20, 0x20, 0x10 }
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};
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static const u8 dma_data_rec_timing[2][3] = {
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{ 0x76, 0x20, 0x20 },
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{ 0x54, 0x20, 0x10 }
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};
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/* Switch from IDE to control mode */
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optidma_unlock(ap);
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/*
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* As with many controllers the address setup time is shared
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* and must suit both devices if present. FIXME: Check if we
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* need to look at slowest of PIO/DMA mode of either device
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*/
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if (mode >= XFER_MW_DMA_0)
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addr = 0;
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else
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addr = addr_timing[pci_clock][pio];
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if (pair) {
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u8 pair_addr;
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/* Hardware constraint */
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if (pair->dma_mode)
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pair_addr = 0;
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else
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pair_addr = addr_timing[pci_clock][pair->pio_mode - XFER_PIO_0];
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if (pair_addr > addr)
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addr = pair_addr;
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}
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/* Commence primary programming sequence */
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/* First we load the device number into the timing select */
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iowrite8(adev->devno, regio + MISC_REG);
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/* Now we load the data timings into read data/write data */
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if (mode < XFER_MW_DMA_0) {
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iowrite8(data_rec_timing[pci_clock][pio], regio + READ_REG);
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iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG);
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} else if (mode < XFER_UDMA_0) {
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iowrite8(dma_data_rec_timing[pci_clock][dma], regio + READ_REG);
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iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG);
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}
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/* Finally we load the address setup into the misc register */
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iowrite8(addr | adev->devno, regio + MISC_REG);
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/* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */
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iowrite8(0x85, regio + CNTRL_REG);
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/* Switch back to IDE mode */
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optidma_lock(ap);
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/* Note: at this point our programming is incomplete. We are
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not supposed to program PCI 0x43 "things we hacked onto the chip"
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until we've done both sets of PIO/DMA timings */
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}
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/**
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* optiplus_mode_setup - DMA setup for Firestar Plus
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* @ap: ATA port
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* @adev: device
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* @mode: desired mode
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*
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* The Firestar plus has additional UDMA functionality for UDMA0-2 and
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* requires we do some additional work. Because the base work we must do
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* is mostly shared we wrap the Firestar setup functionality in this
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* one
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*/
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static void optiplus_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u8 udcfg;
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u8 udslave;
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int dev2 = 2 * adev->devno;
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int unit = 2 * ap->port_no + adev->devno;
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int udma = mode - XFER_UDMA_0;
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pci_read_config_byte(pdev, 0x44, &udcfg);
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if (mode <= XFER_UDMA_0) {
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udcfg &= ~(1 << unit);
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optidma_mode_setup(ap, adev, adev->dma_mode);
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} else {
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udcfg |= (1 << unit);
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if (ap->port_no) {
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pci_read_config_byte(pdev, 0x45, &udslave);
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udslave &= ~(0x03 << dev2);
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udslave |= (udma << dev2);
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pci_write_config_byte(pdev, 0x45, udslave);
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} else {
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udcfg &= ~(0x30 << dev2);
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udcfg |= (udma << dev2);
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}
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}
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pci_write_config_byte(pdev, 0x44, udcfg);
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}
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/**
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* optidma_set_pio_mode - PIO setup callback
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* @ap: ATA port
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* @adev: Device
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*
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* The libata core provides separate functions for handling PIO and
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* DMA programming. The architecture of the Firestar makes it easier
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* for us to have a common function so we provide wrappers
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*/
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static void optidma_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
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{
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optidma_mode_setup(ap, adev, adev->pio_mode);
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}
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/**
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* optidma_set_dma_mode - DMA setup callback
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* @ap: ATA port
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* @adev: Device
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*
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* The libata core provides separate functions for handling PIO and
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* DMA programming. The architecture of the Firestar makes it easier
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* for us to have a common function so we provide wrappers
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*/
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static void optidma_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
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{
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optidma_mode_setup(ap, adev, adev->dma_mode);
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}
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/**
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* optiplus_set_pio_mode - PIO setup callback
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* @ap: ATA port
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* @adev: Device
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*
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* The libata core provides separate functions for handling PIO and
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* DMA programming. The architecture of the Firestar makes it easier
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* for us to have a common function so we provide wrappers
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*/
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static void optiplus_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
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{
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optiplus_mode_setup(ap, adev, adev->pio_mode);
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}
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/**
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* optiplus_set_dma_mode - DMA setup callback
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* @ap: ATA port
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* @adev: Device
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*
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* The libata core provides separate functions for handling PIO and
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* DMA programming. The architecture of the Firestar makes it easier
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* for us to have a common function so we provide wrappers
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*/
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static void optiplus_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
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{
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optiplus_mode_setup(ap, adev, adev->dma_mode);
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}
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/**
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* optidma_make_bits - PCI setup helper
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* @adev: ATA device
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*
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* Turn the ATA device setup into PCI configuration bits
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* for register 0x43 and return the two bits needed.
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*/
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static u8 optidma_make_bits43(struct ata_device *adev)
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{
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static const u8 bits43[5] = {
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0, 0, 0, 1, 2
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};
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if (!ata_dev_enabled(adev))
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return 0;
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if (adev->dma_mode)
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return adev->dma_mode - XFER_MW_DMA_0;
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return bits43[adev->pio_mode - XFER_PIO_0];
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}
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/**
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* optidma_set_mode - mode setup
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* @link: link to set up
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*
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* Use the standard setup to tune the chipset and then finalise the
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* configuration by writing the nibble of extra bits of data into
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* the chip.
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*/
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static int optidma_set_mode(struct ata_link *link, struct ata_device **r_failed)
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{
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struct ata_port *ap = link->ap;
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u8 r;
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int nybble = 4 * ap->port_no;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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int rc = ata_do_set_mode(link, r_failed);
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if (rc == 0) {
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pci_read_config_byte(pdev, 0x43, &r);
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r &= (0x0F << nybble);
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r |= (optidma_make_bits43(&link->device[0]) +
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(optidma_make_bits43(&link->device[0]) << 2)) << nybble;
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pci_write_config_byte(pdev, 0x43, r);
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}
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return rc;
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}
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static struct scsi_host_template optidma_sht = {
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ATA_BMDMA_SHT(DRV_NAME),
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};
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static struct ata_port_operations optidma_port_ops = {
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.inherits = &ata_bmdma_port_ops,
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.cable_detect = ata_cable_40wire,
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.set_piomode = optidma_set_pio_mode,
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.set_dmamode = optidma_set_dma_mode,
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.set_mode = optidma_set_mode,
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.prereset = optidma_pre_reset,
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};
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static struct ata_port_operations optiplus_port_ops = {
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.inherits = &optidma_port_ops,
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.set_piomode = optiplus_set_pio_mode,
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.set_dmamode = optiplus_set_dma_mode,
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};
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/**
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* optiplus_with_udma - Look for UDMA capable setup
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* @pdev; ATA controller
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*/
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static int optiplus_with_udma(struct pci_dev *pdev)
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{
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u8 r;
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int ret = 0;
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int ioport = 0x22;
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struct pci_dev *dev1;
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/* Find function 1 */
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dev1 = pci_get_device(0x1045, 0xC701, NULL);
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if (dev1 == NULL)
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return 0;
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/* Rev must be >= 0x10 */
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pci_read_config_byte(dev1, 0x08, &r);
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if (r < 0x10)
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goto done_nomsg;
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/* Read the chipset system configuration to check our mode */
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pci_read_config_byte(dev1, 0x5F, &r);
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ioport |= (r << 8);
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outb(0x10, ioport);
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/* Must be 66Mhz sync */
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if ((inb(ioport + 2) & 1) == 0)
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goto done;
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/* Check the ATA arbitration/timing is suitable */
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pci_read_config_byte(pdev, 0x42, &r);
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if ((r & 0x36) != 0x36)
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goto done;
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pci_read_config_byte(dev1, 0x52, &r);
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if (r & 0x80) /* IDEDIR disabled */
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ret = 1;
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done:
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printk(KERN_WARNING "UDMA not supported in this configuration.\n");
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done_nomsg: /* Wrong chip revision */
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pci_dev_put(dev1);
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return ret;
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}
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static int optidma_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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static const struct ata_port_info info_82c700 = {
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.flags = ATA_FLAG_SLAVE_POSS,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.port_ops = &optidma_port_ops
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};
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static const struct ata_port_info info_82c700_udma = {
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.flags = ATA_FLAG_SLAVE_POSS,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA2,
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.port_ops = &optiplus_port_ops
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};
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const struct ata_port_info *ppi[] = { &info_82c700, NULL };
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int rc;
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ata_print_version_once(&dev->dev, DRV_VERSION);
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rc = pcim_enable_device(dev);
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if (rc)
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return rc;
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/* Fixed location chipset magic */
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inw(0x1F1);
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inw(0x1F1);
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pci_clock = inb(0x1F5) & 1; /* 0 = 33Mhz, 1 = 25Mhz */
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if (optiplus_with_udma(dev))
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ppi[0] = &info_82c700_udma;
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return ata_pci_bmdma_init_one(dev, ppi, &optidma_sht, NULL, 0);
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}
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static const struct pci_device_id optidma[] = {
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{ PCI_VDEVICE(OPTI, 0xD568), }, /* Opti 82C700 */
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{ },
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};
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static struct pci_driver optidma_pci_driver = {
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.name = DRV_NAME,
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.id_table = optidma,
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.probe = optidma_init_one,
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.remove = ata_pci_remove_one,
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#ifdef CONFIG_PM_SLEEP
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.suspend = ata_pci_device_suspend,
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.resume = ata_pci_device_resume,
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#endif
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};
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module_pci_driver(optidma_pci_driver);
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MODULE_AUTHOR("Alan Cox");
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MODULE_DESCRIPTION("low-level driver for Opti Firestar/Firestar Plus");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, optidma);
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MODULE_VERSION(DRV_VERSION);
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