174 строки
4.1 KiB
C
174 строки
4.1 KiB
C
/*
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* Actions Semi Owl timer
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*
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* Copyright 2012 Actions Semi Inc.
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* Author: Actions Semi, Inc.
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*
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* Copyright (c) 2017 SUSE Linux GmbH
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* Author: Andreas Färber
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqreturn.h>
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#include <linux/sched_clock.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#define OWL_Tx_CTL 0x0
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#define OWL_Tx_CMP 0x4
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#define OWL_Tx_VAL 0x8
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#define OWL_Tx_CTL_PD BIT(0)
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#define OWL_Tx_CTL_INTEN BIT(1)
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#define OWL_Tx_CTL_EN BIT(2)
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static void __iomem *owl_timer_base;
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static void __iomem *owl_clksrc_base;
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static void __iomem *owl_clkevt_base;
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static inline void owl_timer_reset(void __iomem *base)
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{
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writel(0, base + OWL_Tx_CTL);
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writel(0, base + OWL_Tx_VAL);
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writel(0, base + OWL_Tx_CMP);
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}
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static inline void owl_timer_set_enabled(void __iomem *base, bool enabled)
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{
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u32 ctl = readl(base + OWL_Tx_CTL);
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/* PD bit is cleared when set */
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ctl &= ~OWL_Tx_CTL_PD;
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if (enabled)
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ctl |= OWL_Tx_CTL_EN;
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else
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ctl &= ~OWL_Tx_CTL_EN;
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writel(ctl, base + OWL_Tx_CTL);
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}
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static u64 notrace owl_timer_sched_read(void)
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{
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return (u64)readl(owl_clksrc_base + OWL_Tx_VAL);
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}
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static int owl_timer_set_state_shutdown(struct clock_event_device *evt)
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{
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owl_timer_set_enabled(owl_clkevt_base, false);
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return 0;
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}
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static int owl_timer_set_state_oneshot(struct clock_event_device *evt)
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{
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owl_timer_reset(owl_clkevt_base);
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return 0;
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}
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static int owl_timer_tick_resume(struct clock_event_device *evt)
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{
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return 0;
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}
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static int owl_timer_set_next_event(unsigned long evt,
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struct clock_event_device *ev)
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{
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void __iomem *base = owl_clkevt_base;
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owl_timer_set_enabled(base, false);
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writel(OWL_Tx_CTL_INTEN, base + OWL_Tx_CTL);
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writel(0, base + OWL_Tx_VAL);
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writel(evt, base + OWL_Tx_CMP);
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owl_timer_set_enabled(base, true);
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return 0;
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}
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static struct clock_event_device owl_clockevent = {
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.name = "owl_tick",
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.rating = 200,
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.features = CLOCK_EVT_FEAT_ONESHOT |
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CLOCK_EVT_FEAT_DYNIRQ,
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.set_state_shutdown = owl_timer_set_state_shutdown,
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.set_state_oneshot = owl_timer_set_state_oneshot,
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.tick_resume = owl_timer_tick_resume,
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.set_next_event = owl_timer_set_next_event,
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};
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static irqreturn_t owl_timer1_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = (struct clock_event_device *)dev_id;
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writel(OWL_Tx_CTL_PD, owl_clkevt_base + OWL_Tx_CTL);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static int __init owl_timer_init(struct device_node *node)
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{
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struct clk *clk;
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unsigned long rate;
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int timer1_irq, ret;
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owl_timer_base = of_io_request_and_map(node, 0, "owl-timer");
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if (IS_ERR(owl_timer_base)) {
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pr_err("Can't map timer registers\n");
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return PTR_ERR(owl_timer_base);
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}
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owl_clksrc_base = owl_timer_base + 0x08;
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owl_clkevt_base = owl_timer_base + 0x14;
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timer1_irq = of_irq_get_byname(node, "timer1");
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if (timer1_irq <= 0) {
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pr_err("Can't parse timer1 IRQ\n");
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return -EINVAL;
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}
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clk = of_clk_get(node, 0);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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rate = clk_get_rate(clk);
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owl_timer_reset(owl_clksrc_base);
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owl_timer_set_enabled(owl_clksrc_base, true);
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sched_clock_register(owl_timer_sched_read, 32, rate);
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clocksource_mmio_init(owl_clksrc_base + OWL_Tx_VAL, node->name,
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rate, 200, 32, clocksource_mmio_readl_up);
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owl_timer_reset(owl_clkevt_base);
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ret = request_irq(timer1_irq, owl_timer1_interrupt, IRQF_TIMER,
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"owl-timer", &owl_clockevent);
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if (ret) {
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pr_err("failed to request irq %d\n", timer1_irq);
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return ret;
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}
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owl_clockevent.cpumask = cpumask_of(0);
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owl_clockevent.irq = timer1_irq;
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clockevents_config_and_register(&owl_clockevent, rate,
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0xf, 0xffffffff);
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return 0;
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}
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TIMER_OF_DECLARE(owl_s500, "actions,s500-timer", owl_timer_init);
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TIMER_OF_DECLARE(owl_s700, "actions,s700-timer", owl_timer_init);
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TIMER_OF_DECLARE(owl_s900, "actions,s900-timer", owl_timer_init);
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