686 строки
19 KiB
C
686 строки
19 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Contains CPU specific errata definitions
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*
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* Copyright (C) 2014 ARM Ltd.
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*/
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#include <linux/arm-smccc.h>
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#include <linux/types.h>
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#include <linux/cpu.h>
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#include <asm/cpu.h>
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#include <asm/cputype.h>
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#include <asm/cpufeature.h>
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#include <asm/kvm_asm.h>
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#include <asm/smp_plat.h>
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static bool __maybe_unused
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is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
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{
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const struct arm64_midr_revidr *fix;
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u32 midr = read_cpuid_id(), revidr;
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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if (!is_midr_in_range(midr, &entry->midr_range))
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return false;
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midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
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revidr = read_cpuid(REVIDR_EL1);
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for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
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if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
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return false;
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return true;
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}
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static bool __maybe_unused
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is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
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int scope)
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{
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
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}
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static bool __maybe_unused
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is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
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{
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u32 model;
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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model = read_cpuid_id();
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model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
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MIDR_ARCHITECTURE_MASK;
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return model == entry->midr_range.model;
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}
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static bool
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has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,
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int scope)
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{
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u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
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u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask;
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u64 ctr_raw, ctr_real;
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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/*
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* We want to make sure that all the CPUs in the system expose
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* a consistent CTR_EL0 to make sure that applications behaves
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* correctly with migration.
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*
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* If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 :
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*
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* 1) It is safe if the system doesn't support IDC, as CPU anyway
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* reports IDC = 0, consistent with the rest.
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*
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* 2) If the system has IDC, it is still safe as we trap CTR_EL0
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* access on this CPU via the ARM64_HAS_CACHE_IDC capability.
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*
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* So, we need to make sure either the raw CTR_EL0 or the effective
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* CTR_EL0 matches the system's copy to allow a secondary CPU to boot.
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*/
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ctr_raw = read_cpuid_cachetype() & mask;
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ctr_real = read_cpuid_effective_cachetype() & mask;
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return (ctr_real != sys) && (ctr_raw != sys);
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}
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static void
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cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap)
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{
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u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
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bool enable_uct_trap = false;
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/* Trap CTR_EL0 access on this CPU, only if it has a mismatch */
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if ((read_cpuid_cachetype() & mask) !=
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(arm64_ftr_reg_ctrel0.sys_val & mask))
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enable_uct_trap = true;
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/* ... or if the system is affected by an erratum */
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if (cap->capability == ARM64_WORKAROUND_1542419)
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enable_uct_trap = true;
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if (enable_uct_trap)
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sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
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}
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#ifdef CONFIG_ARM64_ERRATUM_1463225
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static bool
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has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry,
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int scope)
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{
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return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode();
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}
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#endif
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static void __maybe_unused
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cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
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{
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sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);
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}
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#define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
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.matches = is_affected_midr_range, \
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.midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
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#define CAP_MIDR_ALL_VERSIONS(model) \
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.matches = is_affected_midr_range, \
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.midr_range = MIDR_ALL_VERSIONS(model)
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#define MIDR_FIXED(rev, revidr_mask) \
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.fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
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#define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
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.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
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CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
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#define CAP_MIDR_RANGE_LIST(list) \
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.matches = is_affected_midr_range_list, \
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.midr_range_list = list
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/* Errata affecting a range of revisions of given model variant */
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#define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \
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ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
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/* Errata affecting a single variant/revision of a model */
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#define ERRATA_MIDR_REV(model, var, rev) \
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ERRATA_MIDR_RANGE(model, var, rev, var, rev)
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/* Errata affecting all variants/revisions of a given a model */
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#define ERRATA_MIDR_ALL_VERSIONS(model) \
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.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
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CAP_MIDR_ALL_VERSIONS(model)
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/* Errata affecting a list of midr ranges, with same work around */
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#define ERRATA_MIDR_RANGE_LIST(midr_list) \
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.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
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CAP_MIDR_RANGE_LIST(midr_list)
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static const __maybe_unused struct midr_range tx2_family_cpus[] = {
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MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
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MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
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{},
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};
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static bool __maybe_unused
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needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry,
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int scope)
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{
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int i;
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if (!is_affected_midr_range_list(entry, scope) ||
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!is_hyp_mode_available())
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return false;
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for_each_possible_cpu(i) {
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if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0)
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return true;
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}
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return false;
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}
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static bool __maybe_unused
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has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry,
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int scope)
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{
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u32 midr = read_cpuid_id();
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bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT);
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const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1);
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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return is_midr_in_range(midr, &range) && has_dic;
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}
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#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
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static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
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#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
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{
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ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0)
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},
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{
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.midr_range.model = MIDR_QCOM_KRYO,
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.matches = is_kryo_midr,
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_1286807
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{
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ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
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},
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{
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/* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */
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ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe),
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_2441007
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{
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ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_2441009
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{
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/* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */
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ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1),
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},
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#endif
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{},
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};
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#endif
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#ifdef CONFIG_CAVIUM_ERRATUM_27456
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const struct midr_range cavium_erratum_27456_cpus[] = {
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/* Cavium ThunderX, T88 pass 1.x - 2.1 */
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MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1),
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/* Cavium ThunderX, T81 pass 1.0 */
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MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
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{},
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};
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#endif
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#ifdef CONFIG_CAVIUM_ERRATUM_30115
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static const struct midr_range cavium_erratum_30115_cpus[] = {
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/* Cavium ThunderX, T88 pass 1.x - 2.2 */
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MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2),
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/* Cavium ThunderX, T81 pass 1.0 - 1.2 */
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MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
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/* Cavium ThunderX, T83 pass 1.0 */
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MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
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{},
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};
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#endif
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#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
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static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {
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{
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ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
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},
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{
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.midr_range.model = MIDR_QCOM_KRYO,
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.matches = is_kryo_midr,
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},
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{},
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};
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#endif
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#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
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static const struct midr_range workaround_clean_cache[] = {
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#if defined(CONFIG_ARM64_ERRATUM_826319) || \
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defined(CONFIG_ARM64_ERRATUM_827319) || \
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defined(CONFIG_ARM64_ERRATUM_824069)
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/* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */
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MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_819472
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/* Cortex-A53 r0p[01] : ARM errata 819472 */
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MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
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#endif
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{},
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};
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_1418040
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/*
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* - 1188873 affects r0p0 to r2p0
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* - 1418040 affects r0p0 to r3p1
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*/
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static const struct midr_range erratum_1418040_list[] = {
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/* Cortex-A76 r0p0 to r3p1 */
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MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
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/* Neoverse-N1 r0p0 to r3p1 */
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MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1),
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/* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
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MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
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{},
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};
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_845719
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static const struct midr_range erratum_845719_list[] = {
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/* Cortex-A53 r0p[01234] */
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MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
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/* Brahma-B53 r0p[0] */
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MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
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/* Kryo2XX Silver rAp4 */
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MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4),
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{},
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};
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_843419
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static const struct arm64_cpu_capabilities erratum_843419_list[] = {
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{
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/* Cortex-A53 r0p[01234] */
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.matches = is_affected_midr_range,
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ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
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MIDR_FIXED(0x4, BIT(8)),
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},
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{
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/* Brahma-B53 r0p[0] */
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.matches = is_affected_midr_range,
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ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
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},
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{},
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};
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#endif
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#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
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static const struct midr_range erratum_speculative_at_list[] = {
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#ifdef CONFIG_ARM64_ERRATUM_1165522
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/* Cortex A76 r0p0 to r2p0 */
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MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_1319367
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_1530923
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/* Cortex A55 r0p0 to r2p0 */
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MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0),
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/* Kryo4xx Silver (rdpe => r1p0) */
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MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
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#endif
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{},
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};
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_1463225
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static const struct midr_range erratum_1463225[] = {
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/* Cortex-A76 r0p0 - r3p1 */
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MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
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/* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
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MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
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{},
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};
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_1742098
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static struct midr_range broken_aarch32_aes[] = {
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MIDR_RANGE(MIDR_CORTEX_A57, 0, 1, 0xf, 0xf),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
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{},
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};
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#endif
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#ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
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static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
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#ifdef CONFIG_ARM64_ERRATUM_2139208
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
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MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_2119858
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
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#endif
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{},
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};
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#endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */
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#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE
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static const struct midr_range tsb_flush_fail_cpus[] = {
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#ifdef CONFIG_ARM64_ERRATUM_2067961
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
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MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_2054223
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
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#endif
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{},
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};
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#endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */
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#ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
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static struct midr_range trbe_write_out_of_range_cpus[] = {
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#ifdef CONFIG_ARM64_ERRATUM_2253138
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
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MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_2224489
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
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#endif
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{},
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};
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#endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */
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#ifdef CONFIG_ARM64_ERRATUM_3194386
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static const struct midr_range erratum_spec_ssbs_list[] = {
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A76),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A77),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A78),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X925),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),
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{}
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|
};
|
|
#endif
|
|
|
|
const struct arm64_cpu_capabilities arm64_errata[] = {
|
|
#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
|
|
{
|
|
.desc = "ARM errata 826319, 827319, 824069, or 819472",
|
|
.capability = ARM64_WORKAROUND_CLEAN_CACHE,
|
|
ERRATA_MIDR_RANGE_LIST(workaround_clean_cache),
|
|
.cpu_enable = cpu_enable_cache_maint_trap,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_832075
|
|
{
|
|
/* Cortex-A57 r0p0 - r1p2 */
|
|
.desc = "ARM erratum 832075",
|
|
.capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
|
|
ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
|
|
0, 0,
|
|
1, 2),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_834220
|
|
{
|
|
/* Cortex-A57 r0p0 - r1p2 */
|
|
.desc = "ARM erratum 834220",
|
|
.capability = ARM64_WORKAROUND_834220,
|
|
ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
|
|
0, 0,
|
|
1, 2),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_843419
|
|
{
|
|
.desc = "ARM erratum 843419",
|
|
.capability = ARM64_WORKAROUND_843419,
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
|
.matches = cpucap_multi_entry_cap_matches,
|
|
.match_list = erratum_843419_list,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_845719
|
|
{
|
|
.desc = "ARM erratum 845719",
|
|
.capability = ARM64_WORKAROUND_845719,
|
|
ERRATA_MIDR_RANGE_LIST(erratum_845719_list),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CAVIUM_ERRATUM_23154
|
|
{
|
|
/* Cavium ThunderX, pass 1.x */
|
|
.desc = "Cavium erratum 23154",
|
|
.capability = ARM64_WORKAROUND_CAVIUM_23154,
|
|
ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CAVIUM_ERRATUM_27456
|
|
{
|
|
.desc = "Cavium erratum 27456",
|
|
.capability = ARM64_WORKAROUND_CAVIUM_27456,
|
|
ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CAVIUM_ERRATUM_30115
|
|
{
|
|
.desc = "Cavium erratum 30115",
|
|
.capability = ARM64_WORKAROUND_CAVIUM_30115,
|
|
ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus),
|
|
},
|
|
#endif
|
|
{
|
|
.desc = "Mismatched cache type (CTR_EL0)",
|
|
.capability = ARM64_MISMATCHED_CACHE_TYPE,
|
|
.matches = has_mismatched_cache_type,
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
|
.cpu_enable = cpu_enable_trap_ctr_access,
|
|
},
|
|
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
|
|
{
|
|
.desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",
|
|
.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
|
.matches = cpucap_multi_entry_cap_matches,
|
|
.match_list = qcom_erratum_1003_list,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
|
|
{
|
|
.desc = "Qualcomm erratum 1009, or ARM erratum 1286807, 2441009",
|
|
.capability = ARM64_WORKAROUND_REPEAT_TLBI,
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
|
.matches = cpucap_multi_entry_cap_matches,
|
|
.match_list = arm64_repeat_tlbi_list,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_858921
|
|
{
|
|
/* Cortex-A73 all versions */
|
|
.desc = "ARM erratum 858921",
|
|
.capability = ARM64_WORKAROUND_858921,
|
|
ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
|
|
},
|
|
#endif
|
|
{
|
|
.desc = "Spectre-v2",
|
|
.capability = ARM64_SPECTRE_V2,
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
|
.matches = has_spectre_v2,
|
|
.cpu_enable = spectre_v2_enable_mitigation,
|
|
},
|
|
#ifdef CONFIG_RANDOMIZE_BASE
|
|
{
|
|
/* Must come after the Spectre-v2 entry */
|
|
.desc = "Spectre-v3a",
|
|
.capability = ARM64_SPECTRE_V3A,
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
|
.matches = has_spectre_v3a,
|
|
.cpu_enable = spectre_v3a_enable_mitigation,
|
|
},
|
|
#endif
|
|
{
|
|
.desc = "Spectre-v4",
|
|
.capability = ARM64_SPECTRE_V4,
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
|
.matches = has_spectre_v4,
|
|
.cpu_enable = spectre_v4_enable_mitigation,
|
|
},
|
|
{
|
|
.desc = "Spectre-BHB",
|
|
.capability = ARM64_SPECTRE_BHB,
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
|
.matches = is_spectre_bhb_affected,
|
|
.cpu_enable = spectre_bhb_enable_mitigation,
|
|
},
|
|
#ifdef CONFIG_ARM64_ERRATUM_1418040
|
|
{
|
|
.desc = "ARM erratum 1418040",
|
|
.capability = ARM64_WORKAROUND_1418040,
|
|
ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),
|
|
/*
|
|
* We need to allow affected CPUs to come in late, but
|
|
* also need the non-affected CPUs to be able to come
|
|
* in at any point in time. Wonderful.
|
|
*/
|
|
.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
|
|
{
|
|
.desc = "ARM errata 1165522, 1319367, or 1530923",
|
|
.capability = ARM64_WORKAROUND_SPECULATIVE_AT,
|
|
ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_1463225
|
|
{
|
|
.desc = "ARM erratum 1463225",
|
|
.capability = ARM64_WORKAROUND_1463225,
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
|
.matches = has_cortex_a76_erratum_1463225,
|
|
.midr_range_list = erratum_1463225,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CAVIUM_TX2_ERRATUM_219
|
|
{
|
|
.desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)",
|
|
.capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM,
|
|
ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
|
|
.matches = needs_tx2_tvm_workaround,
|
|
},
|
|
{
|
|
.desc = "Cavium ThunderX2 erratum 219 (PRFM removal)",
|
|
.capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM,
|
|
ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_1542419
|
|
{
|
|
/* we depend on the firmware portion for correctness */
|
|
.desc = "ARM erratum 1542419 (kernel portion)",
|
|
.capability = ARM64_WORKAROUND_1542419,
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
|
.matches = has_neoverse_n1_erratum_1542419,
|
|
.cpu_enable = cpu_enable_trap_ctr_access,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_1508412
|
|
{
|
|
/* we depend on the firmware portion for correctness */
|
|
.desc = "ARM erratum 1508412 (kernel portion)",
|
|
.capability = ARM64_WORKAROUND_1508412,
|
|
ERRATA_MIDR_RANGE(MIDR_CORTEX_A77,
|
|
0, 0,
|
|
1, 0),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_NVIDIA_CARMEL_CNP_ERRATUM
|
|
{
|
|
/* NVIDIA Carmel */
|
|
.desc = "NVIDIA Carmel CNP erratum",
|
|
.capability = ARM64_WORKAROUND_NVIDIA_CARMEL_CNP,
|
|
ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
|
|
},
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARM64_ERRATUM_2457168
|
|
{
|
|
.desc = "ARM erratum 2457168",
|
|
.capability = ARM64_WORKAROUND_2457168,
|
|
.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
|
|
/* Cortex-A510 r0p0-r1p1 */
|
|
CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1)
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_1742098
|
|
{
|
|
.desc = "ARM erratum 1742098",
|
|
.capability = ARM64_WORKAROUND_1742098,
|
|
CAP_MIDR_RANGE_LIST(broken_aarch32_aes),
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
|
|
{
|
|
/*
|
|
* The erratum work around is handled within the TRBE
|
|
* driver and can be applied per-cpu. So, we can allow
|
|
* a late CPU to come online with this erratum.
|
|
*/
|
|
.desc = "ARM erratum 2119858 or 2139208",
|
|
.capability = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE,
|
|
.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
|
|
CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE
|
|
{
|
|
.desc = "ARM erratum 2067961 or 2054223",
|
|
.capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE,
|
|
ERRATA_MIDR_RANGE_LIST(tsb_flush_fail_cpus),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
|
|
{
|
|
.desc = "ARM erratum 2253138 or 2224489",
|
|
.capability = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE,
|
|
.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
|
|
CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_3194386
|
|
{
|
|
.desc = "SSBS not fully self-synchronizing",
|
|
.capability = ARM64_WORKAROUND_SPECULATIVE_SSBS,
|
|
ERRATA_MIDR_RANGE_LIST(erratum_spec_ssbs_list),
|
|
},
|
|
#endif
|
|
{
|
|
}
|
|
};
|