266 строки
6.7 KiB
C
266 строки
6.7 KiB
C
/*
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* linux/arch/arm/common/gic.c
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*
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* Copyright (C) 2002 ARM Limited, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Interrupt architecture for the GIC:
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*
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* o There is one Interrupt Distributor, which receives interrupts
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* from system devices and sends them to the Interrupt Controllers.
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*
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* o There is one CPU Interface per CPU, which sends interrupts sent
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* by the Distributor, and interrupts generated locally, to the
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* associated CPU. The base address of the CPU interface is usually
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* aliased so that the same address points to different chips depending
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* on the CPU it is accessed from.
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*
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* Note that IRQs 0-31 are special - they are local to each CPU.
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* As such, the enable set/clear, pending set/clear and active bit
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* registers are banked per-cpu for these sources.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/smp.h>
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#include <linux/cpumask.h>
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#include <linux/io.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <asm/hardware/gic.h>
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static DEFINE_SPINLOCK(irq_controller_lock);
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struct gic_chip_data {
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unsigned int irq_offset;
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void __iomem *dist_base;
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void __iomem *cpu_base;
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};
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#ifndef MAX_GIC_NR
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#define MAX_GIC_NR 1
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#endif
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static struct gic_chip_data gic_data[MAX_GIC_NR];
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static inline void __iomem *gic_dist_base(unsigned int irq)
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{
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struct gic_chip_data *gic_data = get_irq_chip_data(irq);
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return gic_data->dist_base;
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}
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static inline void __iomem *gic_cpu_base(unsigned int irq)
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{
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struct gic_chip_data *gic_data = get_irq_chip_data(irq);
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return gic_data->cpu_base;
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}
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static inline unsigned int gic_irq(unsigned int irq)
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{
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struct gic_chip_data *gic_data = get_irq_chip_data(irq);
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return irq - gic_data->irq_offset;
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}
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/*
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* Routines to acknowledge, disable and enable interrupts
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*
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* Linux assumes that when we're done with an interrupt we need to
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* unmask it, in the same way we need to unmask an interrupt when
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* we first enable it.
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*
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* The GIC has a separate notion of "end of interrupt" to re-enable
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* an interrupt after handling, in order to support hardware
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* prioritisation.
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*
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* We can make the GIC behave in the way that Linux expects by making
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* our "acknowledge" routine disable the interrupt, then mark it as
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* complete.
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*/
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static void gic_ack_irq(unsigned int irq)
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{
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u32 mask = 1 << (irq % 32);
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spin_lock(&irq_controller_lock);
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writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4);
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writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI);
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spin_unlock(&irq_controller_lock);
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}
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static void gic_mask_irq(unsigned int irq)
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{
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u32 mask = 1 << (irq % 32);
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spin_lock(&irq_controller_lock);
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writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4);
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spin_unlock(&irq_controller_lock);
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}
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static void gic_unmask_irq(unsigned int irq)
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{
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u32 mask = 1 << (irq % 32);
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spin_lock(&irq_controller_lock);
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writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_SET + (gic_irq(irq) / 32) * 4);
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spin_unlock(&irq_controller_lock);
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}
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#ifdef CONFIG_SMP
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static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val)
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{
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void __iomem *reg = gic_dist_base(irq) + GIC_DIST_TARGET + (gic_irq(irq) & ~3);
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unsigned int shift = (irq % 4) * 8;
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unsigned int cpu = cpumask_first(mask_val);
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u32 val;
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spin_lock(&irq_controller_lock);
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irq_desc[irq].node = cpu;
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val = readl(reg) & ~(0xff << shift);
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val |= 1 << (cpu + shift);
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writel(val, reg);
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spin_unlock(&irq_controller_lock);
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return 0;
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}
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#endif
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static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
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{
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struct gic_chip_data *chip_data = get_irq_data(irq);
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struct irq_chip *chip = get_irq_chip(irq);
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unsigned int cascade_irq, gic_irq;
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unsigned long status;
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/* primary controller ack'ing */
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chip->ack(irq);
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spin_lock(&irq_controller_lock);
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status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
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spin_unlock(&irq_controller_lock);
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gic_irq = (status & 0x3ff);
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if (gic_irq == 1023)
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goto out;
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cascade_irq = gic_irq + chip_data->irq_offset;
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if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))
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do_bad_IRQ(cascade_irq, desc);
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else
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generic_handle_irq(cascade_irq);
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out:
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/* primary controller unmasking */
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chip->unmask(irq);
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}
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static struct irq_chip gic_chip = {
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.name = "GIC",
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.ack = gic_ack_irq,
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.mask = gic_mask_irq,
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.unmask = gic_unmask_irq,
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#ifdef CONFIG_SMP
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.set_affinity = gic_set_cpu,
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#endif
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};
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void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
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{
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if (gic_nr >= MAX_GIC_NR)
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BUG();
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if (set_irq_data(irq, &gic_data[gic_nr]) != 0)
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BUG();
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set_irq_chained_handler(irq, gic_handle_cascade_irq);
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}
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void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
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unsigned int irq_start)
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{
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unsigned int max_irq, i;
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u32 cpumask = 1 << smp_processor_id();
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if (gic_nr >= MAX_GIC_NR)
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BUG();
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cpumask |= cpumask << 8;
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cpumask |= cpumask << 16;
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gic_data[gic_nr].dist_base = base;
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gic_data[gic_nr].irq_offset = (irq_start - 1) & ~31;
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writel(0, base + GIC_DIST_CTRL);
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/*
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* Find out how many interrupts are supported.
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*/
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max_irq = readl(base + GIC_DIST_CTR) & 0x1f;
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max_irq = (max_irq + 1) * 32;
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/*
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* The GIC only supports up to 1020 interrupt sources.
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* Limit this to either the architected maximum, or the
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* platform maximum.
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*/
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if (max_irq > max(1020, NR_IRQS))
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max_irq = max(1020, NR_IRQS);
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/*
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* Set all global interrupts to be level triggered, active low.
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*/
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for (i = 32; i < max_irq; i += 16)
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writel(0, base + GIC_DIST_CONFIG + i * 4 / 16);
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/*
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* Set all global interrupts to this CPU only.
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*/
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for (i = 32; i < max_irq; i += 4)
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writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
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/*
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* Set priority on all interrupts.
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*/
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for (i = 0; i < max_irq; i += 4)
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writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
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/*
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* Disable all interrupts.
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*/
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for (i = 0; i < max_irq; i += 32)
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writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
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/*
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* Setup the Linux IRQ subsystem.
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*/
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for (i = irq_start; i < gic_data[gic_nr].irq_offset + max_irq; i++) {
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set_irq_chip(i, &gic_chip);
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set_irq_chip_data(i, &gic_data[gic_nr]);
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set_irq_handler(i, handle_level_irq);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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}
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writel(1, base + GIC_DIST_CTRL);
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}
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void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)
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{
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if (gic_nr >= MAX_GIC_NR)
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BUG();
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gic_data[gic_nr].cpu_base = base;
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writel(0xf0, base + GIC_CPU_PRIMASK);
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writel(1, base + GIC_CPU_CTRL);
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}
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#ifdef CONFIG_SMP
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void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
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{
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unsigned long map = *cpus_addr(*mask);
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/* this always happens on GIC0 */
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writel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
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}
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#endif
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