453 строки
21 KiB
ReStructuredText
453 строки
21 KiB
ReStructuredText
.. _hmm:
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=====================================
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Heterogeneous Memory Management (HMM)
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=====================================
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Provide infrastructure and helpers to integrate non-conventional memory (device
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memory like GPU on board memory) into regular kernel path, with the cornerstone
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of this being specialized struct page for such memory (see sections 5 to 7 of
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this document).
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HMM also provides optional helpers for SVM (Share Virtual Memory), i.e.,
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allowing a device to transparently access program addresses coherently with
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the CPU meaning that any valid pointer on the CPU is also a valid pointer
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for the device. This is becoming mandatory to simplify the use of advanced
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heterogeneous computing where GPU, DSP, or FPGA are used to perform various
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computations on behalf of a process.
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This document is divided as follows: in the first section I expose the problems
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related to using device specific memory allocators. In the second section, I
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expose the hardware limitations that are inherent to many platforms. The third
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section gives an overview of the HMM design. The fourth section explains how
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CPU page-table mirroring works and the purpose of HMM in this context. The
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fifth section deals with how device memory is represented inside the kernel.
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Finally, the last section presents a new migration helper that allows
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leveraging the device DMA engine.
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.. contents:: :local:
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Problems of using a device specific memory allocator
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====================================================
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Devices with a large amount of on board memory (several gigabytes) like GPUs
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have historically managed their memory through dedicated driver specific APIs.
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This creates a disconnect between memory allocated and managed by a device
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driver and regular application memory (private anonymous, shared memory, or
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regular file backed memory). From here on I will refer to this aspect as split
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address space. I use shared address space to refer to the opposite situation:
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i.e., one in which any application memory region can be used by a device
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transparently.
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Split address space happens because devices can only access memory allocated
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through a device specific API. This implies that all memory objects in a program
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are not equal from the device point of view which complicates large programs
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that rely on a wide set of libraries.
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Concretely, this means that code that wants to leverage devices like GPUs needs
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to copy objects between generically allocated memory (malloc, mmap private, mmap
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share) and memory allocated through the device driver API (this still ends up
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with an mmap but of the device file).
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For flat data sets (array, grid, image, ...) this isn't too hard to achieve but
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for complex data sets (list, tree, ...) it's hard to get right. Duplicating a
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complex data set needs to re-map all the pointer relations between each of its
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elements. This is error prone and programs get harder to debug because of the
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duplicate data set and addresses.
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Split address space also means that libraries cannot transparently use data
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they are getting from the core program or another library and thus each library
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might have to duplicate its input data set using the device specific memory
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allocator. Large projects suffer from this and waste resources because of the
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various memory copies.
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Duplicating each library API to accept as input or output memory allocated by
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each device specific allocator is not a viable option. It would lead to a
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combinatorial explosion in the library entry points.
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Finally, with the advance of high level language constructs (in C++ but in
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other languages too) it is now possible for the compiler to leverage GPUs and
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other devices without programmer knowledge. Some compiler identified patterns
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are only do-able with a shared address space. It is also more reasonable to use
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a shared address space for all other patterns.
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I/O bus, device memory characteristics
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======================================
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I/O buses cripple shared address spaces due to a few limitations. Most I/O
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buses only allow basic memory access from device to main memory; even cache
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coherency is often optional. Access to device memory from a CPU is even more
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limited. More often than not, it is not cache coherent.
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If we only consider the PCIE bus, then a device can access main memory (often
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through an IOMMU) and be cache coherent with the CPUs. However, it only allows
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a limited set of atomic operations from the device on main memory. This is worse
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in the other direction: the CPU can only access a limited range of the device
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memory and cannot perform atomic operations on it. Thus device memory cannot
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be considered the same as regular memory from the kernel point of view.
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Another crippling factor is the limited bandwidth (~32GBytes/s with PCIE 4.0
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and 16 lanes). This is 33 times less than the fastest GPU memory (1 TBytes/s).
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The final limitation is latency. Access to main memory from the device has an
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order of magnitude higher latency than when the device accesses its own memory.
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Some platforms are developing new I/O buses or additions/modifications to PCIE
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to address some of these limitations (OpenCAPI, CCIX). They mainly allow
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two-way cache coherency between CPU and device and allow all atomic operations the
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architecture supports. Sadly, not all platforms are following this trend and
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some major architectures are left without hardware solutions to these problems.
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So for shared address space to make sense, not only must we allow devices to
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access any memory but we must also permit any memory to be migrated to device
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memory while the device is using it (blocking CPU access while it happens).
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Shared address space and migration
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==================================
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HMM intends to provide two main features. The first one is to share the address
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space by duplicating the CPU page table in the device page table so the same
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address points to the same physical memory for any valid main memory address in
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the process address space.
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To achieve this, HMM offers a set of helpers to populate the device page table
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while keeping track of CPU page table updates. Device page table updates are
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not as easy as CPU page table updates. To update the device page table, you must
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allocate a buffer (or use a pool of pre-allocated buffers) and write GPU
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specific commands in it to perform the update (unmap, cache invalidations, and
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flush, ...). This cannot be done through common code for all devices. Hence
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why HMM provides helpers to factor out everything that can be while leaving the
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hardware specific details to the device driver.
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The second mechanism HMM provides is a new kind of ZONE_DEVICE memory that
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allows allocating a struct page for each page of device memory. Those pages
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are special because the CPU cannot map them. However, they allow migrating
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main memory to device memory using existing migration mechanisms and everything
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looks like a page that is swapped out to disk from the CPU point of view. Using a
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struct page gives the easiest and cleanest integration with existing mm
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mechanisms. Here again, HMM only provides helpers, first to hotplug new ZONE_DEVICE
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memory for the device memory and second to perform migration. Policy decisions
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of what and when to migrate is left to the device driver.
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Note that any CPU access to a device page triggers a page fault and a migration
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back to main memory. For example, when a page backing a given CPU address A is
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migrated from a main memory page to a device page, then any CPU access to
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address A triggers a page fault and initiates a migration back to main memory.
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With these two features, HMM not only allows a device to mirror process address
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space and keeps both CPU and device page tables synchronized, but also
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leverages device memory by migrating the part of the data set that is actively being
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used by the device.
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Address space mirroring implementation and API
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==============================================
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Address space mirroring's main objective is to allow duplication of a range of
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CPU page table into a device page table; HMM helps keep both synchronized. A
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device driver that wants to mirror a process address space must start with the
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registration of a mmu_interval_notifier::
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int mmu_interval_notifier_insert(struct mmu_interval_notifier *interval_sub,
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struct mm_struct *mm, unsigned long start,
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unsigned long length,
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const struct mmu_interval_notifier_ops *ops);
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During the ops->invalidate() callback the device driver must perform the
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update action to the range (mark range read only, or fully unmap, etc.). The
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device must complete the update before the driver callback returns.
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When the device driver wants to populate a range of virtual addresses, it can
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use::
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int hmm_range_fault(struct hmm_range *range);
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It will trigger a page fault on missing or read-only entries if write access is
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requested (see below). Page faults use the generic mm page fault code path just
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like a CPU page fault.
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Both functions copy CPU page table entries into their pfns array argument. Each
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entry in that array corresponds to an address in the virtual range. HMM
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provides a set of flags to help the driver identify special CPU page table
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entries.
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Locking within the sync_cpu_device_pagetables() callback is the most important
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aspect the driver must respect in order to keep things properly synchronized.
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The usage pattern is::
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int driver_populate_range(...)
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{
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struct hmm_range range;
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...
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range.notifier = &interval_sub;
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range.start = ...;
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range.end = ...;
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range.hmm_pfns = ...;
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if (!mmget_not_zero(interval_sub->notifier.mm))
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return -EFAULT;
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again:
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range.notifier_seq = mmu_interval_read_begin(&interval_sub);
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mmap_read_lock(mm);
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ret = hmm_range_fault(&range);
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if (ret) {
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mmap_read_unlock(mm);
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if (ret == -EBUSY)
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goto again;
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return ret;
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}
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mmap_read_unlock(mm);
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take_lock(driver->update);
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if (mmu_interval_read_retry(&ni, range.notifier_seq) {
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release_lock(driver->update);
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goto again;
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}
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/* Use pfns array content to update device page table,
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* under the update lock */
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release_lock(driver->update);
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return 0;
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}
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The driver->update lock is the same lock that the driver takes inside its
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invalidate() callback. That lock must be held before calling
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mmu_interval_read_retry() to avoid any race with a concurrent CPU page table
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update.
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Leverage default_flags and pfn_flags_mask
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=========================================
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The hmm_range struct has 2 fields, default_flags and pfn_flags_mask, that specify
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fault or snapshot policy for the whole range instead of having to set them
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for each entry in the pfns array.
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For instance if the device driver wants pages for a range with at least read
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permission, it sets::
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range->default_flags = HMM_PFN_REQ_FAULT;
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range->pfn_flags_mask = 0;
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and calls hmm_range_fault() as described above. This will fill fault all pages
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in the range with at least read permission.
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Now let's say the driver wants to do the same except for one page in the range for
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which it wants to have write permission. Now driver set::
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range->default_flags = HMM_PFN_REQ_FAULT;
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range->pfn_flags_mask = HMM_PFN_REQ_WRITE;
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range->pfns[index_of_write] = HMM_PFN_REQ_WRITE;
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With this, HMM will fault in all pages with at least read (i.e., valid) and for the
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address == range->start + (index_of_write << PAGE_SHIFT) it will fault with
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write permission i.e., if the CPU pte does not have write permission set then HMM
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will call handle_mm_fault().
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After hmm_range_fault completes the flag bits are set to the current state of
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the page tables, ie HMM_PFN_VALID | HMM_PFN_WRITE will be set if the page is
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writable.
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Represent and manage device memory from core kernel point of view
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=================================================================
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Several different designs were tried to support device memory. The first one
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used a device specific data structure to keep information about migrated memory
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and HMM hooked itself in various places of mm code to handle any access to
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addresses that were backed by device memory. It turns out that this ended up
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replicating most of the fields of struct page and also needed many kernel code
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paths to be updated to understand this new kind of memory.
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Most kernel code paths never try to access the memory behind a page
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but only care about struct page contents. Because of this, HMM switched to
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directly using struct page for device memory which left most kernel code paths
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unaware of the difference. We only need to make sure that no one ever tries to
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map those pages from the CPU side.
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Migration to and from device memory
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===================================
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Because the CPU cannot access device memory directly, the device driver must
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use hardware DMA or device specific load/store instructions to migrate data.
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The migrate_vma_setup(), migrate_vma_pages(), and migrate_vma_finalize()
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functions are designed to make drivers easier to write and to centralize common
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code across drivers.
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Before migrating pages to device private memory, special device private
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``struct page`` need to be created. These will be used as special "swap"
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page table entries so that a CPU process will fault if it tries to access
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a page that has been migrated to device private memory.
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These can be allocated and freed with::
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struct resource *res;
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struct dev_pagemap pagemap;
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res = request_free_mem_region(&iomem_resource, /* number of bytes */,
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"name of driver resource");
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pagemap.type = MEMORY_DEVICE_PRIVATE;
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pagemap.range.start = res->start;
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pagemap.range.end = res->end;
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pagemap.nr_range = 1;
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pagemap.ops = &device_devmem_ops;
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memremap_pages(&pagemap, numa_node_id());
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memunmap_pages(&pagemap);
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release_mem_region(pagemap.range.start, range_len(&pagemap.range));
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There are also devm_request_free_mem_region(), devm_memremap_pages(),
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devm_memunmap_pages(), and devm_release_mem_region() when the resources can
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be tied to a ``struct device``.
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The overall migration steps are similar to migrating NUMA pages within system
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memory (see :ref:`Page migration <page_migration>`) but the steps are split
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between device driver specific code and shared common code:
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1. ``mmap_read_lock()``
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The device driver has to pass a ``struct vm_area_struct`` to
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migrate_vma_setup() so the mmap_read_lock() or mmap_write_lock() needs to
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be held for the duration of the migration.
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2. ``migrate_vma_setup(struct migrate_vma *args)``
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The device driver initializes the ``struct migrate_vma`` fields and passes
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the pointer to migrate_vma_setup(). The ``args->flags`` field is used to
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filter which source pages should be migrated. For example, setting
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``MIGRATE_VMA_SELECT_SYSTEM`` will only migrate system memory and
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``MIGRATE_VMA_SELECT_DEVICE_PRIVATE`` will only migrate pages residing in
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device private memory. If the latter flag is set, the ``args->pgmap_owner``
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field is used to identify device private pages owned by the driver. This
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avoids trying to migrate device private pages residing in other devices.
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Currently only anonymous private VMA ranges can be migrated to or from
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system memory and device private memory.
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One of the first steps migrate_vma_setup() does is to invalidate other
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device's MMUs with the ``mmu_notifier_invalidate_range_start(()`` and
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``mmu_notifier_invalidate_range_end()`` calls around the page table
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walks to fill in the ``args->src`` array with PFNs to be migrated.
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The ``invalidate_range_start()`` callback is passed a
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``struct mmu_notifier_range`` with the ``event`` field set to
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``MMU_NOTIFY_MIGRATE`` and the ``owner`` field set to
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the ``args->pgmap_owner`` field passed to migrate_vma_setup(). This is
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allows the device driver to skip the invalidation callback and only
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invalidate device private MMU mappings that are actually migrating.
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This is explained more in the next section.
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While walking the page tables, a ``pte_none()`` or ``is_zero_pfn()``
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entry results in a valid "zero" PFN stored in the ``args->src`` array.
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This lets the driver allocate device private memory and clear it instead
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of copying a page of zeros. Valid PTE entries to system memory or
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device private struct pages will be locked with ``lock_page()``, isolated
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from the LRU (if system memory since device private pages are not on
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the LRU), unmapped from the process, and a special migration PTE is
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inserted in place of the original PTE.
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migrate_vma_setup() also clears the ``args->dst`` array.
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3. The device driver allocates destination pages and copies source pages to
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destination pages.
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The driver checks each ``src`` entry to see if the ``MIGRATE_PFN_MIGRATE``
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bit is set and skips entries that are not migrating. The device driver
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can also choose to skip migrating a page by not filling in the ``dst``
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array for that page.
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The driver then allocates either a device private struct page or a
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system memory page, locks the page with ``lock_page()``, and fills in the
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``dst`` array entry with::
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dst[i] = migrate_pfn(page_to_pfn(dpage));
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Now that the driver knows that this page is being migrated, it can
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invalidate device private MMU mappings and copy device private memory
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to system memory or another device private page. The core Linux kernel
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handles CPU page table invalidations so the device driver only has to
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invalidate its own MMU mappings.
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The driver can use ``migrate_pfn_to_page(src[i])`` to get the
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``struct page`` of the source and either copy the source page to the
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destination or clear the destination device private memory if the pointer
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is ``NULL`` meaning the source page was not populated in system memory.
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4. ``migrate_vma_pages()``
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This step is where the migration is actually "committed".
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If the source page was a ``pte_none()`` or ``is_zero_pfn()`` page, this
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is where the newly allocated page is inserted into the CPU's page table.
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This can fail if a CPU thread faults on the same page. However, the page
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table is locked and only one of the new pages will be inserted.
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The device driver will see that the ``MIGRATE_PFN_MIGRATE`` bit is cleared
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if it loses the race.
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If the source page was locked, isolated, etc. the source ``struct page``
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information is now copied to destination ``struct page`` finalizing the
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migration on the CPU side.
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5. Device driver updates device MMU page tables for pages still migrating,
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rolling back pages not migrating.
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If the ``src`` entry still has ``MIGRATE_PFN_MIGRATE`` bit set, the device
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driver can update the device MMU and set the write enable bit if the
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``MIGRATE_PFN_WRITE`` bit is set.
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6. ``migrate_vma_finalize()``
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This step replaces the special migration page table entry with the new
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page's page table entry and releases the reference to the source and
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destination ``struct page``.
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7. ``mmap_read_unlock()``
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The lock can now be released.
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Exclusive access memory
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=======================
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Some devices have features such as atomic PTE bits that can be used to implement
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atomic access to system memory. To support atomic operations to a shared virtual
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memory page such a device needs access to that page which is exclusive of any
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userspace access from the CPU. The ``make_device_exclusive_range()`` function
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can be used to make a memory range inaccessible from userspace.
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This replaces all mappings for pages in the given range with special swap
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entries. Any attempt to access the swap entry results in a fault which is
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resovled by replacing the entry with the original mapping. A driver gets
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notified that the mapping has been changed by MMU notifiers, after which point
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it will no longer have exclusive access to the page. Exclusive access is
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guranteed to last until the driver drops the page lock and page reference, at
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which point any CPU faults on the page may proceed as described.
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Memory cgroup (memcg) and rss accounting
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========================================
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For now, device memory is accounted as any regular page in rss counters (either
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anonymous if device page is used for anonymous, file if device page is used for
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file backed page, or shmem if device page is used for shared memory). This is a
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deliberate choice to keep existing applications, that might start using device
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memory without knowing about it, running unimpacted.
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A drawback is that the OOM killer might kill an application using a lot of
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device memory and not a lot of regular system memory and thus not freeing much
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system memory. We want to gather more real world experience on how applications
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and system react under memory pressure in the presence of device memory before
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deciding to account device memory differently.
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Same decision was made for memory cgroup. Device memory pages are accounted
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against same memory cgroup a regular page would be accounted to. This does
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simplify migration to and from device memory. This also means that migration
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back from device memory to regular memory cannot fail because it would
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go above memory cgroup limit. We might revisit this choice latter on once we
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get more experience in how device memory is used and its impact on memory
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resource control.
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Note that device memory can never be pinned by a device driver nor through GUP
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and thus such memory is always free upon process exit. Or when last reference
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is dropped in case of shared memory or file backed memory.
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