135 строки
3.1 KiB
C
135 строки
3.1 KiB
C
/*
|
|
* Copyright (C) 2011 Google, Inc.
|
|
*
|
|
* Author:
|
|
* Colin Cross <ccross@android.com>
|
|
*
|
|
* Copyright (C) 2010, NVIDIA Corporation
|
|
*
|
|
* This software is licensed under the terms of the GNU General Public
|
|
* License version 2, as published by the Free Software Foundation, and
|
|
* may be copied, distributed, and modified under those terms.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
*/
|
|
|
|
#include <linux/kernel.h>
|
|
#include <linux/interrupt.h>
|
|
#include <linux/irq.h>
|
|
#include <linux/io.h>
|
|
|
|
#include <asm/hardware/gic.h>
|
|
|
|
#include <mach/iomap.h>
|
|
|
|
#include "board.h"
|
|
|
|
#define INT_SYS_NR (INT_GPIO_BASE - INT_PRI_BASE)
|
|
#define INT_SYS_SZ (INT_SEC_BASE - INT_PRI_BASE)
|
|
#define PPI_NR ((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ)
|
|
|
|
#define ICTLR_CPU_IEP_VFIQ 0x08
|
|
#define ICTLR_CPU_IEP_FIR 0x14
|
|
#define ICTLR_CPU_IEP_FIR_SET 0x18
|
|
#define ICTLR_CPU_IEP_FIR_CLR 0x1c
|
|
|
|
#define ICTLR_CPU_IER 0x20
|
|
#define ICTLR_CPU_IER_SET 0x24
|
|
#define ICTLR_CPU_IER_CLR 0x28
|
|
#define ICTLR_CPU_IEP_CLASS 0x2C
|
|
|
|
#define ICTLR_COP_IER 0x30
|
|
#define ICTLR_COP_IER_SET 0x34
|
|
#define ICTLR_COP_IER_CLR 0x38
|
|
#define ICTLR_COP_IEP_CLASS 0x3c
|
|
|
|
#define NUM_ICTLRS 4
|
|
#define FIRST_LEGACY_IRQ 32
|
|
|
|
static void __iomem *ictlr_reg_base[] = {
|
|
IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
|
|
IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
|
|
IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
|
|
IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
|
|
};
|
|
|
|
static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
|
|
{
|
|
void __iomem *base;
|
|
u32 mask;
|
|
|
|
BUG_ON(irq < FIRST_LEGACY_IRQ ||
|
|
irq >= FIRST_LEGACY_IRQ + NUM_ICTLRS * 32);
|
|
|
|
base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32];
|
|
mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
|
|
|
|
__raw_writel(mask, base + reg);
|
|
}
|
|
|
|
static void tegra_mask(struct irq_data *d)
|
|
{
|
|
if (d->irq < FIRST_LEGACY_IRQ)
|
|
return;
|
|
|
|
tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_CLR);
|
|
}
|
|
|
|
static void tegra_unmask(struct irq_data *d)
|
|
{
|
|
if (d->irq < FIRST_LEGACY_IRQ)
|
|
return;
|
|
|
|
tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_SET);
|
|
}
|
|
|
|
static void tegra_ack(struct irq_data *d)
|
|
{
|
|
if (d->irq < FIRST_LEGACY_IRQ)
|
|
return;
|
|
|
|
tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
|
|
}
|
|
|
|
static void tegra_eoi(struct irq_data *d)
|
|
{
|
|
if (d->irq < FIRST_LEGACY_IRQ)
|
|
return;
|
|
|
|
tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
|
|
}
|
|
|
|
static int tegra_retrigger(struct irq_data *d)
|
|
{
|
|
if (d->irq < FIRST_LEGACY_IRQ)
|
|
return 0;
|
|
|
|
tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_SET);
|
|
|
|
return 1;
|
|
}
|
|
|
|
void __init tegra_init_irq(void)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < NUM_ICTLRS; i++) {
|
|
void __iomem *ictlr = ictlr_reg_base[i];
|
|
writel(~0, ictlr + ICTLR_CPU_IER_CLR);
|
|
writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
|
|
}
|
|
|
|
gic_arch_extn.irq_ack = tegra_ack;
|
|
gic_arch_extn.irq_eoi = tegra_eoi;
|
|
gic_arch_extn.irq_mask = tegra_mask;
|
|
gic_arch_extn.irq_unmask = tegra_unmask;
|
|
gic_arch_extn.irq_retrigger = tegra_retrigger;
|
|
|
|
gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
|
|
IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
|
|
}
|