WSL2-Linux-Kernel/arch/x86/kernel/cpu/mtrr
Ajaykumar Hotchandani 8dbf4a3003 x86/mtrr: Resolve inconsistency with Intel processor manual
Following is from Notes of section 11.5.3 of Intel processor
manual available at:

  http://www.intel.com/Assets/PDF/manual/325384.pdf

For the Pentium 4 and Intel Xeon processors, after the sequence of
steps given above has been executed, the cache lines containing the
code between the end of the WBINVD instruction and before the
MTRRS have actually been disabled may be retained in the cache
hierarchy. Here, to remove code from the cache completely, a
second WBINVD instruction must be executed after the MTRRs have
been disabled.

This patch provides resolution for that.

Ideally, I will like to make changes only for Pentium 4 and Xeon
processors. But, I am not finding easier way to do it.
And, extra wbinvd() instruction does not hurt much for other
processors.

Signed-off-by: Ajaykumar Hotchandani <ajaykumar.hotchandani@oracle.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Arjan van de Ven <arjan@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@profusion.mobi>
Link: http://lkml.kernel.org/r/4EBD1CC5.3030008@oracle.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-12-05 15:06:15 +01:00
..
Makefile x86, mtrr: Remove unused mtrr/state.c 2010-02-04 10:01:38 +01:00
amd.c x86, mtrr: Constify struct mtrr_ops 2010-02-01 11:20:43 -08:00
centaur.c x86, mtrr: Constify struct mtrr_ops 2010-02-01 11:20:43 -08:00
cleanup.c x86, mtrr: Assume SYS_CFG[Tom2ForceMemTypeWB] exists on all future AMD CPUs 2010-10-01 16:18:31 -07:00
cyrix.c x86, mtrr: Constify struct mtrr_ops 2010-02-01 11:20:43 -08:00
generic.c x86/mtrr: Resolve inconsistency with Intel processor manual 2011-12-05 15:06:15 +01:00
if.c include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h 2010-03-30 22:02:32 +09:00
main.c mtrr: fix UP breakage caused during switch to stop_machine 2011-08-25 11:02:29 -07:00
mtrr.h x86, mtrr: Constify struct mtrr_ops 2010-02-01 11:20:43 -08:00