547 строки
14 KiB
C
547 строки
14 KiB
C
/*
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* linux/arch/arm/common/vic.c
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*
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* Copyright (C) 1999 - 2003 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/syscore_ops.h>
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#include <linux/device.h>
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#include <linux/amba/bus.h>
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#include <linux/irqchip/arm-vic.h>
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#include <asm/exception.h>
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#include <asm/irq.h>
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#define VIC_IRQ_STATUS 0x00
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#define VIC_FIQ_STATUS 0x04
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#define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */
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#define VIC_INT_SOFT 0x18
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#define VIC_INT_SOFT_CLEAR 0x1c
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#define VIC_PROTECT 0x20
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#define VIC_PL190_VECT_ADDR 0x30 /* PL190 only */
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#define VIC_PL190_DEF_VECT_ADDR 0x34 /* PL190 only */
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#define VIC_VECT_ADDR0 0x100 /* 0 to 15 (0..31 PL192) */
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#define VIC_VECT_CNTL0 0x200 /* 0 to 15 (0..31 PL192) */
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#define VIC_ITCR 0x300 /* VIC test control register */
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#define VIC_VECT_CNTL_ENABLE (1 << 5)
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#define VIC_PL192_VECT_ADDR 0xF00
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/**
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* struct vic_device - VIC PM device
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* @parent_irq: The parent IRQ number of the VIC if cascaded, or 0.
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* @irq: The IRQ number for the base of the VIC.
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* @base: The register base for the VIC.
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* @valid_sources: A bitmask of valid interrupts
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* @resume_sources: A bitmask of interrupts for resume.
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* @resume_irqs: The IRQs enabled for resume.
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* @int_select: Save for VIC_INT_SELECT.
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* @int_enable: Save for VIC_INT_ENABLE.
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* @soft_int: Save for VIC_INT_SOFT.
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* @protect: Save for VIC_PROTECT.
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* @domain: The IRQ domain for the VIC.
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*/
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struct vic_device {
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void __iomem *base;
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int irq;
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u32 valid_sources;
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u32 resume_sources;
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u32 resume_irqs;
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u32 int_select;
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u32 int_enable;
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u32 soft_int;
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u32 protect;
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struct irq_domain *domain;
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};
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/* we cannot allocate memory when VICs are initially registered */
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static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
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static int vic_id;
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static void vic_handle_irq(struct pt_regs *regs);
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/**
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* vic_init2 - common initialisation code
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* @base: Base of the VIC.
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*
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* Common initialisation code for registration
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* and resume.
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*/
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static void vic_init2(void __iomem *base)
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{
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int i;
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for (i = 0; i < 16; i++) {
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void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
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writel(VIC_VECT_CNTL_ENABLE | i, reg);
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}
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writel(32, base + VIC_PL190_DEF_VECT_ADDR);
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}
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#ifdef CONFIG_PM
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static void resume_one_vic(struct vic_device *vic)
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{
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void __iomem *base = vic->base;
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printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
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/* re-initialise static settings */
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vic_init2(base);
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writel(vic->int_select, base + VIC_INT_SELECT);
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writel(vic->protect, base + VIC_PROTECT);
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/* set the enabled ints and then clear the non-enabled */
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writel(vic->int_enable, base + VIC_INT_ENABLE);
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writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
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/* and the same for the soft-int register */
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writel(vic->soft_int, base + VIC_INT_SOFT);
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writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
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}
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static void vic_resume(void)
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{
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int id;
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for (id = vic_id - 1; id >= 0; id--)
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resume_one_vic(vic_devices + id);
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}
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static void suspend_one_vic(struct vic_device *vic)
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{
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void __iomem *base = vic->base;
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printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
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vic->int_select = readl(base + VIC_INT_SELECT);
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vic->int_enable = readl(base + VIC_INT_ENABLE);
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vic->soft_int = readl(base + VIC_INT_SOFT);
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vic->protect = readl(base + VIC_PROTECT);
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/* set the interrupts (if any) that are used for
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* resuming the system */
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writel(vic->resume_irqs, base + VIC_INT_ENABLE);
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writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
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}
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static int vic_suspend(void)
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{
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int id;
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for (id = 0; id < vic_id; id++)
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suspend_one_vic(vic_devices + id);
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return 0;
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}
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static struct syscore_ops vic_syscore_ops = {
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.suspend = vic_suspend,
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.resume = vic_resume,
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};
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/**
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* vic_pm_init - initicall to register VIC pm
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*
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* This is called via late_initcall() to register
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* the resources for the VICs due to the early
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* nature of the VIC's registration.
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*/
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static int __init vic_pm_init(void)
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{
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if (vic_id > 0)
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register_syscore_ops(&vic_syscore_ops);
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return 0;
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}
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late_initcall(vic_pm_init);
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#endif /* CONFIG_PM */
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static struct irq_chip vic_chip;
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static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct vic_device *v = d->host_data;
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/* Skip invalid IRQs, only register handlers for the real ones */
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if (!(v->valid_sources & (1 << hwirq)))
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return -EPERM;
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irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq);
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irq_set_chip_data(irq, v->base);
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irq_set_probe(irq);
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return 0;
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}
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/*
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* Handle each interrupt in a single VIC. Returns non-zero if we've
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* handled at least one interrupt. This reads the status register
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* before handling each interrupt, which is necessary given that
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* handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
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*/
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static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
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{
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u32 stat, irq;
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int handled = 0;
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while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
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irq = ffs(stat) - 1;
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handle_domain_irq(vic->domain, irq, regs);
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handled = 1;
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}
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return handled;
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}
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static void vic_handle_irq_cascaded(struct irq_desc *desc)
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{
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u32 stat, hwirq;
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struct irq_chip *host_chip = irq_desc_get_chip(desc);
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struct vic_device *vic = irq_desc_get_handler_data(desc);
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chained_irq_enter(host_chip, desc);
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while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
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hwirq = ffs(stat) - 1;
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generic_handle_irq(irq_find_mapping(vic->domain, hwirq));
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}
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chained_irq_exit(host_chip, desc);
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}
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/*
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* Keep iterating over all registered VIC's until there are no pending
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* interrupts.
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*/
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static void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
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{
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int i, handled;
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do {
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for (i = 0, handled = 0; i < vic_id; ++i)
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handled |= handle_one_vic(&vic_devices[i], regs);
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} while (handled);
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}
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static const struct irq_domain_ops vic_irqdomain_ops = {
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.map = vic_irqdomain_map,
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.xlate = irq_domain_xlate_onetwocell,
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};
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/**
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* vic_register() - Register a VIC.
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* @base: The base address of the VIC.
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* @parent_irq: The parent IRQ if cascaded, else 0.
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* @irq: The base IRQ for the VIC.
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* @valid_sources: bitmask of valid interrupts
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* @resume_sources: bitmask of interrupts allowed for resume sources.
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* @node: The device tree node associated with the VIC.
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*
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* Register the VIC with the system device tree so that it can be notified
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* of suspend and resume requests and ensure that the correct actions are
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* taken to re-instate the settings on resume.
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*
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* This also configures the IRQ domain for the VIC.
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*/
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static void __init vic_register(void __iomem *base, unsigned int parent_irq,
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unsigned int irq,
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u32 valid_sources, u32 resume_sources,
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struct device_node *node)
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{
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struct vic_device *v;
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int i;
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if (vic_id >= ARRAY_SIZE(vic_devices)) {
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printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
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return;
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}
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v = &vic_devices[vic_id];
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v->base = base;
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v->valid_sources = valid_sources;
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v->resume_sources = resume_sources;
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set_handle_irq(vic_handle_irq);
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vic_id++;
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if (parent_irq) {
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irq_set_chained_handler_and_data(parent_irq,
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vic_handle_irq_cascaded, v);
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}
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v->domain = irq_domain_add_simple(node, fls(valid_sources), irq,
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&vic_irqdomain_ops, v);
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/* create an IRQ mapping for each valid IRQ */
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for (i = 0; i < fls(valid_sources); i++)
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if (valid_sources & (1 << i))
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irq_create_mapping(v->domain, i);
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/* If no base IRQ was passed, figure out our allocated base */
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if (irq)
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v->irq = irq;
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else
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v->irq = irq_find_mapping(v->domain, 0);
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}
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static void vic_ack_irq(struct irq_data *d)
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{
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void __iomem *base = irq_data_get_irq_chip_data(d);
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unsigned int irq = d->hwirq;
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writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
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/* moreover, clear the soft-triggered, in case it was the reason */
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writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
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}
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static void vic_mask_irq(struct irq_data *d)
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{
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void __iomem *base = irq_data_get_irq_chip_data(d);
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unsigned int irq = d->hwirq;
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writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
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}
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static void vic_unmask_irq(struct irq_data *d)
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{
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void __iomem *base = irq_data_get_irq_chip_data(d);
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unsigned int irq = d->hwirq;
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writel(1 << irq, base + VIC_INT_ENABLE);
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}
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#if defined(CONFIG_PM)
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static struct vic_device *vic_from_irq(unsigned int irq)
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{
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struct vic_device *v = vic_devices;
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unsigned int base_irq = irq & ~31;
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int id;
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for (id = 0; id < vic_id; id++, v++) {
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if (v->irq == base_irq)
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return v;
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}
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return NULL;
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}
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static int vic_set_wake(struct irq_data *d, unsigned int on)
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{
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struct vic_device *v = vic_from_irq(d->irq);
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unsigned int off = d->hwirq;
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u32 bit = 1 << off;
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if (!v)
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return -EINVAL;
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if (!(bit & v->resume_sources))
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return -EINVAL;
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if (on)
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v->resume_irqs |= bit;
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else
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v->resume_irqs &= ~bit;
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return 0;
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}
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#else
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#define vic_set_wake NULL
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#endif /* CONFIG_PM */
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static struct irq_chip vic_chip = {
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.name = "VIC",
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.irq_ack = vic_ack_irq,
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.irq_mask = vic_mask_irq,
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.irq_unmask = vic_unmask_irq,
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.irq_set_wake = vic_set_wake,
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};
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static void __init vic_disable(void __iomem *base)
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{
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writel(0, base + VIC_INT_SELECT);
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writel(0, base + VIC_INT_ENABLE);
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writel(~0, base + VIC_INT_ENABLE_CLEAR);
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writel(0, base + VIC_ITCR);
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writel(~0, base + VIC_INT_SOFT_CLEAR);
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}
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static void __init vic_clear_interrupts(void __iomem *base)
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{
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unsigned int i;
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writel(0, base + VIC_PL190_VECT_ADDR);
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for (i = 0; i < 19; i++) {
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unsigned int value;
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value = readl(base + VIC_PL190_VECT_ADDR);
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writel(value, base + VIC_PL190_VECT_ADDR);
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}
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}
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/*
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* The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
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* The original cell has 32 interrupts, while the modified one has 64,
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* replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
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* the probe function is called twice, with base set to offset 000
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* and 020 within the page. We call this "second block".
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*/
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static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
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u32 vic_sources, struct device_node *node)
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{
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unsigned int i;
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int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
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/* Disable all interrupts initially. */
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vic_disable(base);
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/*
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* Make sure we clear all existing interrupts. The vector registers
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* in this cell are after the second block of general registers,
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* so we can address them using standard offsets, but only from
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* the second base address, which is 0x20 in the page
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*/
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if (vic_2nd_block) {
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vic_clear_interrupts(base);
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/* ST has 16 vectors as well, but we don't enable them by now */
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for (i = 0; i < 16; i++) {
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void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
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writel(0, reg);
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}
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writel(32, base + VIC_PL190_DEF_VECT_ADDR);
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}
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vic_register(base, 0, irq_start, vic_sources, 0, node);
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}
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void __init __vic_init(void __iomem *base, int parent_irq, int irq_start,
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u32 vic_sources, u32 resume_sources,
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struct device_node *node)
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{
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unsigned int i;
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u32 cellid = 0;
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enum amba_vendor vendor;
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/* Identify which VIC cell this one is, by reading the ID */
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for (i = 0; i < 4; i++) {
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void __iomem *addr;
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addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
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cellid |= (readl(addr) & 0xff) << (8 * i);
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}
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vendor = (cellid >> 12) & 0xff;
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printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
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base, cellid, vendor);
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switch(vendor) {
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case AMBA_VENDOR_ST:
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vic_init_st(base, irq_start, vic_sources, node);
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return;
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default:
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printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
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/* fall through */
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case AMBA_VENDOR_ARM:
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break;
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}
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/* Disable all interrupts initially. */
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vic_disable(base);
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/* Make sure we clear all existing interrupts */
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vic_clear_interrupts(base);
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vic_init2(base);
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vic_register(base, parent_irq, irq_start, vic_sources, resume_sources, node);
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}
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/**
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* vic_init() - initialise a vectored interrupt controller
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* @base: iomem base address
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* @irq_start: starting interrupt number, must be muliple of 32
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* @vic_sources: bitmask of interrupt sources to allow
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* @resume_sources: bitmask of interrupt sources to allow for resume
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*/
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void __init vic_init(void __iomem *base, unsigned int irq_start,
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u32 vic_sources, u32 resume_sources)
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{
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__vic_init(base, 0, irq_start, vic_sources, resume_sources, NULL);
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}
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/**
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* vic_init_cascaded() - initialise a cascaded vectored interrupt controller
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* @base: iomem base address
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* @parent_irq: the parent IRQ we're cascaded off
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* @vic_sources: bitmask of interrupt sources to allow
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* @resume_sources: bitmask of interrupt sources to allow for resume
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*
|
|
* This returns the base for the new interrupts or negative on error.
|
|
*/
|
|
int __init vic_init_cascaded(void __iomem *base, unsigned int parent_irq,
|
|
u32 vic_sources, u32 resume_sources)
|
|
{
|
|
struct vic_device *v;
|
|
|
|
v = &vic_devices[vic_id];
|
|
__vic_init(base, parent_irq, 0, vic_sources, resume_sources, NULL);
|
|
/* Return out acquired base */
|
|
return v->irq;
|
|
}
|
|
EXPORT_SYMBOL_GPL(vic_init_cascaded);
|
|
|
|
#ifdef CONFIG_OF
|
|
static int __init vic_of_init(struct device_node *node,
|
|
struct device_node *parent)
|
|
{
|
|
void __iomem *regs;
|
|
u32 interrupt_mask = ~0;
|
|
u32 wakeup_mask = ~0;
|
|
|
|
if (WARN(parent, "non-root VICs are not supported"))
|
|
return -EINVAL;
|
|
|
|
regs = of_iomap(node, 0);
|
|
if (WARN_ON(!regs))
|
|
return -EIO;
|
|
|
|
of_property_read_u32(node, "valid-mask", &interrupt_mask);
|
|
of_property_read_u32(node, "valid-wakeup-mask", &wakeup_mask);
|
|
|
|
/*
|
|
* Passing 0 as first IRQ makes the simple domain allocate descriptors
|
|
*/
|
|
__vic_init(regs, 0, 0, interrupt_mask, wakeup_mask, node);
|
|
|
|
return 0;
|
|
}
|
|
IRQCHIP_DECLARE(arm_pl190_vic, "arm,pl190-vic", vic_of_init);
|
|
IRQCHIP_DECLARE(arm_pl192_vic, "arm,pl192-vic", vic_of_init);
|
|
IRQCHIP_DECLARE(arm_versatile_vic, "arm,versatile-vic", vic_of_init);
|
|
#endif /* CONFIG OF */
|