151 строка
3.3 KiB
C
151 строка
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/smp.h>
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#include <linux/spinlock.h>
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#include <linux/stop_machine.h>
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#include <linux/uaccess.h>
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#include <asm/cacheflush.h>
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#include <asm/fixmap.h>
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#include <asm/insn.h>
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#include <asm/kprobes.h>
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#include <asm/patching.h>
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#include <asm/sections.h>
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static DEFINE_RAW_SPINLOCK(patch_lock);
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static bool is_exit_text(unsigned long addr)
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{
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/* discarded with init text/data */
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return system_state < SYSTEM_RUNNING &&
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addr >= (unsigned long)__exittext_begin &&
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addr < (unsigned long)__exittext_end;
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}
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static bool is_image_text(unsigned long addr)
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{
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return core_kernel_text(addr) || is_exit_text(addr);
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}
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static void __kprobes *patch_map(void *addr, int fixmap)
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{
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unsigned long uintaddr = (uintptr_t) addr;
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bool image = is_image_text(uintaddr);
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struct page *page;
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if (image)
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page = phys_to_page(__pa_symbol(addr));
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else if (IS_ENABLED(CONFIG_STRICT_MODULE_RWX))
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page = vmalloc_to_page(addr);
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else
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return addr;
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BUG_ON(!page);
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return (void *)set_fixmap_offset(fixmap, page_to_phys(page) +
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(uintaddr & ~PAGE_MASK));
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}
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static void __kprobes patch_unmap(int fixmap)
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{
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clear_fixmap(fixmap);
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}
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/*
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* In ARMv8-A, A64 instructions have a fixed length of 32 bits and are always
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* little-endian.
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*/
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int __kprobes aarch64_insn_read(void *addr, u32 *insnp)
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{
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int ret;
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__le32 val;
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ret = copy_from_kernel_nofault(&val, addr, AARCH64_INSN_SIZE);
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if (!ret)
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*insnp = le32_to_cpu(val);
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return ret;
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}
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static int __kprobes __aarch64_insn_write(void *addr, __le32 insn)
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{
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void *waddr = addr;
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unsigned long flags = 0;
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int ret;
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raw_spin_lock_irqsave(&patch_lock, flags);
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waddr = patch_map(addr, FIX_TEXT_POKE0);
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ret = copy_to_kernel_nofault(waddr, &insn, AARCH64_INSN_SIZE);
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patch_unmap(FIX_TEXT_POKE0);
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raw_spin_unlock_irqrestore(&patch_lock, flags);
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return ret;
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}
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int __kprobes aarch64_insn_write(void *addr, u32 insn)
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{
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return __aarch64_insn_write(addr, cpu_to_le32(insn));
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}
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int __kprobes aarch64_insn_patch_text_nosync(void *addr, u32 insn)
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{
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u32 *tp = addr;
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int ret;
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/* A64 instructions must be word aligned */
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if ((uintptr_t)tp & 0x3)
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return -EINVAL;
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ret = aarch64_insn_write(tp, insn);
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if (ret == 0)
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caches_clean_inval_pou((uintptr_t)tp,
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(uintptr_t)tp + AARCH64_INSN_SIZE);
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return ret;
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}
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struct aarch64_insn_patch {
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void **text_addrs;
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u32 *new_insns;
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int insn_cnt;
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atomic_t cpu_count;
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};
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static int __kprobes aarch64_insn_patch_text_cb(void *arg)
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{
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int i, ret = 0;
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struct aarch64_insn_patch *pp = arg;
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/* The first CPU becomes master */
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if (atomic_inc_return(&pp->cpu_count) == 1) {
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for (i = 0; ret == 0 && i < pp->insn_cnt; i++)
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ret = aarch64_insn_patch_text_nosync(pp->text_addrs[i],
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pp->new_insns[i]);
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/* Notify other processors with an additional increment. */
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atomic_inc(&pp->cpu_count);
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} else {
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while (atomic_read(&pp->cpu_count) <= num_online_cpus())
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cpu_relax();
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isb();
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}
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return ret;
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}
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int __kprobes aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt)
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{
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struct aarch64_insn_patch patch = {
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.text_addrs = addrs,
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.new_insns = insns,
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.insn_cnt = cnt,
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.cpu_count = ATOMIC_INIT(0),
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};
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if (cnt <= 0)
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return -EINVAL;
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return stop_machine_cpuslocked(aarch64_insn_patch_text_cb, &patch,
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cpu_online_mask);
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}
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