639 строки
17 KiB
C
639 строки
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (c) 2014 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* Copyright (c) 2016 Rockchip Electronics Co. Ltd.
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* Author: Xing Zheng <zhengxing@rock-chips.com>
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*
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* based on
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*
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* samsung/clk.c
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* Copyright (c) 2013 Linaro Ltd.
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* Author: Thomas Abraham <thomas.ab@samsung.com>
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*/
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <linux/reboot.h>
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#include <linux/rational.h>
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#include "clk.h"
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/**
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* Register a clock branch.
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* Most clock branches have a form like
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*
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* src1 --|--\
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* |M |--[GATE]-[DIV]-
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* src2 --|--/
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*
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* sometimes without one of those components.
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*/
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static struct clk *rockchip_clk_register_branch(const char *name,
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const char *const *parent_names, u8 num_parents,
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void __iomem *base,
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int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
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int div_offset, u8 div_shift, u8 div_width, u8 div_flags,
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struct clk_div_table *div_table, int gate_offset,
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u8 gate_shift, u8 gate_flags, unsigned long flags,
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spinlock_t *lock)
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{
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struct clk *clk;
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struct clk_mux *mux = NULL;
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struct clk_gate *gate = NULL;
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struct clk_divider *div = NULL;
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const struct clk_ops *mux_ops = NULL, *div_ops = NULL,
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*gate_ops = NULL;
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int ret;
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if (num_parents > 1) {
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mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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if (!mux)
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return ERR_PTR(-ENOMEM);
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mux->reg = base + muxdiv_offset;
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mux->shift = mux_shift;
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mux->mask = BIT(mux_width) - 1;
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mux->flags = mux_flags;
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mux->lock = lock;
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mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
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: &clk_mux_ops;
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}
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if (gate_offset >= 0) {
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate) {
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ret = -ENOMEM;
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goto err_gate;
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}
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gate->flags = gate_flags;
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gate->reg = base + gate_offset;
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gate->bit_idx = gate_shift;
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gate->lock = lock;
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gate_ops = &clk_gate_ops;
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}
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if (div_width > 0) {
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div = kzalloc(sizeof(*div), GFP_KERNEL);
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if (!div) {
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ret = -ENOMEM;
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goto err_div;
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}
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div->flags = div_flags;
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if (div_offset)
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div->reg = base + div_offset;
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else
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div->reg = base + muxdiv_offset;
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div->shift = div_shift;
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div->width = div_width;
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div->lock = lock;
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div->table = div_table;
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div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
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? &clk_divider_ro_ops
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: &clk_divider_ops;
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}
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clk = clk_register_composite(NULL, name, parent_names, num_parents,
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mux ? &mux->hw : NULL, mux_ops,
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div ? &div->hw : NULL, div_ops,
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gate ? &gate->hw : NULL, gate_ops,
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flags);
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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goto err_composite;
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}
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return clk;
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err_composite:
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kfree(div);
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err_div:
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kfree(gate);
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err_gate:
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kfree(mux);
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return ERR_PTR(ret);
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}
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struct rockchip_clk_frac {
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struct notifier_block clk_nb;
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struct clk_fractional_divider div;
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struct clk_gate gate;
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struct clk_mux mux;
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const struct clk_ops *mux_ops;
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int mux_frac_idx;
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bool rate_change_remuxed;
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int rate_change_idx;
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};
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#define to_rockchip_clk_frac_nb(nb) \
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container_of(nb, struct rockchip_clk_frac, clk_nb)
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static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct clk_notifier_data *ndata = data;
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struct rockchip_clk_frac *frac = to_rockchip_clk_frac_nb(nb);
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struct clk_mux *frac_mux = &frac->mux;
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int ret = 0;
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pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n",
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__func__, event, ndata->old_rate, ndata->new_rate);
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if (event == PRE_RATE_CHANGE) {
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frac->rate_change_idx =
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frac->mux_ops->get_parent(&frac_mux->hw);
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if (frac->rate_change_idx != frac->mux_frac_idx) {
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frac->mux_ops->set_parent(&frac_mux->hw,
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frac->mux_frac_idx);
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frac->rate_change_remuxed = 1;
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}
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} else if (event == POST_RATE_CHANGE) {
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/*
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* The POST_RATE_CHANGE notifier runs directly after the
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* divider clock is set in clk_change_rate, so we'll have
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* remuxed back to the original parent before clk_change_rate
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* reaches the mux itself.
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*/
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if (frac->rate_change_remuxed) {
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frac->mux_ops->set_parent(&frac_mux->hw,
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frac->rate_change_idx);
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frac->rate_change_remuxed = 0;
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}
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}
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return notifier_from_errno(ret);
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}
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/**
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* fractional divider must set that denominator is 20 times larger than
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* numerator to generate precise clock frequency.
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*/
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static void rockchip_fractional_approximation(struct clk_hw *hw,
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unsigned long rate, unsigned long *parent_rate,
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unsigned long *m, unsigned long *n)
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{
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struct clk_fractional_divider *fd = to_clk_fd(hw);
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unsigned long p_rate, p_parent_rate;
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struct clk_hw *p_parent;
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unsigned long scale;
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p_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
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if ((rate * 20 > p_rate) && (p_rate % rate != 0)) {
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p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
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p_parent_rate = clk_hw_get_rate(p_parent);
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*parent_rate = p_parent_rate;
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}
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/*
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* Get rate closer to *parent_rate to guarantee there is no overflow
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* for m and n. In the result it will be the nearest rate left shifted
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* by (scale - fd->nwidth) bits.
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*/
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scale = fls_long(*parent_rate / rate - 1);
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if (scale > fd->nwidth)
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rate <<= scale - fd->nwidth;
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rational_best_approximation(rate, *parent_rate,
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GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
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m, n);
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}
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static struct clk *rockchip_clk_register_frac_branch(
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struct rockchip_clk_provider *ctx, const char *name,
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const char *const *parent_names, u8 num_parents,
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void __iomem *base, int muxdiv_offset, u8 div_flags,
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int gate_offset, u8 gate_shift, u8 gate_flags,
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unsigned long flags, struct rockchip_clk_branch *child,
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spinlock_t *lock)
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{
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struct rockchip_clk_frac *frac;
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struct clk *clk;
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struct clk_gate *gate = NULL;
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struct clk_fractional_divider *div = NULL;
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const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
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if (muxdiv_offset < 0)
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return ERR_PTR(-EINVAL);
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if (child && child->branch_type != branch_mux) {
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pr_err("%s: fractional child clock for %s can only be a mux\n",
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__func__, name);
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return ERR_PTR(-EINVAL);
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}
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frac = kzalloc(sizeof(*frac), GFP_KERNEL);
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if (!frac)
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return ERR_PTR(-ENOMEM);
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if (gate_offset >= 0) {
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gate = &frac->gate;
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gate->flags = gate_flags;
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gate->reg = base + gate_offset;
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gate->bit_idx = gate_shift;
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gate->lock = lock;
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gate_ops = &clk_gate_ops;
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}
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div = &frac->div;
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div->flags = div_flags;
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div->reg = base + muxdiv_offset;
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div->mshift = 16;
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div->mwidth = 16;
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div->mmask = GENMASK(div->mwidth - 1, 0) << div->mshift;
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div->nshift = 0;
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div->nwidth = 16;
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div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
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div->lock = lock;
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div->approximation = rockchip_fractional_approximation;
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div_ops = &clk_fractional_divider_ops;
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clk = clk_register_composite(NULL, name, parent_names, num_parents,
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NULL, NULL,
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&div->hw, div_ops,
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gate ? &gate->hw : NULL, gate_ops,
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flags | CLK_SET_RATE_UNGATE);
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if (IS_ERR(clk)) {
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kfree(frac);
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return clk;
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}
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if (child) {
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struct clk_mux *frac_mux = &frac->mux;
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struct clk_init_data init;
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struct clk *mux_clk;
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int ret;
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frac->mux_frac_idx = match_string(child->parent_names,
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child->num_parents, name);
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frac->mux_ops = &clk_mux_ops;
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frac->clk_nb.notifier_call = rockchip_clk_frac_notifier_cb;
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frac_mux->reg = base + child->muxdiv_offset;
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frac_mux->shift = child->mux_shift;
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frac_mux->mask = BIT(child->mux_width) - 1;
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frac_mux->flags = child->mux_flags;
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frac_mux->lock = lock;
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frac_mux->hw.init = &init;
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init.name = child->name;
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init.flags = child->flags | CLK_SET_RATE_PARENT;
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init.ops = frac->mux_ops;
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init.parent_names = child->parent_names;
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init.num_parents = child->num_parents;
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mux_clk = clk_register(NULL, &frac_mux->hw);
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if (IS_ERR(mux_clk)) {
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kfree(frac);
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return clk;
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}
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rockchip_clk_add_lookup(ctx, mux_clk, child->id);
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/* notifier on the fraction divider to catch rate changes */
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if (frac->mux_frac_idx >= 0) {
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pr_debug("%s: found fractional parent in mux at pos %d\n",
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__func__, frac->mux_frac_idx);
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ret = clk_notifier_register(clk, &frac->clk_nb);
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if (ret)
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pr_err("%s: failed to register clock notifier for %s\n",
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__func__, name);
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} else {
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pr_warn("%s: could not find %s as parent of %s, rate changes may not work\n",
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__func__, name, child->name);
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}
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}
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return clk;
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}
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static struct clk *rockchip_clk_register_factor_branch(const char *name,
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const char *const *parent_names, u8 num_parents,
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void __iomem *base, unsigned int mult, unsigned int div,
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int gate_offset, u8 gate_shift, u8 gate_flags,
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unsigned long flags, spinlock_t *lock)
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{
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struct clk *clk;
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struct clk_gate *gate = NULL;
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struct clk_fixed_factor *fix = NULL;
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/* without gate, register a simple factor clock */
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if (gate_offset == 0) {
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return clk_register_fixed_factor(NULL, name,
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parent_names[0], flags, mult,
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div);
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}
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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gate->flags = gate_flags;
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gate->reg = base + gate_offset;
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gate->bit_idx = gate_shift;
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gate->lock = lock;
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fix = kzalloc(sizeof(*fix), GFP_KERNEL);
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if (!fix) {
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kfree(gate);
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return ERR_PTR(-ENOMEM);
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}
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fix->mult = mult;
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fix->div = div;
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clk = clk_register_composite(NULL, name, parent_names, num_parents,
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NULL, NULL,
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&fix->hw, &clk_fixed_factor_ops,
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&gate->hw, &clk_gate_ops, flags);
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if (IS_ERR(clk)) {
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kfree(fix);
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kfree(gate);
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}
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return clk;
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}
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struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
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void __iomem *base, unsigned long nr_clks)
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{
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struct rockchip_clk_provider *ctx;
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struct clk **clk_table;
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int i;
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ctx = kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL);
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if (!ctx)
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return ERR_PTR(-ENOMEM);
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clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
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if (!clk_table)
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goto err_free;
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for (i = 0; i < nr_clks; ++i)
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clk_table[i] = ERR_PTR(-ENOENT);
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ctx->reg_base = base;
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ctx->clk_data.clks = clk_table;
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ctx->clk_data.clk_num = nr_clks;
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ctx->cru_node = np;
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spin_lock_init(&ctx->lock);
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ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
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"rockchip,grf");
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return ctx;
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err_free:
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kfree(ctx);
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return ERR_PTR(-ENOMEM);
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}
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void __init rockchip_clk_of_add_provider(struct device_node *np,
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struct rockchip_clk_provider *ctx)
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{
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if (of_clk_add_provider(np, of_clk_src_onecell_get,
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&ctx->clk_data))
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pr_err("%s: could not register clk provider\n", __func__);
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}
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void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
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struct clk *clk, unsigned int id)
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{
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if (ctx->clk_data.clks && id)
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ctx->clk_data.clks[id] = clk;
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}
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void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
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struct rockchip_pll_clock *list,
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unsigned int nr_pll, int grf_lock_offset)
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{
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struct clk *clk;
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int idx;
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for (idx = 0; idx < nr_pll; idx++, list++) {
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clk = rockchip_clk_register_pll(ctx, list->type, list->name,
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list->parent_names, list->num_parents,
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list->con_offset, grf_lock_offset,
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list->lock_shift, list->mode_offset,
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list->mode_shift, list->rate_table,
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list->flags, list->pll_flags);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register clock %s\n", __func__,
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list->name);
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continue;
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}
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rockchip_clk_add_lookup(ctx, clk, list->id);
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}
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}
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void __init rockchip_clk_register_branches(
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struct rockchip_clk_provider *ctx,
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struct rockchip_clk_branch *list,
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unsigned int nr_clk)
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{
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struct clk *clk = NULL;
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unsigned int idx;
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unsigned long flags;
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for (idx = 0; idx < nr_clk; idx++, list++) {
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flags = list->flags;
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/* catch simple muxes */
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switch (list->branch_type) {
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case branch_mux:
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clk = clk_register_mux(NULL, list->name,
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list->parent_names, list->num_parents,
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flags, ctx->reg_base + list->muxdiv_offset,
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list->mux_shift, list->mux_width,
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list->mux_flags, &ctx->lock);
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break;
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case branch_muxgrf:
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clk = rockchip_clk_register_muxgrf(list->name,
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list->parent_names, list->num_parents,
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flags, ctx->grf, list->muxdiv_offset,
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list->mux_shift, list->mux_width,
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list->mux_flags);
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break;
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case branch_divider:
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if (list->div_table)
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clk = clk_register_divider_table(NULL,
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list->name, list->parent_names[0],
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flags,
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ctx->reg_base + list->muxdiv_offset,
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list->div_shift, list->div_width,
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list->div_flags, list->div_table,
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&ctx->lock);
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else
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clk = clk_register_divider(NULL, list->name,
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list->parent_names[0], flags,
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ctx->reg_base + list->muxdiv_offset,
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list->div_shift, list->div_width,
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list->div_flags, &ctx->lock);
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break;
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case branch_fraction_divider:
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clk = rockchip_clk_register_frac_branch(ctx, list->name,
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list->parent_names, list->num_parents,
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ctx->reg_base, list->muxdiv_offset,
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list->div_flags,
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list->gate_offset, list->gate_shift,
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list->gate_flags, flags, list->child,
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&ctx->lock);
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break;
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case branch_half_divider:
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clk = rockchip_clk_register_halfdiv(list->name,
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list->parent_names, list->num_parents,
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ctx->reg_base, list->muxdiv_offset,
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list->mux_shift, list->mux_width,
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list->mux_flags, list->div_shift,
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list->div_width, list->div_flags,
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list->gate_offset, list->gate_shift,
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list->gate_flags, flags, &ctx->lock);
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break;
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case branch_gate:
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flags |= CLK_SET_RATE_PARENT;
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clk = clk_register_gate(NULL, list->name,
|
|
list->parent_names[0], flags,
|
|
ctx->reg_base + list->gate_offset,
|
|
list->gate_shift, list->gate_flags, &ctx->lock);
|
|
break;
|
|
case branch_composite:
|
|
clk = rockchip_clk_register_branch(list->name,
|
|
list->parent_names, list->num_parents,
|
|
ctx->reg_base, list->muxdiv_offset,
|
|
list->mux_shift,
|
|
list->mux_width, list->mux_flags,
|
|
list->div_offset, list->div_shift, list->div_width,
|
|
list->div_flags, list->div_table,
|
|
list->gate_offset, list->gate_shift,
|
|
list->gate_flags, flags, &ctx->lock);
|
|
break;
|
|
case branch_mmc:
|
|
clk = rockchip_clk_register_mmc(
|
|
list->name,
|
|
list->parent_names, list->num_parents,
|
|
ctx->reg_base + list->muxdiv_offset,
|
|
list->div_shift
|
|
);
|
|
break;
|
|
case branch_inverter:
|
|
clk = rockchip_clk_register_inverter(
|
|
list->name, list->parent_names,
|
|
list->num_parents,
|
|
ctx->reg_base + list->muxdiv_offset,
|
|
list->div_shift, list->div_flags, &ctx->lock);
|
|
break;
|
|
case branch_factor:
|
|
clk = rockchip_clk_register_factor_branch(
|
|
list->name, list->parent_names,
|
|
list->num_parents, ctx->reg_base,
|
|
list->div_shift, list->div_width,
|
|
list->gate_offset, list->gate_shift,
|
|
list->gate_flags, flags, &ctx->lock);
|
|
break;
|
|
case branch_ddrclk:
|
|
clk = rockchip_clk_register_ddrclk(
|
|
list->name, list->flags,
|
|
list->parent_names, list->num_parents,
|
|
list->muxdiv_offset, list->mux_shift,
|
|
list->mux_width, list->div_shift,
|
|
list->div_width, list->div_flags,
|
|
ctx->reg_base, &ctx->lock);
|
|
break;
|
|
}
|
|
|
|
/* none of the cases above matched */
|
|
if (!clk) {
|
|
pr_err("%s: unknown clock type %d\n",
|
|
__func__, list->branch_type);
|
|
continue;
|
|
}
|
|
|
|
if (IS_ERR(clk)) {
|
|
pr_err("%s: failed to register clock %s: %ld\n",
|
|
__func__, list->name, PTR_ERR(clk));
|
|
continue;
|
|
}
|
|
|
|
rockchip_clk_add_lookup(ctx, clk, list->id);
|
|
}
|
|
}
|
|
|
|
void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
|
|
unsigned int lookup_id,
|
|
const char *name, const char *const *parent_names,
|
|
u8 num_parents,
|
|
const struct rockchip_cpuclk_reg_data *reg_data,
|
|
const struct rockchip_cpuclk_rate_table *rates,
|
|
int nrates)
|
|
{
|
|
struct clk *clk;
|
|
|
|
clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents,
|
|
reg_data, rates, nrates,
|
|
ctx->reg_base, &ctx->lock);
|
|
if (IS_ERR(clk)) {
|
|
pr_err("%s: failed to register clock %s: %ld\n",
|
|
__func__, name, PTR_ERR(clk));
|
|
return;
|
|
}
|
|
|
|
rockchip_clk_add_lookup(ctx, clk, lookup_id);
|
|
}
|
|
|
|
void __init rockchip_clk_protect_critical(const char *const clocks[],
|
|
int nclocks)
|
|
{
|
|
int i;
|
|
|
|
/* Protect the clocks that needs to stay on */
|
|
for (i = 0; i < nclocks; i++) {
|
|
struct clk *clk = __clk_lookup(clocks[i]);
|
|
|
|
if (clk)
|
|
clk_prepare_enable(clk);
|
|
}
|
|
}
|
|
|
|
static void __iomem *rst_base;
|
|
static unsigned int reg_restart;
|
|
static void (*cb_restart)(void);
|
|
static int rockchip_restart_notify(struct notifier_block *this,
|
|
unsigned long mode, void *cmd)
|
|
{
|
|
if (cb_restart)
|
|
cb_restart();
|
|
|
|
writel(0xfdb9, rst_base + reg_restart);
|
|
return NOTIFY_DONE;
|
|
}
|
|
|
|
static struct notifier_block rockchip_restart_handler = {
|
|
.notifier_call = rockchip_restart_notify,
|
|
.priority = 128,
|
|
};
|
|
|
|
void __init
|
|
rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
|
|
unsigned int reg,
|
|
void (*cb)(void))
|
|
{
|
|
int ret;
|
|
|
|
rst_base = ctx->reg_base;
|
|
reg_restart = reg;
|
|
cb_restart = cb;
|
|
ret = register_restart_handler(&rockchip_restart_handler);
|
|
if (ret)
|
|
pr_err("%s: cannot register restart handler, %d\n",
|
|
__func__, ret);
|
|
}
|