Hansen 5a1fef0278 drm/amd/display: Fix detection of 4 lane for DPALT ... [Why] DPALT detection for B0 PHY has its own set of RDPCSPIPE registers [How] Use RDPCSPIPE registers to detect if DPALT lane is 4 lane Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Hansen <Hansen.Dsouza@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org		2021-10-06 16:14:17 -04:00
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amdgpu	drm/amdgpu: handle the case of pci_channel_io_frozen only in amdgpu_pci_resume	2021-10-05 13:02:31 -04:00
amdkfd	drm/amdkfd: remove redundant iommu cleanup code	2021-10-05 13:02:13 -04:00
display	drm/amd/display: Fix detection of 4 lane for DPALT	2021-10-06 16:14:17 -04:00
include	drm/amd/display: Fix B0 USB-C DP Alt mode	2021-10-05 10:17:32 -04:00
pm	drm/amd/pm: Update intermediate power state for SI	2021-09-23 17:06:11 -04:00