472 строки
12 KiB
ArmAsm
472 строки
12 KiB
ArmAsm
/*
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* linux/arch/arm/mm/proc-feroceon.S: MMU functions for Feroceon
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*
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* Heavily based on proc-arm926.S
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* Maintainer: Assaf Hoffman <hoffman@marvell.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/elf.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#include "proc-macros.S"
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/*
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* This is the maximum size of an area which will be invalidated
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* using the single invalidate entry instructions. Anything larger
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* than this, and we go for the whole cache.
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*
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* This value should be chosen such that we choose the cheapest
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* alternative.
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*/
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#define CACHE_DLIMIT 16384
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/*
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* the cache line size of the I and D cache
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*/
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#define CACHE_DLINESIZE 32
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.text
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/*
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* cpu_feroceon_proc_init()
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*/
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ENTRY(cpu_feroceon_proc_init)
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mov pc, lr
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/*
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* cpu_feroceon_proc_fin()
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*/
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ENTRY(cpu_feroceon_proc_fin)
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stmfd sp!, {lr}
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mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
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msr cpsr_c, ip
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bl feroceon_flush_kern_cache_all
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x1000 @ ...i............
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bic r0, r0, #0x000e @ ............wca.
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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ldmfd sp!, {pc}
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/*
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* cpu_feroceon_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* loc: location to jump to for soft reset
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*/
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.align 5
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ENTRY(cpu_feroceon_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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#ifdef CONFIG_MMU
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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#endif
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mrc p15, 0, ip, c1, c0, 0 @ ctrl register
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bic ip, ip, #0x000f @ ............wcam
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bic ip, ip, #0x1100 @ ...i...s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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/*
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* cpu_feroceon_do_idle()
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*
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* Called with IRQs disabled
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*/
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.align 5
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ENTRY(cpu_feroceon_do_idle)
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
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mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
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mov pc, lr
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/*
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* flush_user_cache_all()
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*
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* Clean and invalidate all cache entries in a particular
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* address space.
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*/
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.align 5
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ENTRY(feroceon_flush_user_cache_all)
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/* FALLTHROUGH */
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/*
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* flush_kern_cache_all()
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*
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* Clean and invalidate the entire cache.
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*/
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ENTRY(feroceon_flush_kern_cache_all)
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mov r2, #VM_EXEC
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mov ip, #0
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__flush_whole_cache:
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1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
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bne 1b
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* flush_user_cache_range(start, end, flags)
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*
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* Clean and invalidate a range of cache entries in the
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* specified address range.
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*
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* - start - start address (inclusive)
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* - end - end address (exclusive)
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* - flags - vm_flags describing address space
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*/
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.align 5
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ENTRY(feroceon_flush_user_cache_range)
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mov ip, #0
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sub r3, r1, r0 @ calculate total size
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cmp r3, #CACHE_DLIMIT
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bgt __flush_whole_cache
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1: tst r2, #VM_EXEC
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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.align 5
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ENTRY(feroceon_coherent_kern_range)
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/* FALLTHROUGH */
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/*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(feroceon_coherent_user_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* flush_kern_dcache_page(void *page)
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*
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* Ensure no D cache aliasing occurs, either with itself or
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* the I cache
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*
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* - addr - page aligned address
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*/
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.align 5
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ENTRY(feroceon_flush_kern_dcache_page)
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add r1, r0, #PAGE_SZ
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_inv_range(start, end)
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*
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* Invalidate (discard) the specified virtual address range.
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* May not write back any entries. If 'start' or 'end'
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* are not cache line aligned, those lines must be written
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* back.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* (same as v4wb)
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*/
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.align 5
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ENTRY(feroceon_dma_inv_range)
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tst r0, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
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tst r1, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_clean_range(start, end)
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*
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* Clean the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* (same as v4wb)
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*/
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.align 5
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ENTRY(feroceon_dma_clean_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_flush_range(start, end)
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*
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* Clean and invalidate the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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.align 5
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ENTRY(feroceon_dma_flush_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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ENTRY(feroceon_cache_fns)
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.long feroceon_flush_kern_cache_all
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.long feroceon_flush_user_cache_all
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.long feroceon_flush_user_cache_range
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.long feroceon_coherent_kern_range
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.long feroceon_coherent_user_range
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.long feroceon_flush_kern_dcache_page
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.long feroceon_dma_inv_range
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.long feroceon_dma_clean_range
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.long feroceon_dma_flush_range
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.align 5
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ENTRY(cpu_feroceon_dcache_clean_area)
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHE_DLINESIZE
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subs r1, r1, #CACHE_DLINESIZE
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bhi 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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/* =============================== PageTable ============================== */
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/*
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* cpu_feroceon_switch_mm(pgd)
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*
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* Set the translation base pointer to be as described by pgd.
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*
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* pgd: new page tables
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*/
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.align 5
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ENTRY(cpu_feroceon_switch_mm)
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#ifdef CONFIG_MMU
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mov ip, #0
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@ && 'Clean & Invalidate whole DCache'
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1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
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bne 1b
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mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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#endif
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mov pc, lr
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/*
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* cpu_feroceon_set_pte_ext(ptep, pte, ext)
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*
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* Set a PTE and flush it out
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*/
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.align 5
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ENTRY(cpu_feroceon_set_pte_ext)
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#ifdef CONFIG_MMU
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str r1, [r0], #-2048 @ linux version
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eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
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bic r2, r1, #PTE_SMALL_AP_MASK
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bic r2, r2, #PTE_TYPE_MASK
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orr r2, r2, #PTE_TYPE_SMALL
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tst r1, #L_PTE_USER @ User?
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orrne r2, r2, #PTE_SMALL_AP_URO_SRW
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tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
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orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
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tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
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movne r2, #0
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str r2, [r0] @ hardware version
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mov r0, r0
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mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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#endif
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mov pc, lr
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__INIT
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.type __feroceon_setup, #function
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__feroceon_setup:
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mov r0, #0
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mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
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#ifdef CONFIG_MMU
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mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
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#endif
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adr r5, feroceon_crval
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ldmia r5, {r5, r6}
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mrc p15, 0, r0, c1, c0 @ get control register v4
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bic r0, r0, r5
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orr r0, r0, r6
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mov pc, lr
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.size __feroceon_setup, . - __feroceon_setup
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/*
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* R
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* .RVI ZFRS BLDP WCAM
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* .011 0001 ..11 0101
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*
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*/
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.type feroceon_crval, #object
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feroceon_crval:
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crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
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__INITDATA
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/*
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* Purpose : Function pointers used to access above functions - all calls
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* come through these
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*/
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.type feroceon_processor_functions, #object
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feroceon_processor_functions:
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.word v5t_early_abort
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.word pabort_noifar
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.word cpu_feroceon_proc_init
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.word cpu_feroceon_proc_fin
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.word cpu_feroceon_reset
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.word cpu_feroceon_do_idle
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.word cpu_feroceon_dcache_clean_area
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.word cpu_feroceon_switch_mm
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.word cpu_feroceon_set_pte_ext
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.size feroceon_processor_functions, . - feroceon_processor_functions
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.section ".rodata"
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.type cpu_arch_name, #object
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cpu_arch_name:
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.asciz "armv5te"
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.size cpu_arch_name, . - cpu_arch_name
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.type cpu_elf_name, #object
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cpu_elf_name:
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.asciz "v5"
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.size cpu_elf_name, . - cpu_elf_name
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.type cpu_feroceon_name, #object
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cpu_feroceon_name:
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.asciz "Feroceon"
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.size cpu_feroceon_name, . - cpu_feroceon_name
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.align
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.section ".proc.info.init", #alloc, #execinstr
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#ifdef CONFIG_CPU_FEROCEON_OLD_ID
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.type __feroceon_old_id_proc_info,#object
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__feroceon_old_id_proc_info:
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.long 0x41069260
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.long 0xfffffff0
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.long PMD_TYPE_SECT | \
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PMD_SECT_BUFFERABLE | \
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PMD_SECT_CACHEABLE | \
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PMD_BIT4 | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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.long PMD_TYPE_SECT | \
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PMD_BIT4 | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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b __feroceon_setup
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.long cpu_arch_name
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.long cpu_elf_name
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.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
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.long cpu_feroceon_name
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.long feroceon_processor_functions
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.long v4wbi_tlb_fns
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.long feroceon_user_fns
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.long feroceon_cache_fns
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.size __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info
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#endif
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.type __feroceon_proc_info,#object
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__feroceon_proc_info:
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.long 0x56055310
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.long 0xfffffff0
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.long PMD_TYPE_SECT | \
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PMD_SECT_BUFFERABLE | \
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PMD_SECT_CACHEABLE | \
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PMD_BIT4 | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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.long PMD_TYPE_SECT | \
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PMD_BIT4 | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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b __feroceon_setup
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.long cpu_arch_name
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.long cpu_elf_name
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.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
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.long cpu_feroceon_name
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.long feroceon_processor_functions
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.long v4wbi_tlb_fns
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.long feroceon_user_fns
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.long feroceon_cache_fns
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.size __feroceon_proc_info, . - __feroceon_proc_info
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