1210 строки
28 KiB
C
1210 строки
28 KiB
C
/* pci_sun4v.c: SUN4V specific PCI controller support.
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*
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* Copyright (C) 2006 David S. Miller (davem@davemloft.net)
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/percpu.h>
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#include <asm/pbm.h>
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#include <asm/iommu.h>
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#include <asm/irq.h>
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#include <asm/upa.h>
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#include <asm/pstate.h>
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#include <asm/oplib.h>
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#include <asm/hypervisor.h>
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#include <asm/prom.h>
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#include "pci_impl.h"
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#include "iommu_common.h"
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#include "pci_sun4v.h"
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#define PGLIST_NENTS (PAGE_SIZE / sizeof(u64))
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struct pci_iommu_batch {
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struct pci_dev *pdev; /* Device mapping is for. */
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unsigned long prot; /* IOMMU page protections */
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unsigned long entry; /* Index into IOTSB. */
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u64 *pglist; /* List of physical pages */
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unsigned long npages; /* Number of pages in list. */
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};
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static DEFINE_PER_CPU(struct pci_iommu_batch, pci_iommu_batch);
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/* Interrupts must be disabled. */
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static inline void pci_iommu_batch_start(struct pci_dev *pdev, unsigned long prot, unsigned long entry)
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{
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struct pci_iommu_batch *p = &__get_cpu_var(pci_iommu_batch);
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p->pdev = pdev;
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p->prot = prot;
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p->entry = entry;
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p->npages = 0;
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}
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/* Interrupts must be disabled. */
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static long pci_iommu_batch_flush(struct pci_iommu_batch *p)
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{
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struct pcidev_cookie *pcp = p->pdev->sysdata;
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unsigned long devhandle = pcp->pbm->devhandle;
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unsigned long prot = p->prot;
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unsigned long entry = p->entry;
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u64 *pglist = p->pglist;
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unsigned long npages = p->npages;
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while (npages != 0) {
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long num;
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num = pci_sun4v_iommu_map(devhandle, HV_PCI_TSBID(0, entry),
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npages, prot, __pa(pglist));
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if (unlikely(num < 0)) {
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if (printk_ratelimit())
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printk("pci_iommu_batch_flush: IOMMU map of "
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"[%08lx:%08lx:%lx:%lx:%lx] failed with "
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"status %ld\n",
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devhandle, HV_PCI_TSBID(0, entry),
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npages, prot, __pa(pglist), num);
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return -1;
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}
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entry += num;
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npages -= num;
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pglist += num;
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}
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p->entry = entry;
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p->npages = 0;
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return 0;
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}
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/* Interrupts must be disabled. */
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static inline long pci_iommu_batch_add(u64 phys_page)
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{
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struct pci_iommu_batch *p = &__get_cpu_var(pci_iommu_batch);
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BUG_ON(p->npages >= PGLIST_NENTS);
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p->pglist[p->npages++] = phys_page;
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if (p->npages == PGLIST_NENTS)
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return pci_iommu_batch_flush(p);
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return 0;
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}
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/* Interrupts must be disabled. */
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static inline long pci_iommu_batch_end(void)
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{
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struct pci_iommu_batch *p = &__get_cpu_var(pci_iommu_batch);
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BUG_ON(p->npages >= PGLIST_NENTS);
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return pci_iommu_batch_flush(p);
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}
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static long pci_arena_alloc(struct pci_iommu_arena *arena, unsigned long npages)
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{
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unsigned long n, i, start, end, limit;
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int pass;
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limit = arena->limit;
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start = arena->hint;
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pass = 0;
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again:
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n = find_next_zero_bit(arena->map, limit, start);
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end = n + npages;
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if (unlikely(end >= limit)) {
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if (likely(pass < 1)) {
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limit = start;
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start = 0;
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pass++;
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goto again;
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} else {
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/* Scanned the whole thing, give up. */
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return -1;
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}
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}
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for (i = n; i < end; i++) {
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if (test_bit(i, arena->map)) {
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start = i + 1;
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goto again;
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}
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}
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for (i = n; i < end; i++)
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__set_bit(i, arena->map);
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arena->hint = end;
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return n;
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}
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static void pci_arena_free(struct pci_iommu_arena *arena, unsigned long base, unsigned long npages)
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{
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unsigned long i;
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for (i = base; i < (base + npages); i++)
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__clear_bit(i, arena->map);
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}
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static void *pci_4v_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp, gfp_t gfp)
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{
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struct pcidev_cookie *pcp;
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struct pci_iommu *iommu;
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unsigned long flags, order, first_page, npages, n;
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void *ret;
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long entry;
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size = IO_PAGE_ALIGN(size);
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order = get_order(size);
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if (unlikely(order >= MAX_ORDER))
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return NULL;
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npages = size >> IO_PAGE_SHIFT;
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first_page = __get_free_pages(gfp, order);
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if (unlikely(first_page == 0UL))
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return NULL;
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memset((char *)first_page, 0, PAGE_SIZE << order);
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pcp = pdev->sysdata;
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iommu = pcp->pbm->iommu;
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spin_lock_irqsave(&iommu->lock, flags);
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entry = pci_arena_alloc(&iommu->arena, npages);
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spin_unlock_irqrestore(&iommu->lock, flags);
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if (unlikely(entry < 0L))
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goto arena_alloc_fail;
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*dma_addrp = (iommu->page_table_map_base +
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(entry << IO_PAGE_SHIFT));
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ret = (void *) first_page;
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first_page = __pa(first_page);
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local_irq_save(flags);
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pci_iommu_batch_start(pdev,
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(HV_PCI_MAP_ATTR_READ |
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HV_PCI_MAP_ATTR_WRITE),
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entry);
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for (n = 0; n < npages; n++) {
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long err = pci_iommu_batch_add(first_page + (n * PAGE_SIZE));
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if (unlikely(err < 0L))
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goto iommu_map_fail;
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}
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if (unlikely(pci_iommu_batch_end() < 0L))
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goto iommu_map_fail;
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local_irq_restore(flags);
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return ret;
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iommu_map_fail:
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/* Interrupts are disabled. */
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spin_lock(&iommu->lock);
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pci_arena_free(&iommu->arena, entry, npages);
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spin_unlock_irqrestore(&iommu->lock, flags);
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arena_alloc_fail:
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free_pages(first_page, order);
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return NULL;
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}
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static void pci_4v_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma)
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{
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struct pcidev_cookie *pcp;
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struct pci_iommu *iommu;
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unsigned long flags, order, npages, entry;
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u32 devhandle;
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npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
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pcp = pdev->sysdata;
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iommu = pcp->pbm->iommu;
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devhandle = pcp->pbm->devhandle;
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entry = ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
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spin_lock_irqsave(&iommu->lock, flags);
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pci_arena_free(&iommu->arena, entry, npages);
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do {
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unsigned long num;
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num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
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npages);
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entry += num;
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npages -= num;
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} while (npages != 0);
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spin_unlock_irqrestore(&iommu->lock, flags);
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order = get_order(size);
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if (order < 10)
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free_pages((unsigned long)cpu, order);
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}
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static dma_addr_t pci_4v_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction)
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{
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struct pcidev_cookie *pcp;
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struct pci_iommu *iommu;
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unsigned long flags, npages, oaddr;
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unsigned long i, base_paddr;
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u32 bus_addr, ret;
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unsigned long prot;
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long entry;
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pcp = pdev->sysdata;
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iommu = pcp->pbm->iommu;
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if (unlikely(direction == PCI_DMA_NONE))
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goto bad;
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oaddr = (unsigned long)ptr;
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npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
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npages >>= IO_PAGE_SHIFT;
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spin_lock_irqsave(&iommu->lock, flags);
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entry = pci_arena_alloc(&iommu->arena, npages);
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spin_unlock_irqrestore(&iommu->lock, flags);
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if (unlikely(entry < 0L))
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goto bad;
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bus_addr = (iommu->page_table_map_base +
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(entry << IO_PAGE_SHIFT));
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ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
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base_paddr = __pa(oaddr & IO_PAGE_MASK);
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prot = HV_PCI_MAP_ATTR_READ;
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if (direction != PCI_DMA_TODEVICE)
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prot |= HV_PCI_MAP_ATTR_WRITE;
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local_irq_save(flags);
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pci_iommu_batch_start(pdev, prot, entry);
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for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) {
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long err = pci_iommu_batch_add(base_paddr);
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if (unlikely(err < 0L))
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goto iommu_map_fail;
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}
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if (unlikely(pci_iommu_batch_end() < 0L))
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goto iommu_map_fail;
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local_irq_restore(flags);
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return ret;
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bad:
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if (printk_ratelimit())
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WARN_ON(1);
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return PCI_DMA_ERROR_CODE;
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iommu_map_fail:
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/* Interrupts are disabled. */
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spin_lock(&iommu->lock);
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pci_arena_free(&iommu->arena, entry, npages);
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spin_unlock_irqrestore(&iommu->lock, flags);
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return PCI_DMA_ERROR_CODE;
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}
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static void pci_4v_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
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{
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struct pcidev_cookie *pcp;
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struct pci_iommu *iommu;
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unsigned long flags, npages;
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long entry;
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u32 devhandle;
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if (unlikely(direction == PCI_DMA_NONE)) {
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if (printk_ratelimit())
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WARN_ON(1);
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return;
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}
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pcp = pdev->sysdata;
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iommu = pcp->pbm->iommu;
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devhandle = pcp->pbm->devhandle;
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npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
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npages >>= IO_PAGE_SHIFT;
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bus_addr &= IO_PAGE_MASK;
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spin_lock_irqsave(&iommu->lock, flags);
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entry = (bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT;
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pci_arena_free(&iommu->arena, entry, npages);
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do {
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unsigned long num;
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num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
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npages);
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entry += num;
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npages -= num;
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} while (npages != 0);
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spin_unlock_irqrestore(&iommu->lock, flags);
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}
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#define SG_ENT_PHYS_ADDRESS(SG) \
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(__pa(page_address((SG)->page)) + (SG)->offset)
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static inline long fill_sg(long entry, struct pci_dev *pdev,
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struct scatterlist *sg,
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int nused, int nelems, unsigned long prot)
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{
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struct scatterlist *dma_sg = sg;
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struct scatterlist *sg_end = sg + nelems;
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unsigned long flags;
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int i;
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local_irq_save(flags);
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pci_iommu_batch_start(pdev, prot, entry);
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for (i = 0; i < nused; i++) {
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unsigned long pteval = ~0UL;
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u32 dma_npages;
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dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) +
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dma_sg->dma_length +
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((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
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do {
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unsigned long offset;
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signed int len;
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/* If we are here, we know we have at least one
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* more page to map. So walk forward until we
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* hit a page crossing, and begin creating new
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* mappings from that spot.
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*/
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for (;;) {
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unsigned long tmp;
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tmp = SG_ENT_PHYS_ADDRESS(sg);
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len = sg->length;
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if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
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pteval = tmp & IO_PAGE_MASK;
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offset = tmp & (IO_PAGE_SIZE - 1UL);
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break;
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}
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if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
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pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
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offset = 0UL;
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len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
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break;
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}
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sg++;
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}
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pteval = (pteval & IOPTE_PAGE);
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while (len > 0) {
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long err;
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err = pci_iommu_batch_add(pteval);
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if (unlikely(err < 0L))
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goto iommu_map_failed;
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pteval += IO_PAGE_SIZE;
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len -= (IO_PAGE_SIZE - offset);
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offset = 0;
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dma_npages--;
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}
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pteval = (pteval & IOPTE_PAGE) + len;
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sg++;
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/* Skip over any tail mappings we've fully mapped,
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* adjusting pteval along the way. Stop when we
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* detect a page crossing event.
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*/
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while (sg < sg_end &&
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(pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
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(pteval == SG_ENT_PHYS_ADDRESS(sg)) &&
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((pteval ^
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(SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
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pteval += sg->length;
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sg++;
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}
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if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
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pteval = ~0UL;
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} while (dma_npages != 0);
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dma_sg++;
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}
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if (unlikely(pci_iommu_batch_end() < 0L))
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goto iommu_map_failed;
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local_irq_restore(flags);
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return 0;
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iommu_map_failed:
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local_irq_restore(flags);
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return -1L;
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}
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static int pci_4v_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
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{
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struct pcidev_cookie *pcp;
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struct pci_iommu *iommu;
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unsigned long flags, npages, prot;
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u32 dma_base;
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struct scatterlist *sgtmp;
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long entry, err;
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int used;
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/* Fast path single entry scatterlists. */
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if (nelems == 1) {
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sglist->dma_address =
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pci_4v_map_single(pdev,
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(page_address(sglist->page) + sglist->offset),
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sglist->length, direction);
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if (unlikely(sglist->dma_address == PCI_DMA_ERROR_CODE))
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return 0;
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sglist->dma_length = sglist->length;
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return 1;
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}
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pcp = pdev->sysdata;
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iommu = pcp->pbm->iommu;
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if (unlikely(direction == PCI_DMA_NONE))
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goto bad;
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/* Step 1: Prepare scatter list. */
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npages = prepare_sg(sglist, nelems);
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/* Step 2: Allocate a cluster and context, if necessary. */
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spin_lock_irqsave(&iommu->lock, flags);
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entry = pci_arena_alloc(&iommu->arena, npages);
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spin_unlock_irqrestore(&iommu->lock, flags);
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if (unlikely(entry < 0L))
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goto bad;
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dma_base = iommu->page_table_map_base +
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(entry << IO_PAGE_SHIFT);
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/* Step 3: Normalize DMA addresses. */
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used = nelems;
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sgtmp = sglist;
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while (used && sgtmp->dma_length) {
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sgtmp->dma_address += dma_base;
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sgtmp++;
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used--;
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}
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used = nelems - used;
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/* Step 4: Create the mappings. */
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prot = HV_PCI_MAP_ATTR_READ;
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if (direction != PCI_DMA_TODEVICE)
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prot |= HV_PCI_MAP_ATTR_WRITE;
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err = fill_sg(entry, pdev, sglist, used, nelems, prot);
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if (unlikely(err < 0L))
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goto iommu_map_failed;
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return used;
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bad:
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if (printk_ratelimit())
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WARN_ON(1);
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return 0;
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iommu_map_failed:
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spin_lock_irqsave(&iommu->lock, flags);
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pci_arena_free(&iommu->arena, entry, npages);
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void pci_4v_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
|
|
{
|
|
struct pcidev_cookie *pcp;
|
|
struct pci_iommu *iommu;
|
|
unsigned long flags, i, npages;
|
|
long entry;
|
|
u32 devhandle, bus_addr;
|
|
|
|
if (unlikely(direction == PCI_DMA_NONE)) {
|
|
if (printk_ratelimit())
|
|
WARN_ON(1);
|
|
}
|
|
|
|
pcp = pdev->sysdata;
|
|
iommu = pcp->pbm->iommu;
|
|
devhandle = pcp->pbm->devhandle;
|
|
|
|
bus_addr = sglist->dma_address & IO_PAGE_MASK;
|
|
|
|
for (i = 1; i < nelems; i++)
|
|
if (sglist[i].dma_length == 0)
|
|
break;
|
|
i--;
|
|
npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) -
|
|
bus_addr) >> IO_PAGE_SHIFT;
|
|
|
|
entry = ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
pci_arena_free(&iommu->arena, entry, npages);
|
|
|
|
do {
|
|
unsigned long num;
|
|
|
|
num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
|
|
npages);
|
|
entry += num;
|
|
npages -= num;
|
|
} while (npages != 0);
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
}
|
|
|
|
static void pci_4v_dma_sync_single_for_cpu(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
|
|
{
|
|
/* Nothing to do... */
|
|
}
|
|
|
|
static void pci_4v_dma_sync_sg_for_cpu(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
|
|
{
|
|
/* Nothing to do... */
|
|
}
|
|
|
|
struct pci_iommu_ops pci_sun4v_iommu_ops = {
|
|
.alloc_consistent = pci_4v_alloc_consistent,
|
|
.free_consistent = pci_4v_free_consistent,
|
|
.map_single = pci_4v_map_single,
|
|
.unmap_single = pci_4v_unmap_single,
|
|
.map_sg = pci_4v_map_sg,
|
|
.unmap_sg = pci_4v_unmap_sg,
|
|
.dma_sync_single_for_cpu = pci_4v_dma_sync_single_for_cpu,
|
|
.dma_sync_sg_for_cpu = pci_4v_dma_sync_sg_for_cpu,
|
|
};
|
|
|
|
/* SUN4V PCI configuration space accessors. */
|
|
|
|
struct pdev_entry {
|
|
struct pdev_entry *next;
|
|
u32 devhandle;
|
|
unsigned int bus;
|
|
unsigned int device;
|
|
unsigned int func;
|
|
};
|
|
|
|
#define PDEV_HTAB_SIZE 16
|
|
#define PDEV_HTAB_MASK (PDEV_HTAB_SIZE - 1)
|
|
static struct pdev_entry *pdev_htab[PDEV_HTAB_SIZE];
|
|
|
|
static inline unsigned int pdev_hashfn(u32 devhandle, unsigned int bus, unsigned int device, unsigned int func)
|
|
{
|
|
unsigned int val;
|
|
|
|
val = (devhandle ^ (devhandle >> 4));
|
|
val ^= bus;
|
|
val ^= device;
|
|
val ^= func;
|
|
|
|
return val & PDEV_HTAB_MASK;
|
|
}
|
|
|
|
static int pdev_htab_add(u32 devhandle, unsigned int bus, unsigned int device, unsigned int func)
|
|
{
|
|
struct pdev_entry *p = kmalloc(sizeof(*p), GFP_KERNEL);
|
|
struct pdev_entry **slot;
|
|
|
|
if (!p)
|
|
return -ENOMEM;
|
|
|
|
slot = &pdev_htab[pdev_hashfn(devhandle, bus, device, func)];
|
|
p->next = *slot;
|
|
*slot = p;
|
|
|
|
p->devhandle = devhandle;
|
|
p->bus = bus;
|
|
p->device = device;
|
|
p->func = func;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Recursively descend into the OBP device tree, rooted at toplevel_node,
|
|
* looking for a PCI device matching bus and devfn.
|
|
*/
|
|
static int obp_find(struct device_node *toplevel_node, unsigned int bus, unsigned int devfn)
|
|
{
|
|
toplevel_node = toplevel_node->child;
|
|
|
|
while (toplevel_node != NULL) {
|
|
struct linux_prom_pci_registers *regs;
|
|
struct property *prop;
|
|
int ret;
|
|
|
|
ret = obp_find(toplevel_node, bus, devfn);
|
|
if (ret != 0)
|
|
return ret;
|
|
|
|
prop = of_find_property(toplevel_node, "reg", NULL);
|
|
if (!prop)
|
|
goto next_sibling;
|
|
|
|
regs = prop->value;
|
|
if (((regs->phys_hi >> 16) & 0xff) == bus &&
|
|
((regs->phys_hi >> 8) & 0xff) == devfn)
|
|
break;
|
|
|
|
next_sibling:
|
|
toplevel_node = toplevel_node->sibling;
|
|
}
|
|
|
|
return toplevel_node != NULL;
|
|
}
|
|
|
|
static int pdev_htab_populate(struct pci_pbm_info *pbm)
|
|
{
|
|
u32 devhandle = pbm->devhandle;
|
|
unsigned int bus;
|
|
|
|
for (bus = pbm->pci_first_busno; bus <= pbm->pci_last_busno; bus++) {
|
|
unsigned int devfn;
|
|
|
|
for (devfn = 0; devfn < 256; devfn++) {
|
|
unsigned int device = PCI_SLOT(devfn);
|
|
unsigned int func = PCI_FUNC(devfn);
|
|
|
|
if (obp_find(pbm->prom_node, bus, devfn)) {
|
|
int err = pdev_htab_add(devhandle, bus,
|
|
device, func);
|
|
if (err)
|
|
return err;
|
|
}
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct pdev_entry *pdev_find(u32 devhandle, unsigned int bus, unsigned int device, unsigned int func)
|
|
{
|
|
struct pdev_entry *p;
|
|
|
|
p = pdev_htab[pdev_hashfn(devhandle, bus, device, func)];
|
|
while (p) {
|
|
if (p->devhandle == devhandle &&
|
|
p->bus == bus &&
|
|
p->device == device &&
|
|
p->func == func)
|
|
break;
|
|
|
|
p = p->next;
|
|
}
|
|
|
|
return p;
|
|
}
|
|
|
|
static inline int pci_sun4v_out_of_range(struct pci_pbm_info *pbm, unsigned int bus, unsigned int device, unsigned int func)
|
|
{
|
|
if (bus < pbm->pci_first_busno ||
|
|
bus > pbm->pci_last_busno)
|
|
return 1;
|
|
return pdev_find(pbm->devhandle, bus, device, func) == NULL;
|
|
}
|
|
|
|
static int pci_sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
|
|
int where, int size, u32 *value)
|
|
{
|
|
struct pci_pbm_info *pbm = bus_dev->sysdata;
|
|
u32 devhandle = pbm->devhandle;
|
|
unsigned int bus = bus_dev->number;
|
|
unsigned int device = PCI_SLOT(devfn);
|
|
unsigned int func = PCI_FUNC(devfn);
|
|
unsigned long ret;
|
|
|
|
if (pci_sun4v_out_of_range(pbm, bus, device, func)) {
|
|
ret = ~0UL;
|
|
} else {
|
|
ret = pci_sun4v_config_get(devhandle,
|
|
HV_PCI_DEVICE_BUILD(bus, device, func),
|
|
where, size);
|
|
#if 0
|
|
printk("rcfg: [%x:%x:%x:%d]=[%lx]\n",
|
|
devhandle, HV_PCI_DEVICE_BUILD(bus, device, func),
|
|
where, size, ret);
|
|
#endif
|
|
}
|
|
switch (size) {
|
|
case 1:
|
|
*value = ret & 0xff;
|
|
break;
|
|
case 2:
|
|
*value = ret & 0xffff;
|
|
break;
|
|
case 4:
|
|
*value = ret & 0xffffffff;
|
|
break;
|
|
};
|
|
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
}
|
|
|
|
static int pci_sun4v_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
|
|
int where, int size, u32 value)
|
|
{
|
|
struct pci_pbm_info *pbm = bus_dev->sysdata;
|
|
u32 devhandle = pbm->devhandle;
|
|
unsigned int bus = bus_dev->number;
|
|
unsigned int device = PCI_SLOT(devfn);
|
|
unsigned int func = PCI_FUNC(devfn);
|
|
unsigned long ret;
|
|
|
|
if (pci_sun4v_out_of_range(pbm, bus, device, func)) {
|
|
/* Do nothing. */
|
|
} else {
|
|
ret = pci_sun4v_config_put(devhandle,
|
|
HV_PCI_DEVICE_BUILD(bus, device, func),
|
|
where, size, value);
|
|
#if 0
|
|
printk("wcfg: [%x:%x:%x:%d] v[%x] == [%lx]\n",
|
|
devhandle, HV_PCI_DEVICE_BUILD(bus, device, func),
|
|
where, size, value, ret);
|
|
#endif
|
|
}
|
|
return PCIBIOS_SUCCESSFUL;
|
|
}
|
|
|
|
static struct pci_ops pci_sun4v_ops = {
|
|
.read = pci_sun4v_read_pci_cfg,
|
|
.write = pci_sun4v_write_pci_cfg,
|
|
};
|
|
|
|
|
|
static void pbm_scan_bus(struct pci_controller_info *p,
|
|
struct pci_pbm_info *pbm)
|
|
{
|
|
struct pcidev_cookie *cookie = kmalloc(sizeof(*cookie), GFP_KERNEL);
|
|
|
|
if (!cookie) {
|
|
prom_printf("%s: Critical allocation failure.\n", pbm->name);
|
|
prom_halt();
|
|
}
|
|
|
|
/* All we care about is the PBM. */
|
|
memset(cookie, 0, sizeof(*cookie));
|
|
cookie->pbm = pbm;
|
|
|
|
pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno, p->pci_ops, pbm);
|
|
#if 0
|
|
pci_fixup_host_bridge_self(pbm->pci_bus);
|
|
pbm->pci_bus->self->sysdata = cookie;
|
|
#endif
|
|
pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
|
|
pci_record_assignments(pbm, pbm->pci_bus);
|
|
pci_assign_unassigned(pbm, pbm->pci_bus);
|
|
pci_fixup_irq(pbm, pbm->pci_bus);
|
|
pci_determine_66mhz_disposition(pbm, pbm->pci_bus);
|
|
pci_setup_busmastering(pbm, pbm->pci_bus);
|
|
}
|
|
|
|
static void pci_sun4v_scan_bus(struct pci_controller_info *p)
|
|
{
|
|
struct property *prop;
|
|
struct device_node *dp;
|
|
|
|
if ((dp = p->pbm_A.prom_node) != NULL) {
|
|
prop = of_find_property(dp, "66mhz-capable", NULL);
|
|
p->pbm_A.is_66mhz_capable = (prop != NULL);
|
|
|
|
pbm_scan_bus(p, &p->pbm_A);
|
|
}
|
|
if ((dp = p->pbm_B.prom_node) != NULL) {
|
|
prop = of_find_property(dp, "66mhz-capable", NULL);
|
|
p->pbm_B.is_66mhz_capable = (prop != NULL);
|
|
|
|
pbm_scan_bus(p, &p->pbm_B);
|
|
}
|
|
|
|
/* XXX register error interrupt handlers XXX */
|
|
}
|
|
|
|
static void pci_sun4v_base_address_update(struct pci_dev *pdev, int resource)
|
|
{
|
|
struct pcidev_cookie *pcp = pdev->sysdata;
|
|
struct pci_pbm_info *pbm = pcp->pbm;
|
|
struct resource *res, *root;
|
|
u32 reg;
|
|
int where, size, is_64bit;
|
|
|
|
res = &pdev->resource[resource];
|
|
if (resource < 6) {
|
|
where = PCI_BASE_ADDRESS_0 + (resource * 4);
|
|
} else if (resource == PCI_ROM_RESOURCE) {
|
|
where = pdev->rom_base_reg;
|
|
} else {
|
|
/* Somebody might have asked allocation of a non-standard resource */
|
|
return;
|
|
}
|
|
|
|
/* XXX 64-bit MEM handling is not %100 correct... XXX */
|
|
is_64bit = 0;
|
|
if (res->flags & IORESOURCE_IO)
|
|
root = &pbm->io_space;
|
|
else {
|
|
root = &pbm->mem_space;
|
|
if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
|
|
== PCI_BASE_ADDRESS_MEM_TYPE_64)
|
|
is_64bit = 1;
|
|
}
|
|
|
|
size = res->end - res->start;
|
|
pci_read_config_dword(pdev, where, ®);
|
|
reg = ((reg & size) |
|
|
(((u32)(res->start - root->start)) & ~size));
|
|
if (resource == PCI_ROM_RESOURCE) {
|
|
reg |= PCI_ROM_ADDRESS_ENABLE;
|
|
res->flags |= IORESOURCE_ROM_ENABLE;
|
|
}
|
|
pci_write_config_dword(pdev, where, reg);
|
|
|
|
/* This knows that the upper 32-bits of the address
|
|
* must be zero. Our PCI common layer enforces this.
|
|
*/
|
|
if (is_64bit)
|
|
pci_write_config_dword(pdev, where + 4, 0);
|
|
}
|
|
|
|
static void pci_sun4v_resource_adjust(struct pci_dev *pdev,
|
|
struct resource *res,
|
|
struct resource *root)
|
|
{
|
|
res->start += root->start;
|
|
res->end += root->start;
|
|
}
|
|
|
|
/* Use ranges property to determine where PCI MEM, I/O, and Config
|
|
* space are for this PCI bus module.
|
|
*/
|
|
static void pci_sun4v_determine_mem_io_space(struct pci_pbm_info *pbm)
|
|
{
|
|
int i, saw_mem, saw_io;
|
|
|
|
saw_mem = saw_io = 0;
|
|
for (i = 0; i < pbm->num_pbm_ranges; i++) {
|
|
struct linux_prom_pci_ranges *pr = &pbm->pbm_ranges[i];
|
|
unsigned long a;
|
|
int type;
|
|
|
|
type = (pr->child_phys_hi >> 24) & 0x3;
|
|
a = (((unsigned long)pr->parent_phys_hi << 32UL) |
|
|
((unsigned long)pr->parent_phys_lo << 0UL));
|
|
|
|
switch (type) {
|
|
case 1:
|
|
/* 16-bit IO space, 16MB */
|
|
pbm->io_space.start = a;
|
|
pbm->io_space.end = a + ((16UL*1024UL*1024UL) - 1UL);
|
|
pbm->io_space.flags = IORESOURCE_IO;
|
|
saw_io = 1;
|
|
break;
|
|
|
|
case 2:
|
|
/* 32-bit MEM space, 2GB */
|
|
pbm->mem_space.start = a;
|
|
pbm->mem_space.end = a + (0x80000000UL - 1UL);
|
|
pbm->mem_space.flags = IORESOURCE_MEM;
|
|
saw_mem = 1;
|
|
break;
|
|
|
|
case 3:
|
|
/* XXX 64-bit MEM handling XXX */
|
|
|
|
default:
|
|
break;
|
|
};
|
|
}
|
|
|
|
if (!saw_io || !saw_mem) {
|
|
prom_printf("%s: Fatal error, missing %s PBM range.\n",
|
|
pbm->name,
|
|
(!saw_io ? "IO" : "MEM"));
|
|
prom_halt();
|
|
}
|
|
|
|
printk("%s: PCI IO[%lx] MEM[%lx]\n",
|
|
pbm->name,
|
|
pbm->io_space.start,
|
|
pbm->mem_space.start);
|
|
}
|
|
|
|
static void pbm_register_toplevel_resources(struct pci_controller_info *p,
|
|
struct pci_pbm_info *pbm)
|
|
{
|
|
pbm->io_space.name = pbm->mem_space.name = pbm->name;
|
|
|
|
request_resource(&ioport_resource, &pbm->io_space);
|
|
request_resource(&iomem_resource, &pbm->mem_space);
|
|
pci_register_legacy_regions(&pbm->io_space,
|
|
&pbm->mem_space);
|
|
}
|
|
|
|
static unsigned long probe_existing_entries(struct pci_pbm_info *pbm,
|
|
struct pci_iommu *iommu)
|
|
{
|
|
struct pci_iommu_arena *arena = &iommu->arena;
|
|
unsigned long i, cnt = 0;
|
|
u32 devhandle;
|
|
|
|
devhandle = pbm->devhandle;
|
|
for (i = 0; i < arena->limit; i++) {
|
|
unsigned long ret, io_attrs, ra;
|
|
|
|
ret = pci_sun4v_iommu_getmap(devhandle,
|
|
HV_PCI_TSBID(0, i),
|
|
&io_attrs, &ra);
|
|
if (ret == HV_EOK) {
|
|
if (page_in_phys_avail(ra)) {
|
|
pci_sun4v_iommu_demap(devhandle,
|
|
HV_PCI_TSBID(0, i), 1);
|
|
} else {
|
|
cnt++;
|
|
__set_bit(i, arena->map);
|
|
}
|
|
}
|
|
}
|
|
|
|
return cnt;
|
|
}
|
|
|
|
static void pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
|
|
{
|
|
struct pci_iommu *iommu = pbm->iommu;
|
|
struct property *prop;
|
|
unsigned long num_tsb_entries, sz;
|
|
u32 vdma[2], dma_mask, dma_offset;
|
|
int tsbsize;
|
|
|
|
prop = of_find_property(pbm->prom_node, "virtual-dma", NULL);
|
|
if (prop) {
|
|
u32 *val = prop->value;
|
|
|
|
vdma[0] = val[0];
|
|
vdma[1] = val[1];
|
|
} else {
|
|
/* No property, use default values. */
|
|
vdma[0] = 0x80000000;
|
|
vdma[1] = 0x80000000;
|
|
}
|
|
|
|
dma_mask = vdma[0];
|
|
switch (vdma[1]) {
|
|
case 0x20000000:
|
|
dma_mask |= 0x1fffffff;
|
|
tsbsize = 64;
|
|
break;
|
|
|
|
case 0x40000000:
|
|
dma_mask |= 0x3fffffff;
|
|
tsbsize = 128;
|
|
break;
|
|
|
|
case 0x80000000:
|
|
dma_mask |= 0x7fffffff;
|
|
tsbsize = 256;
|
|
break;
|
|
|
|
default:
|
|
prom_printf("PCI-SUN4V: strange virtual-dma size.\n");
|
|
prom_halt();
|
|
};
|
|
|
|
tsbsize *= (8 * 1024);
|
|
|
|
num_tsb_entries = tsbsize / sizeof(iopte_t);
|
|
|
|
dma_offset = vdma[0];
|
|
|
|
/* Setup initial software IOMMU state. */
|
|
spin_lock_init(&iommu->lock);
|
|
iommu->ctx_lowest_free = 1;
|
|
iommu->page_table_map_base = dma_offset;
|
|
iommu->dma_addr_mask = dma_mask;
|
|
|
|
/* Allocate and initialize the free area map. */
|
|
sz = num_tsb_entries / 8;
|
|
sz = (sz + 7UL) & ~7UL;
|
|
iommu->arena.map = kmalloc(sz, GFP_KERNEL);
|
|
if (!iommu->arena.map) {
|
|
prom_printf("PCI_IOMMU: Error, kmalloc(arena.map) failed.\n");
|
|
prom_halt();
|
|
}
|
|
memset(iommu->arena.map, 0, sz);
|
|
iommu->arena.limit = num_tsb_entries;
|
|
|
|
sz = probe_existing_entries(pbm, iommu);
|
|
if (sz)
|
|
printk("%s: Imported %lu TSB entries from OBP\n",
|
|
pbm->name, sz);
|
|
}
|
|
|
|
static void pci_sun4v_get_bus_range(struct pci_pbm_info *pbm)
|
|
{
|
|
struct property *prop;
|
|
unsigned int *busrange;
|
|
|
|
prop = of_find_property(pbm->prom_node, "bus-range", NULL);
|
|
|
|
busrange = prop->value;
|
|
|
|
pbm->pci_first_busno = busrange[0];
|
|
pbm->pci_last_busno = busrange[1];
|
|
|
|
}
|
|
|
|
static void pci_sun4v_pbm_init(struct pci_controller_info *p, struct device_node *dp, u32 devhandle)
|
|
{
|
|
struct pci_pbm_info *pbm;
|
|
struct property *prop;
|
|
int len, i;
|
|
|
|
if (devhandle & 0x40)
|
|
pbm = &p->pbm_B;
|
|
else
|
|
pbm = &p->pbm_A;
|
|
|
|
pbm->parent = p;
|
|
pbm->prom_node = dp;
|
|
pbm->pci_first_slot = 1;
|
|
|
|
pbm->devhandle = devhandle;
|
|
|
|
pbm->name = dp->full_name;
|
|
|
|
printk("%s: SUN4V PCI Bus Module\n", pbm->name);
|
|
|
|
prop = of_find_property(dp, "ranges", &len);
|
|
pbm->pbm_ranges = prop->value;
|
|
pbm->num_pbm_ranges =
|
|
(len / sizeof(struct linux_prom_pci_ranges));
|
|
|
|
/* Mask out the top 8 bits of the ranges, leaving the real
|
|
* physical address.
|
|
*/
|
|
for (i = 0; i < pbm->num_pbm_ranges; i++)
|
|
pbm->pbm_ranges[i].parent_phys_hi &= 0x0fffffff;
|
|
|
|
pci_sun4v_determine_mem_io_space(pbm);
|
|
pbm_register_toplevel_resources(p, pbm);
|
|
|
|
prop = of_find_property(dp, "interrupt-map", &len);
|
|
pbm->pbm_intmap = prop->value;
|
|
pbm->num_pbm_intmap =
|
|
(len / sizeof(struct linux_prom_pci_intmap));
|
|
|
|
prop = of_find_property(dp, "interrupt-map-mask", NULL);
|
|
pbm->pbm_intmask = prop->value;
|
|
|
|
pci_sun4v_get_bus_range(pbm);
|
|
pci_sun4v_iommu_init(pbm);
|
|
|
|
pdev_htab_populate(pbm);
|
|
}
|
|
|
|
void sun4v_pci_init(struct device_node *dp, char *model_name)
|
|
{
|
|
struct pci_controller_info *p;
|
|
struct pci_iommu *iommu;
|
|
struct property *prop;
|
|
struct linux_prom64_registers *regs;
|
|
u32 devhandle;
|
|
int i;
|
|
|
|
prop = of_find_property(dp, "reg", NULL);
|
|
regs = prop->value;
|
|
|
|
devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff;
|
|
|
|
for (p = pci_controller_root; p; p = p->next) {
|
|
struct pci_pbm_info *pbm;
|
|
|
|
if (p->pbm_A.prom_node && p->pbm_B.prom_node)
|
|
continue;
|
|
|
|
pbm = (p->pbm_A.prom_node ?
|
|
&p->pbm_A :
|
|
&p->pbm_B);
|
|
|
|
if (pbm->devhandle == (devhandle ^ 0x40)) {
|
|
pci_sun4v_pbm_init(p, dp, devhandle);
|
|
return;
|
|
}
|
|
}
|
|
|
|
for_each_possible_cpu(i) {
|
|
unsigned long page = get_zeroed_page(GFP_ATOMIC);
|
|
|
|
if (!page)
|
|
goto fatal_memory_error;
|
|
|
|
per_cpu(pci_iommu_batch, i).pglist = (u64 *) page;
|
|
}
|
|
|
|
p = kmalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
|
|
if (!p)
|
|
goto fatal_memory_error;
|
|
|
|
memset(p, 0, sizeof(*p));
|
|
|
|
iommu = kmalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
|
|
if (!iommu)
|
|
goto fatal_memory_error;
|
|
|
|
memset(iommu, 0, sizeof(*iommu));
|
|
p->pbm_A.iommu = iommu;
|
|
|
|
iommu = kmalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
|
|
if (!iommu)
|
|
goto fatal_memory_error;
|
|
|
|
memset(iommu, 0, sizeof(*iommu));
|
|
p->pbm_B.iommu = iommu;
|
|
|
|
p->next = pci_controller_root;
|
|
pci_controller_root = p;
|
|
|
|
p->index = pci_num_controllers++;
|
|
p->pbms_same_domain = 0;
|
|
|
|
p->scan_bus = pci_sun4v_scan_bus;
|
|
p->base_address_update = pci_sun4v_base_address_update;
|
|
p->resource_adjust = pci_sun4v_resource_adjust;
|
|
p->pci_ops = &pci_sun4v_ops;
|
|
|
|
/* Like PSYCHO and SCHIZO we have a 2GB aligned area
|
|
* for memory space.
|
|
*/
|
|
pci_memspace_mask = 0x7fffffffUL;
|
|
|
|
pci_sun4v_pbm_init(p, dp, devhandle);
|
|
return;
|
|
|
|
fatal_memory_error:
|
|
prom_printf("SUN4V_PCI: Fatal memory allocation error.\n");
|
|
prom_halt();
|
|
}
|