711 строки
20 KiB
ArmAsm
711 строки
20 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
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* Initial PowerPC version.
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* Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
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* Rewritten for PReP
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* Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
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* Low-level exception handers, MMU support, and rewrite.
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* Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
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* PowerPC 8xx modifications.
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* Copyright (c) 1998-1999 TiVo, Inc.
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* PowerPC 403GCX modifications.
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* Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
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* PowerPC 403GCX/405GP modifications.
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* Copyright 2000 MontaVista Software Inc.
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* PPC405 modifications
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* PowerPC 403GCX/405GP modifications.
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* Author: MontaVista Software, Inc.
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* frank_rowand@mvista.com or source@mvista.com
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* debbie_chu@mvista.com
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*
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* Module name: head_4xx.S
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*
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* Description:
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* Kernel execution entry point code.
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*/
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#include <linux/init.h>
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#include <linux/pgtable.h>
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#include <linux/sizes.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/cputable.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/ptrace.h>
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#include <asm/export.h>
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#include "head_32.h"
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/* As with the other PowerPC ports, it is expected that when code
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* execution begins here, the following registers contain valid, yet
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* optional, information:
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*
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* r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
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* r4 - Starting address of the init RAM disk
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* r5 - Ending address of the init RAM disk
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* r6 - Start of kernel command line string (e.g. "mem=96m")
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* r7 - End of kernel command line string
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*
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* This is all going to change RSN when we add bi_recs....... -- Dan
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*/
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__HEAD
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_ENTRY(_stext);
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_ENTRY(_start);
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mr r31,r3 /* save device tree ptr */
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/* We have to turn on the MMU right away so we get cache modes
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* set correctly.
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*/
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bl initial_mmu
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/* We now have the lower 16 Meg mapped into TLB entries, and the caches
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* ready to work.
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*/
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turn_on_mmu:
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lis r0,MSR_KERNEL@h
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ori r0,r0,MSR_KERNEL@l
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mtspr SPRN_SRR1,r0
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lis r0,start_here@h
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ori r0,r0,start_here@l
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mtspr SPRN_SRR0,r0
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rfi /* enables MMU */
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b . /* prevent prefetch past rfi */
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/*
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* This area is used for temporarily saving registers during the
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* critical exception prolog.
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*/
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. = 0xc0
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crit_save:
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_ENTRY(crit_r10)
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.space 4
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_ENTRY(crit_r11)
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.space 4
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_ENTRY(crit_srr0)
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.space 4
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_ENTRY(crit_srr1)
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.space 4
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_ENTRY(crit_r1)
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.space 4
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_ENTRY(crit_dear)
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.space 4
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_ENTRY(crit_esr)
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.space 4
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/*
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* Exception prolog for critical exceptions. This is a little different
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* from the normal exception prolog above since a critical exception
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* can potentially occur at any point during normal exception processing.
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* Thus we cannot use the same SPRG registers as the normal prolog above.
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* Instead we use a couple of words of memory at low physical addresses.
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* This is OK since we don't support SMP on these processors.
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*/
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.macro CRITICAL_EXCEPTION_PROLOG trapno name
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stw r10,crit_r10@l(0) /* save two registers to work with */
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stw r11,crit_r11@l(0)
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mfspr r10,SPRN_SRR0
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mfspr r11,SPRN_SRR1
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stw r10,crit_srr0@l(0)
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stw r11,crit_srr1@l(0)
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mfspr r10,SPRN_DEAR
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mfspr r11,SPRN_ESR
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stw r10,crit_dear@l(0)
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stw r11,crit_esr@l(0)
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mfcr r10 /* save CR in r10 for now */
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mfspr r11,SPRN_SRR3 /* check whether user or kernel */
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andi. r11,r11,MSR_PR
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lis r11,(critirq_ctx-PAGE_OFFSET)@ha
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lwz r11,(critirq_ctx-PAGE_OFFSET)@l(r11)
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beq 1f
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/* COMING FROM USER MODE */
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mfspr r11,SPRN_SPRG_THREAD /* if from user, start at top of */
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lwz r11,TASK_STACK-THREAD(r11) /* this thread's kernel stack */
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1: stw r1,crit_r1@l(0)
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addi r1,r11,THREAD_SIZE-INT_FRAME_SIZE /* Alloc an excpt frm */
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LOAD_REG_IMMEDIATE(r11, MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)) /* re-enable MMU */
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mtspr SPRN_SRR1, r11
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lis r11, 1f@h
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ori r11, r11, 1f@l
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mtspr SPRN_SRR0, r11
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rfi
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.text
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1:
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\name\()_virt:
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lwz r11,crit_r1@l(0)
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stw r11,GPR1(r1)
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stw r11,0(r1)
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mr r11,r1
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stw r10,_CCR(r11) /* save various registers */
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stw r12,GPR12(r11)
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stw r9,GPR9(r11)
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mflr r10
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stw r10,_LINK(r11)
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lis r9,PAGE_OFFSET@ha
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lwz r10,crit_r10@l(r9)
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lwz r12,crit_r11@l(r9)
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stw r10,GPR10(r11)
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stw r12,GPR11(r11)
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lwz r12,crit_dear@l(r9)
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lwz r9,crit_esr@l(r9)
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stw r12,_DEAR(r11) /* since they may have had stuff */
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stw r9,_ESR(r11) /* exception was taken */
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mfspr r12,SPRN_SRR2
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mfspr r9,SPRN_SRR3
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rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */
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COMMON_EXCEPTION_PROLOG_END \trapno + 2
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_ASM_NOKPROBE_SYMBOL(\name\()_virt)
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.endm
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/*
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* State at this point:
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* r9 saved in stack frame, now saved SRR3 & ~MSR_WE
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* r10 saved in crit_r10 and in stack frame, trashed
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* r11 saved in crit_r11 and in stack frame,
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* now phys stack/exception frame pointer
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* r12 saved in stack frame, now saved SRR2
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* CR saved in stack frame, CR0.EQ = !SRR3.PR
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* LR, DEAR, ESR in stack frame
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* r1 saved in stack frame, now virt stack/excframe pointer
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* r0, r3-r8 saved in stack frame
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*/
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/*
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* Exception vectors.
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*/
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#define CRITICAL_EXCEPTION(n, label, hdlr) \
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START_EXCEPTION(n, label); \
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CRITICAL_EXCEPTION_PROLOG n label; \
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prepare_transfer_to_handler; \
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bl hdlr; \
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b ret_from_crit_exc
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/*
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* 0x0100 - Critical Interrupt Exception
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*/
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CRITICAL_EXCEPTION(0x0100, CriticalInterrupt, unknown_exception)
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/*
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* 0x0200 - Machine Check Exception
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*/
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CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
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/*
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* 0x0300 - Data Storage Exception
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* This happens for just a few reasons. U0 set (but we don't do that),
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* or zone protection fault (user violation, write to protected page).
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* The other Data TLB exceptions bail out to this point
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* if they can't resolve the lightweight TLB fault.
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*/
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START_EXCEPTION(0x0300, DataStorage)
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EXCEPTION_PROLOG 0x300 DataStorage handle_dar_dsisr=1
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prepare_transfer_to_handler
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bl do_page_fault
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b interrupt_return
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/*
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* 0x0400 - Instruction Storage Exception
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* This is caused by a fetch from non-execute or guarded pages.
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*/
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START_EXCEPTION(0x0400, InstructionAccess)
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EXCEPTION_PROLOG 0x400 InstructionAccess
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li r5,0
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stw r5, _ESR(r11) /* Zero ESR */
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stw r12, _DEAR(r11) /* SRR0 as DEAR */
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prepare_transfer_to_handler
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bl do_page_fault
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b interrupt_return
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/* 0x0500 - External Interrupt Exception */
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EXCEPTION(0x0500, HardwareInterrupt, do_IRQ)
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/* 0x0600 - Alignment Exception */
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START_EXCEPTION(0x0600, Alignment)
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EXCEPTION_PROLOG 0x600 Alignment handle_dar_dsisr=1
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prepare_transfer_to_handler
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bl alignment_exception
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REST_NVGPRS(r1)
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b interrupt_return
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/* 0x0700 - Program Exception */
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START_EXCEPTION(0x0700, ProgramCheck)
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EXCEPTION_PROLOG 0x700 ProgramCheck handle_dar_dsisr=1
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prepare_transfer_to_handler
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bl program_check_exception
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REST_NVGPRS(r1)
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b interrupt_return
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EXCEPTION(0x0800, Trap_08, unknown_exception)
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EXCEPTION(0x0900, Trap_09, unknown_exception)
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EXCEPTION(0x0A00, Trap_0A, unknown_exception)
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EXCEPTION(0x0B00, Trap_0B, unknown_exception)
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/* 0x0C00 - System Call Exception */
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START_EXCEPTION(0x0C00, SystemCall)
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SYSCALL_ENTRY 0xc00
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/* Trap_0D is commented out to get more space for system call exception */
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/* EXCEPTION(0x0D00, Trap_0D, unknown_exception) */
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EXCEPTION(0x0E00, Trap_0E, unknown_exception)
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EXCEPTION(0x0F00, Trap_0F, unknown_exception)
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/* 0x1000 - Programmable Interval Timer (PIT) Exception */
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START_EXCEPTION(0x1000, DecrementerTrap)
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b Decrementer
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/* 0x1010 - Fixed Interval Timer (FIT) Exception */
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START_EXCEPTION(0x1010, FITExceptionTrap)
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b FITException
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/* 0x1020 - Watchdog Timer (WDT) Exception */
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START_EXCEPTION(0x1020, WDTExceptionTrap)
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b WDTException
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/* 0x1100 - Data TLB Miss Exception
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* As the name implies, translation is not in the MMU, so search the
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* page tables and fix it. The only purpose of this function is to
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* load TLB entries from the page table if they exist.
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*/
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START_EXCEPTION(0x1100, DTLBMiss)
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mtspr SPRN_SPRG_SCRATCH5, r10 /* Save some working registers */
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mtspr SPRN_SPRG_SCRATCH6, r11
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mtspr SPRN_SPRG_SCRATCH3, r12
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mtspr SPRN_SPRG_SCRATCH4, r9
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mfcr r12
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mfspr r9, SPRN_PID
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rlwimi r12, r9, 0, 0xff
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mfspr r10, SPRN_DEAR /* Get faulting address */
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/* If we are faulting a kernel address, we have to use the
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* kernel page tables.
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*/
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lis r11, PAGE_OFFSET@h
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cmplw r10, r11
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blt+ 3f
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lis r11, swapper_pg_dir@h
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ori r11, r11, swapper_pg_dir@l
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li r9, 0
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mtspr SPRN_PID, r9 /* TLB will have 0 TID */
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b 4f
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/* Get the PGD for the current thread.
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*/
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3:
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mfspr r11,SPRN_SPRG_THREAD
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lwz r11,PGDIR(r11)
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4:
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tophys(r11, r11)
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rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
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lwz r11, 0(r11) /* Get L1 entry */
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andi. r9, r11, _PMD_PRESENT /* Check if it points to a PTE page */
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beq 2f /* Bail if no table */
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rlwimi r11, r10, 22, 20, 29 /* Compute PTE address */
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lwz r11, 0(r11) /* Get Linux PTE */
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li r9, _PAGE_PRESENT | _PAGE_ACCESSED
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andc. r9, r9, r11 /* Check permission */
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bne 5f
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rlwinm r9, r11, 1, _PAGE_RW /* dirty => rw */
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and r9, r9, r11 /* hwwrite = dirty & rw */
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rlwimi r11, r9, 0, _PAGE_RW /* replace rw by hwwrite */
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/* Create TLB tag. This is the faulting address plus a static
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* set of bits. These are size, valid, E, U0.
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*/
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li r9, 0x00c0
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rlwimi r10, r9, 0, 20, 31
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b finish_tlb_load
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2: /* Check for possible large-page pmd entry */
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rlwinm. r9, r11, 2, 22, 24
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beq 5f
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/* Create TLB tag. This is the faulting address, plus a static
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* set of bits (valid, E, U0) plus the size from the PMD.
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*/
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ori r9, r9, 0x40
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rlwimi r10, r9, 0, 20, 31
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b finish_tlb_load
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5:
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/* The bailout. Restore registers to pre-exception conditions
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* and call the heavyweights to help us out.
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*/
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mtspr SPRN_PID, r12
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mtcrf 0x80, r12
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mfspr r9, SPRN_SPRG_SCRATCH4
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mfspr r12, SPRN_SPRG_SCRATCH3
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mfspr r11, SPRN_SPRG_SCRATCH6
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mfspr r10, SPRN_SPRG_SCRATCH5
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b DataStorage
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/* 0x1200 - Instruction TLB Miss Exception
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* Nearly the same as above, except we get our information from different
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* registers and bailout to a different point.
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*/
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START_EXCEPTION(0x1200, ITLBMiss)
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mtspr SPRN_SPRG_SCRATCH5, r10 /* Save some working registers */
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mtspr SPRN_SPRG_SCRATCH6, r11
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mtspr SPRN_SPRG_SCRATCH3, r12
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mtspr SPRN_SPRG_SCRATCH4, r9
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mfcr r12
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mfspr r9, SPRN_PID
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rlwimi r12, r9, 0, 0xff
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mfspr r10, SPRN_SRR0 /* Get faulting address */
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/* If we are faulting a kernel address, we have to use the
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* kernel page tables.
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*/
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lis r11, PAGE_OFFSET@h
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cmplw r10, r11
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blt+ 3f
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lis r11, swapper_pg_dir@h
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ori r11, r11, swapper_pg_dir@l
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li r9, 0
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mtspr SPRN_PID, r9 /* TLB will have 0 TID */
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b 4f
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/* Get the PGD for the current thread.
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*/
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3:
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mfspr r11,SPRN_SPRG_THREAD
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lwz r11,PGDIR(r11)
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4:
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tophys(r11, r11)
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rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
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lwz r11, 0(r11) /* Get L1 entry */
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andi. r9, r11, _PMD_PRESENT /* Check if it points to a PTE page */
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beq 2f /* Bail if no table */
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rlwimi r11, r10, 22, 20, 29 /* Compute PTE address */
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lwz r11, 0(r11) /* Get Linux PTE */
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li r9, _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
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andc. r9, r9, r11 /* Check permission */
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bne 5f
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rlwinm r9, r11, 1, _PAGE_RW /* dirty => rw */
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and r9, r9, r11 /* hwwrite = dirty & rw */
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rlwimi r11, r9, 0, _PAGE_RW /* replace rw by hwwrite */
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/* Create TLB tag. This is the faulting address plus a static
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* set of bits. These are size, valid, E, U0.
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*/
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li r9, 0x00c0
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rlwimi r10, r9, 0, 20, 31
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b finish_tlb_load
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2: /* Check for possible large-page pmd entry */
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rlwinm. r9, r11, 2, 22, 24
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beq 5f
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/* Create TLB tag. This is the faulting address, plus a static
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* set of bits (valid, E, U0) plus the size from the PMD.
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*/
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ori r9, r9, 0x40
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rlwimi r10, r9, 0, 20, 31
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b finish_tlb_load
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5:
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/* The bailout. Restore registers to pre-exception conditions
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* and call the heavyweights to help us out.
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*/
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mtspr SPRN_PID, r12
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mtcrf 0x80, r12
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mfspr r9, SPRN_SPRG_SCRATCH4
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mfspr r12, SPRN_SPRG_SCRATCH3
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mfspr r11, SPRN_SPRG_SCRATCH6
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mfspr r10, SPRN_SPRG_SCRATCH5
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b InstructionAccess
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EXCEPTION(0x1300, Trap_13, unknown_exception)
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EXCEPTION(0x1400, Trap_14, unknown_exception)
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EXCEPTION(0x1500, Trap_15, unknown_exception)
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EXCEPTION(0x1600, Trap_16, unknown_exception)
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EXCEPTION(0x1700, Trap_17, unknown_exception)
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EXCEPTION(0x1800, Trap_18, unknown_exception)
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EXCEPTION(0x1900, Trap_19, unknown_exception)
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EXCEPTION(0x1A00, Trap_1A, unknown_exception)
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EXCEPTION(0x1B00, Trap_1B, unknown_exception)
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EXCEPTION(0x1C00, Trap_1C, unknown_exception)
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EXCEPTION(0x1D00, Trap_1D, unknown_exception)
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EXCEPTION(0x1E00, Trap_1E, unknown_exception)
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EXCEPTION(0x1F00, Trap_1F, unknown_exception)
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/* Check for a single step debug exception while in an exception
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* handler before state has been saved. This is to catch the case
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* where an instruction that we are trying to single step causes
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* an exception (eg ITLB/DTLB miss) and thus the first instruction of
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* the exception handler generates a single step debug exception.
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*
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* If we get a debug trap on the first instruction of an exception handler,
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* we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
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* a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
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* The exception handler was handling a non-critical interrupt, so it will
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* save (and later restore) the MSR via SPRN_SRR1, which will still have
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* the MSR_DE bit set.
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*/
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/* 0x2000 - Debug Exception */
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START_EXCEPTION(0x2000, DebugTrap)
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CRITICAL_EXCEPTION_PROLOG 0x2000 DebugTrap
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/*
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* If this is a single step or branch-taken exception in an
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* exception entry sequence, it was probably meant to apply to
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* the code where the exception occurred (since exception entry
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* doesn't turn off DE automatically). We simulate the effect
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* of turning off DE on entry to an exception handler by turning
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* off DE in the SRR3 value and clearing the debug status.
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*/
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mfspr r10,SPRN_DBSR /* check single-step/branch taken */
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andis. r10,r10,DBSR_IC@h
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beq+ 2f
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andi. r10,r9,MSR_IR|MSR_PR /* check supervisor + MMU off */
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beq 1f /* branch and fix it up */
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mfspr r10,SPRN_SRR2 /* Faulting instruction address */
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cmplwi r10,0x2100
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bgt+ 2f /* address above exception vectors */
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/* here it looks like we got an inappropriate debug exception. */
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1: rlwinm r9,r9,0,~MSR_DE /* clear DE in the SRR3 value */
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lis r10,DBSR_IC@h /* clear the IC event */
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mtspr SPRN_DBSR,r10
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/* restore state and get out */
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lwz r10,_CCR(r11)
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lwz r0,GPR0(r11)
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lwz r1,GPR1(r11)
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mtcrf 0x80,r10
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mtspr SPRN_SRR2,r12
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mtspr SPRN_SRR3,r9
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lwz r9,GPR9(r11)
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lwz r12,GPR12(r11)
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lwz r10,crit_r10@l(0)
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lwz r11,crit_r11@l(0)
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rfci
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b .
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/* continue normal handling for a critical exception... */
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2: mfspr r4,SPRN_DBSR
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stw r4,_ESR(r11) /* DebugException takes DBSR in _ESR */
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prepare_transfer_to_handler
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bl DebugException
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b ret_from_crit_exc
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/* Programmable Interval Timer (PIT) Exception. (from 0x1000) */
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__HEAD
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Decrementer:
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EXCEPTION_PROLOG 0x1000 Decrementer
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lis r0,TSR_PIS@h
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mtspr SPRN_TSR,r0 /* Clear the PIT exception */
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prepare_transfer_to_handler
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bl timer_interrupt
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b interrupt_return
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/* Fixed Interval Timer (FIT) Exception. (from 0x1010) */
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__HEAD
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FITException:
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EXCEPTION_PROLOG 0x1010 FITException
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prepare_transfer_to_handler
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bl unknown_exception
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b interrupt_return
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/* Watchdog Timer (WDT) Exception. (from 0x1020) */
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__HEAD
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WDTException:
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CRITICAL_EXCEPTION_PROLOG 0x1020 WDTException
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prepare_transfer_to_handler
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bl WatchdogException
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b ret_from_crit_exc
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/* Other PowerPC processors, namely those derived from the 6xx-series
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* have vectors from 0x2100 through 0x2F00 defined, but marked as reserved.
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* However, for the 4xx-series processors these are neither defined nor
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* reserved.
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*/
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__HEAD
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/* Damn, I came up one instruction too many to fit into the
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* exception space :-). Both the instruction and data TLB
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* miss get to this point to load the TLB.
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* r10 - TLB_TAG value
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* r11 - Linux PTE
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* r9 - available to use
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* PID - loaded with proper value when we get here
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* Upon exit, we reload everything and RFI.
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* Actually, it will fit now, but oh well.....a common place
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* to load the TLB.
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*/
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tlb_4xx_index:
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.long 0
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finish_tlb_load:
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/*
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* Clear out the software-only bits in the PTE to generate the
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* TLB_DATA value. These are the bottom 2 bits of the RPM, the
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* top 3 bits of the zone field, and M.
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*/
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li r9, 0x0ce2
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andc r11, r11, r9
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/* load the next available TLB index. */
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lwz r9, tlb_4xx_index@l(0)
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addi r9, r9, 1
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andi. r9, r9, PPC40X_TLB_SIZE - 1
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stw r9, tlb_4xx_index@l(0)
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tlbwe r11, r9, TLB_DATA /* Load TLB LO */
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tlbwe r10, r9, TLB_TAG /* Load TLB HI */
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/* Done...restore registers and get out of here.
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*/
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mtspr SPRN_PID, r12
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mtcrf 0x80, r12
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mfspr r9, SPRN_SPRG_SCRATCH4
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mfspr r12, SPRN_SPRG_SCRATCH3
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mfspr r11, SPRN_SPRG_SCRATCH6
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mfspr r10, SPRN_SPRG_SCRATCH5
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rfi /* Should sync shadow TLBs */
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b . /* prevent prefetch past rfi */
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/* This is where the main kernel code starts.
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*/
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start_here:
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/* ptr to current */
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lis r2,init_task@h
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ori r2,r2,init_task@l
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/* ptr to phys current thread */
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tophys(r4,r2)
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addi r4,r4,THREAD /* init task's THREAD */
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mtspr SPRN_SPRG_THREAD,r4
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/* stack */
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lis r1,init_thread_union@ha
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addi r1,r1,init_thread_union@l
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li r0,0
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stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
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bl early_init /* We have to do this with MMU on */
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/*
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* Decide what sort of machine this is and initialize the MMU.
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*/
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#ifdef CONFIG_KASAN
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bl kasan_early_init
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#endif
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li r3,0
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mr r4,r31
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bl machine_init
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bl MMU_init
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/* Go back to running unmapped so we can load up new values
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* and change to using our exception vectors.
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* On the 4xx, all we have to do is invalidate the TLB to clear
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* the old 16M byte TLB mappings.
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*/
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lis r4,2f@h
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ori r4,r4,2f@l
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tophys(r4,r4)
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lis r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@h
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ori r3,r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@l
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mtspr SPRN_SRR0,r4
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mtspr SPRN_SRR1,r3
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rfi
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b . /* prevent prefetch past rfi */
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/* Load up the kernel context */
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2:
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sync /* Flush to memory before changing TLB */
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tlbia
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isync /* Flush shadow TLBs */
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/* set up the PTE pointers for the Abatron bdiGDB.
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*/
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lis r6, swapper_pg_dir@h
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ori r6, r6, swapper_pg_dir@l
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lis r5, abatron_pteptrs@h
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ori r5, r5, abatron_pteptrs@l
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stw r5, 0xf0(0) /* Must match your Abatron config file */
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tophys(r5,r5)
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stw r6, 0(r5)
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/* Now turn on the MMU for real! */
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lis r4,MSR_KERNEL@h
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ori r4,r4,MSR_KERNEL@l
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lis r3,start_kernel@h
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ori r3,r3,start_kernel@l
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mtspr SPRN_SRR0,r3
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mtspr SPRN_SRR1,r4
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rfi /* enable MMU and jump to start_kernel */
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b . /* prevent prefetch past rfi */
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/* Set up the initial MMU state so we can do the first level of
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* kernel initialization. This maps the first 32 MBytes of memory 1:1
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* virtual to physical and more importantly sets the cache mode.
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*/
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initial_mmu:
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tlbia /* Invalidate all TLB entries */
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isync
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/* We should still be executing code at physical address 0x0000xxxx
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* at this point. However, start_here is at virtual address
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* 0xC000xxxx. So, set up a TLB mapping to cover this once
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* translation is enabled.
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*/
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lis r3,KERNELBASE@h /* Load the kernel virtual address */
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ori r3,r3,KERNELBASE@l
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tophys(r4,r3) /* Load the kernel physical address */
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iccci r0,r3 /* Invalidate the i-cache before use */
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/* Load the kernel PID.
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*/
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li r0,0
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mtspr SPRN_PID,r0
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sync
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/* Configure and load one entry into TLB slots 63 */
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clrrwi r4,r4,10 /* Mask off the real page number */
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ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */
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clrrwi r3,r3,10 /* Mask off the effective page number */
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ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M))
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li r0,63 /* TLB slot 63 */
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tlbwe r4,r0,TLB_DATA /* Load the data portion of the entry */
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tlbwe r3,r0,TLB_TAG /* Load the tag portion of the entry */
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li r0,62 /* TLB slot 62 */
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addis r4,r4,SZ_16M@h
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addis r3,r3,SZ_16M@h
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tlbwe r4,r0,TLB_DATA /* Load the data portion of the entry */
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tlbwe r3,r0,TLB_TAG /* Load the tag portion of the entry */
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isync
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/* Establish the exception vector base
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*/
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lis r4,KERNELBASE@h /* EVPR only uses the high 16-bits */
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tophys(r0,r4) /* Use the physical address */
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mtspr SPRN_EVPR,r0
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blr
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_GLOBAL(abort)
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mfspr r13,SPRN_DBCR0
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oris r13,r13,DBCR0_RST_SYSTEM@h
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mtspr SPRN_DBCR0,r13
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