156 строки
3.9 KiB
C
156 строки
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* RZ/G2L Clock Pulse Generator
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*
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*/
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#ifndef __RENESAS_RZG2L_CPG_H__
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#define __RENESAS_RZG2L_CPG_H__
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#define CPG_PL2_DDIV (0x204)
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#define CPG_PL3A_DDIV (0x208)
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/* n = 0/1/2 for PLL1/4/6 */
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#define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n))
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#define CPG_SAMPLL_CLK2(n) (0x08 + (16 * n))
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#define PLL146_CONF(n) (CPG_SAMPLL_CLK1(n) << 22 | CPG_SAMPLL_CLK2(n) << 12)
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#define DDIV_PACK(offset, bitpos, size) \
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(((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
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#define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3)
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#define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3)
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#define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3)
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/**
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* Definitions of CPG Core Clocks
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*
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* These include:
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* - Clock outputs exported to DT
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* - External input clocks
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* - Internal CPG clocks
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*/
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struct cpg_core_clk {
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const char *name;
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unsigned int id;
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unsigned int parent;
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unsigned int div;
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unsigned int mult;
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unsigned int type;
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unsigned int conf;
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const struct clk_div_table *dtable;
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const char * const *parent_names;
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int flag;
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int num_parents;
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};
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enum clk_types {
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/* Generic */
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CLK_TYPE_IN, /* External Clock Input */
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CLK_TYPE_FF, /* Fixed Factor Clock */
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CLK_TYPE_SAM_PLL,
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/* Clock with divider */
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CLK_TYPE_DIV,
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};
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#define DEF_TYPE(_name, _id, _type...) \
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{ .name = _name, .id = _id, .type = _type }
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#define DEF_BASE(_name, _id, _type, _parent...) \
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DEF_TYPE(_name, _id, _type, .parent = _parent)
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#define DEF_SAMPLL(_name, _id, _parent, _conf) \
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DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf)
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#define DEF_INPUT(_name, _id) \
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DEF_TYPE(_name, _id, CLK_TYPE_IN)
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#define DEF_FIXED(_name, _id, _parent, _mult, _div) \
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DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
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#define DEF_DIV(_name, _id, _parent, _conf, _dtable, _flag) \
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DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
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.parent = _parent, .dtable = _dtable, .flag = _flag)
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/**
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* struct rzg2l_mod_clk - Module Clocks definitions
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*
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* @name: handle between common and hardware-specific interfaces
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* @id: clock index in array containing all Core and Module Clocks
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* @parent: id of parent clock
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* @off: register offset
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* @bit: ON/MON bit
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*/
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struct rzg2l_mod_clk {
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const char *name;
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unsigned int id;
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unsigned int parent;
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u16 off;
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u8 bit;
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};
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#define DEF_MOD(_name, _id, _parent, _off, _bit) \
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{ \
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.name = _name, \
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.id = MOD_CLK_BASE + (_id), \
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.parent = (_parent), \
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.off = (_off), \
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.bit = (_bit), \
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}
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/**
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* struct rzg2l_reset - Reset definitions
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*
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* @off: register offset
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* @bit: reset bit
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*/
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struct rzg2l_reset {
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u16 off;
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u8 bit;
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};
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#define DEF_RST(_id, _off, _bit) \
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[_id] = { \
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.off = (_off), \
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.bit = (_bit) \
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}
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/**
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* struct rzg2l_cpg_info - SoC-specific CPG Description
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*
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* @core_clks: Array of Core Clock definitions
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* @num_core_clks: Number of entries in core_clks[]
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* @last_dt_core_clk: ID of the last Core Clock exported to DT
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* @num_total_core_clks: Total number of Core Clocks (exported + internal)
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*
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* @mod_clks: Array of Module Clock definitions
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* @num_mod_clks: Number of entries in mod_clks[]
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* @num_hw_mod_clks: Number of Module Clocks supported by the hardware
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*
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* @crit_mod_clks: Array with Module Clock IDs of critical clocks that
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* should not be disabled without a knowledgeable driver
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* @num_crit_mod_clks: Number of entries in crit_mod_clks[]
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*/
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struct rzg2l_cpg_info {
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/* Core Clocks */
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const struct cpg_core_clk *core_clks;
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unsigned int num_core_clks;
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unsigned int last_dt_core_clk;
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unsigned int num_total_core_clks;
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/* Module Clocks */
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const struct rzg2l_mod_clk *mod_clks;
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unsigned int num_mod_clks;
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unsigned int num_hw_mod_clks;
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/* Resets */
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const struct rzg2l_reset *resets;
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unsigned int num_resets;
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/* Critical Module Clocks that should not be disabled */
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const unsigned int *crit_mod_clks;
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unsigned int num_crit_mod_clks;
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};
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extern const struct rzg2l_cpg_info r9a07g044_cpg_info;
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#endif
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