446 строки
13 KiB
C
446 строки
13 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright 2018 SiFive, Inc.
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//
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// SiFive SPI controller driver (master mode only)
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//
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// Author: SiFive, Inc.
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// sifive@sifive.com
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/io.h>
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#include <linux/log2.h>
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#define SIFIVE_SPI_DRIVER_NAME "sifive_spi"
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#define SIFIVE_SPI_MAX_CS 32
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#define SIFIVE_SPI_DEFAULT_DEPTH 8
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#define SIFIVE_SPI_DEFAULT_MAX_BITS 8
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/* register offsets */
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#define SIFIVE_SPI_REG_SCKDIV 0x00 /* Serial clock divisor */
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#define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */
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#define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */
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#define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */
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#define SIFIVE_SPI_REG_CSMODE 0x18 /* Chip select mode */
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#define SIFIVE_SPI_REG_DELAY0 0x28 /* Delay control 0 */
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#define SIFIVE_SPI_REG_DELAY1 0x2c /* Delay control 1 */
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#define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */
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#define SIFIVE_SPI_REG_TXDATA 0x48 /* Tx FIFO data */
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#define SIFIVE_SPI_REG_RXDATA 0x4c /* Rx FIFO data */
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#define SIFIVE_SPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
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#define SIFIVE_SPI_REG_RXMARK 0x54 /* Rx FIFO watermark */
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#define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */
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#define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */
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#define SIFIVE_SPI_REG_IE 0x70 /* Interrupt Enable Register */
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#define SIFIVE_SPI_REG_IP 0x74 /* Interrupt Pendings Register */
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/* sckdiv bits */
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#define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU
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/* sckmode bits */
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#define SIFIVE_SPI_SCKMODE_PHA BIT(0)
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#define SIFIVE_SPI_SCKMODE_POL BIT(1)
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#define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA | \
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SIFIVE_SPI_SCKMODE_POL)
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/* csmode bits */
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#define SIFIVE_SPI_CSMODE_MODE_AUTO 0U
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#define SIFIVE_SPI_CSMODE_MODE_HOLD 2U
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#define SIFIVE_SPI_CSMODE_MODE_OFF 3U
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/* delay0 bits */
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#define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x))
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#define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU
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#define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16)
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#define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16)
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/* delay1 bits */
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#define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x))
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#define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU
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#define SIFIVE_SPI_DELAY1_INTERXFR(x) ((u32)(x) << 16)
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#define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16)
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/* fmt bits */
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#define SIFIVE_SPI_FMT_PROTO_SINGLE 0U
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#define SIFIVE_SPI_FMT_PROTO_DUAL 1U
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#define SIFIVE_SPI_FMT_PROTO_QUAD 2U
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#define SIFIVE_SPI_FMT_PROTO_MASK 3U
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#define SIFIVE_SPI_FMT_ENDIAN BIT(2)
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#define SIFIVE_SPI_FMT_DIR BIT(3)
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#define SIFIVE_SPI_FMT_LEN(x) ((u32)(x) << 16)
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#define SIFIVE_SPI_FMT_LEN_MASK (0xfU << 16)
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/* txdata bits */
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#define SIFIVE_SPI_TXDATA_DATA_MASK 0xffU
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#define SIFIVE_SPI_TXDATA_FULL BIT(31)
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/* rxdata bits */
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#define SIFIVE_SPI_RXDATA_DATA_MASK 0xffU
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#define SIFIVE_SPI_RXDATA_EMPTY BIT(31)
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/* ie and ip bits */
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#define SIFIVE_SPI_IP_TXWM BIT(0)
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#define SIFIVE_SPI_IP_RXWM BIT(1)
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struct sifive_spi {
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void __iomem *regs; /* virt. address of control registers */
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struct clk *clk; /* bus clock */
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unsigned int fifo_depth; /* fifo depth in words */
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u32 cs_inactive; /* level of the CS pins when inactive */
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struct completion done; /* wake-up from interrupt */
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};
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static void sifive_spi_write(struct sifive_spi *spi, int offset, u32 value)
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{
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iowrite32(value, spi->regs + offset);
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}
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static u32 sifive_spi_read(struct sifive_spi *spi, int offset)
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{
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return ioread32(spi->regs + offset);
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}
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static void sifive_spi_init(struct sifive_spi *spi)
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{
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/* Watermark interrupts are disabled by default */
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sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
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/* Default watermark FIFO threshold values */
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sifive_spi_write(spi, SIFIVE_SPI_REG_TXMARK, 1);
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sifive_spi_write(spi, SIFIVE_SPI_REG_RXMARK, 0);
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/* Set CS/SCK Delays and Inactive Time to defaults */
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sifive_spi_write(spi, SIFIVE_SPI_REG_DELAY0,
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SIFIVE_SPI_DELAY0_CSSCK(1) |
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SIFIVE_SPI_DELAY0_SCKCS(1));
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sifive_spi_write(spi, SIFIVE_SPI_REG_DELAY1,
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SIFIVE_SPI_DELAY1_INTERCS(1) |
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SIFIVE_SPI_DELAY1_INTERXFR(0));
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/* Exit specialized memory-mapped SPI flash mode */
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sifive_spi_write(spi, SIFIVE_SPI_REG_FCTRL, 0);
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}
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static int
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sifive_spi_prepare_message(struct spi_master *master, struct spi_message *msg)
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{
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struct sifive_spi *spi = spi_master_get_devdata(master);
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struct spi_device *device = msg->spi;
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/* Update the chip select polarity */
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if (device->mode & SPI_CS_HIGH)
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spi->cs_inactive &= ~BIT(device->chip_select);
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else
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spi->cs_inactive |= BIT(device->chip_select);
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sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);
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/* Select the correct device */
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sifive_spi_write(spi, SIFIVE_SPI_REG_CSID, device->chip_select);
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/* Set clock mode */
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sifive_spi_write(spi, SIFIVE_SPI_REG_SCKMODE,
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device->mode & SIFIVE_SPI_SCKMODE_MODE_MASK);
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return 0;
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}
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static void sifive_spi_set_cs(struct spi_device *device, bool is_high)
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{
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struct sifive_spi *spi = spi_master_get_devdata(device->master);
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/* Reverse polarity is handled by SCMR/CPOL. Not inverted CS. */
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if (device->mode & SPI_CS_HIGH)
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is_high = !is_high;
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sifive_spi_write(spi, SIFIVE_SPI_REG_CSMODE, is_high ?
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SIFIVE_SPI_CSMODE_MODE_AUTO :
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SIFIVE_SPI_CSMODE_MODE_HOLD);
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}
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static int
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sifive_spi_prep_transfer(struct sifive_spi *spi, struct spi_device *device,
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struct spi_transfer *t)
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{
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u32 cr;
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unsigned int mode;
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/* Calculate and program the clock rate */
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cr = DIV_ROUND_UP(clk_get_rate(spi->clk) >> 1, t->speed_hz) - 1;
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cr &= SIFIVE_SPI_SCKDIV_DIV_MASK;
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sifive_spi_write(spi, SIFIVE_SPI_REG_SCKDIV, cr);
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mode = max_t(unsigned int, t->rx_nbits, t->tx_nbits);
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/* Set frame format */
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cr = SIFIVE_SPI_FMT_LEN(t->bits_per_word);
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switch (mode) {
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case SPI_NBITS_QUAD:
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cr |= SIFIVE_SPI_FMT_PROTO_QUAD;
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break;
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case SPI_NBITS_DUAL:
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cr |= SIFIVE_SPI_FMT_PROTO_DUAL;
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break;
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default:
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cr |= SIFIVE_SPI_FMT_PROTO_SINGLE;
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break;
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}
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if (device->mode & SPI_LSB_FIRST)
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cr |= SIFIVE_SPI_FMT_ENDIAN;
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if (!t->rx_buf)
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cr |= SIFIVE_SPI_FMT_DIR;
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sifive_spi_write(spi, SIFIVE_SPI_REG_FMT, cr);
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/* We will want to poll if the time we need to wait is
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* less than the context switching time.
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* Let's call that threshold 5us. The operation will take:
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* (8/mode) * fifo_depth / hz <= 5 * 10^-6
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* 1600000 * fifo_depth <= hz * mode
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*/
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return 1600000 * spi->fifo_depth <= t->speed_hz * mode;
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}
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static irqreturn_t sifive_spi_irq(int irq, void *dev_id)
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{
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struct sifive_spi *spi = dev_id;
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u32 ip = sifive_spi_read(spi, SIFIVE_SPI_REG_IP);
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if (ip & (SIFIVE_SPI_IP_TXWM | SIFIVE_SPI_IP_RXWM)) {
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/* Disable interrupts until next transfer */
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sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
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complete(&spi->done);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static void sifive_spi_wait(struct sifive_spi *spi, u32 bit, int poll)
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{
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if (poll) {
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u32 cr;
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do {
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cr = sifive_spi_read(spi, SIFIVE_SPI_REG_IP);
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} while (!(cr & bit));
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} else {
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reinit_completion(&spi->done);
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sifive_spi_write(spi, SIFIVE_SPI_REG_IE, bit);
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wait_for_completion(&spi->done);
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}
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}
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static void sifive_spi_tx(struct sifive_spi *spi, const u8 *tx_ptr)
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{
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WARN_ON_ONCE((sifive_spi_read(spi, SIFIVE_SPI_REG_TXDATA)
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& SIFIVE_SPI_TXDATA_FULL) != 0);
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sifive_spi_write(spi, SIFIVE_SPI_REG_TXDATA,
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*tx_ptr & SIFIVE_SPI_TXDATA_DATA_MASK);
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}
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static void sifive_spi_rx(struct sifive_spi *spi, u8 *rx_ptr)
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{
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u32 data = sifive_spi_read(spi, SIFIVE_SPI_REG_RXDATA);
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WARN_ON_ONCE((data & SIFIVE_SPI_RXDATA_EMPTY) != 0);
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*rx_ptr = data & SIFIVE_SPI_RXDATA_DATA_MASK;
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}
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static int
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sifive_spi_transfer_one(struct spi_master *master, struct spi_device *device,
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struct spi_transfer *t)
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{
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struct sifive_spi *spi = spi_master_get_devdata(master);
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int poll = sifive_spi_prep_transfer(spi, device, t);
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const u8 *tx_ptr = t->tx_buf;
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u8 *rx_ptr = t->rx_buf;
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unsigned int remaining_words = t->len;
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while (remaining_words) {
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unsigned int n_words = min(remaining_words, spi->fifo_depth);
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unsigned int i;
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/* Enqueue n_words for transmission */
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for (i = 0; i < n_words; i++)
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sifive_spi_tx(spi, tx_ptr++);
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if (rx_ptr) {
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/* Wait for transmission + reception to complete */
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sifive_spi_write(spi, SIFIVE_SPI_REG_RXMARK,
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n_words - 1);
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sifive_spi_wait(spi, SIFIVE_SPI_IP_RXWM, poll);
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/* Read out all the data from the RX FIFO */
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for (i = 0; i < n_words; i++)
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sifive_spi_rx(spi, rx_ptr++);
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} else {
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/* Wait for transmission to complete */
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sifive_spi_wait(spi, SIFIVE_SPI_IP_TXWM, poll);
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}
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remaining_words -= n_words;
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}
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return 0;
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}
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static int sifive_spi_probe(struct platform_device *pdev)
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{
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struct sifive_spi *spi;
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int ret, irq, num_cs;
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u32 cs_bits, max_bits_per_word;
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struct spi_master *master;
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master = spi_alloc_master(&pdev->dev, sizeof(struct sifive_spi));
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if (!master) {
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dev_err(&pdev->dev, "out of memory\n");
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return -ENOMEM;
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}
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spi = spi_master_get_devdata(master);
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init_completion(&spi->done);
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platform_set_drvdata(pdev, master);
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spi->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(spi->regs)) {
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ret = PTR_ERR(spi->regs);
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goto put_master;
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}
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spi->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(spi->clk)) {
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dev_err(&pdev->dev, "Unable to find bus clock\n");
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ret = PTR_ERR(spi->clk);
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goto put_master;
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}
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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ret = irq;
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goto put_master;
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}
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/* Optional parameters */
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ret =
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of_property_read_u32(pdev->dev.of_node, "sifive,fifo-depth",
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&spi->fifo_depth);
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if (ret < 0)
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spi->fifo_depth = SIFIVE_SPI_DEFAULT_DEPTH;
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ret =
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of_property_read_u32(pdev->dev.of_node, "sifive,max-bits-per-word",
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&max_bits_per_word);
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if (!ret && max_bits_per_word < 8) {
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dev_err(&pdev->dev, "Only 8bit SPI words supported by the driver\n");
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ret = -EINVAL;
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goto put_master;
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}
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/* Spin up the bus clock before hitting registers */
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ret = clk_prepare_enable(spi->clk);
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if (ret) {
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dev_err(&pdev->dev, "Unable to enable bus clock\n");
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goto put_master;
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}
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/* probe the number of CS lines */
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spi->cs_inactive = sifive_spi_read(spi, SIFIVE_SPI_REG_CSDEF);
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sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, 0xffffffffU);
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cs_bits = sifive_spi_read(spi, SIFIVE_SPI_REG_CSDEF);
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sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);
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if (!cs_bits) {
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dev_err(&pdev->dev, "Could not auto probe CS lines\n");
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ret = -EINVAL;
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goto put_master;
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}
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num_cs = ilog2(cs_bits) + 1;
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if (num_cs > SIFIVE_SPI_MAX_CS) {
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dev_err(&pdev->dev, "Invalid number of spi slaves\n");
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ret = -EINVAL;
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goto put_master;
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}
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/* Define our master */
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master->dev.of_node = pdev->dev.of_node;
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master->bus_num = pdev->id;
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master->num_chipselect = num_cs;
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master->mode_bits = SPI_CPHA | SPI_CPOL
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| SPI_CS_HIGH | SPI_LSB_FIRST
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| SPI_TX_DUAL | SPI_TX_QUAD
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| SPI_RX_DUAL | SPI_RX_QUAD;
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/* TODO: add driver support for bits_per_word < 8
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* we need to "left-align" the bits (unless SPI_LSB_FIRST)
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*/
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master->bits_per_word_mask = SPI_BPW_MASK(8);
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master->flags = SPI_CONTROLLER_MUST_TX | SPI_MASTER_GPIO_SS;
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master->prepare_message = sifive_spi_prepare_message;
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master->set_cs = sifive_spi_set_cs;
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master->transfer_one = sifive_spi_transfer_one;
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pdev->dev.dma_mask = NULL;
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/* Configure the SPI master hardware */
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sifive_spi_init(spi);
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/* Register for SPI Interrupt */
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ret = devm_request_irq(&pdev->dev, irq, sifive_spi_irq, 0,
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dev_name(&pdev->dev), spi);
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if (ret) {
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dev_err(&pdev->dev, "Unable to bind to interrupt\n");
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goto put_master;
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}
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dev_info(&pdev->dev, "mapped; irq=%d, cs=%d\n",
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irq, master->num_chipselect);
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ret = devm_spi_register_master(&pdev->dev, master);
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if (ret < 0) {
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dev_err(&pdev->dev, "spi_register_master failed\n");
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goto put_master;
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}
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return 0;
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put_master:
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spi_master_put(master);
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return ret;
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}
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static int sifive_spi_remove(struct platform_device *pdev)
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{
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struct spi_master *master = platform_get_drvdata(pdev);
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struct sifive_spi *spi = spi_master_get_devdata(master);
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/* Disable all the interrupts just in case */
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sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
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return 0;
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}
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static const struct of_device_id sifive_spi_of_match[] = {
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{ .compatible = "sifive,spi0", },
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{}
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};
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MODULE_DEVICE_TABLE(of, sifive_spi_of_match);
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static struct platform_driver sifive_spi_driver = {
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.probe = sifive_spi_probe,
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.remove = sifive_spi_remove,
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.driver = {
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.name = SIFIVE_SPI_DRIVER_NAME,
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.of_match_table = sifive_spi_of_match,
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},
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};
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module_platform_driver(sifive_spi_driver);
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MODULE_AUTHOR("SiFive, Inc. <sifive@sifive.com>");
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MODULE_DESCRIPTION("SiFive SPI driver");
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MODULE_LICENSE("GPL");
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