528 строки
13 KiB
C
528 строки
13 KiB
C
/*
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* linux/sound/soc/ep93xx-i2s.c
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* EP93xx I2S driver
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*
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* Copyright (C) 2010 Ryan Mallon
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*
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* Based on the original driver by:
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* Copyright (C) 2007 Chase Douglas <chasedouglas@gmail>
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* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <sound/core.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include <linux/platform_data/dma-ep93xx.h>
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#include <linux/soc/cirrus/ep93xx.h>
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#include "ep93xx-pcm.h"
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#define EP93XX_I2S_TXCLKCFG 0x00
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#define EP93XX_I2S_RXCLKCFG 0x04
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#define EP93XX_I2S_GLSTS 0x08
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#define EP93XX_I2S_GLCTRL 0x0C
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#define EP93XX_I2S_I2STX0LFT 0x10
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#define EP93XX_I2S_I2STX0RT 0x14
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#define EP93XX_I2S_TXLINCTRLDATA 0x28
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#define EP93XX_I2S_TXCTRL 0x2C
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#define EP93XX_I2S_TXWRDLEN 0x30
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#define EP93XX_I2S_TX0EN 0x34
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#define EP93XX_I2S_RXLINCTRLDATA 0x58
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#define EP93XX_I2S_RXCTRL 0x5C
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#define EP93XX_I2S_RXWRDLEN 0x60
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#define EP93XX_I2S_RX0EN 0x64
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#define EP93XX_I2S_WRDLEN_16 (0 << 0)
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#define EP93XX_I2S_WRDLEN_24 (1 << 0)
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#define EP93XX_I2S_WRDLEN_32 (2 << 0)
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#define EP93XX_I2S_RXLINCTRLDATA_R_JUST BIT(1) /* Right justify */
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#define EP93XX_I2S_TXLINCTRLDATA_R_JUST BIT(2) /* Right justify */
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/*
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* Transmit empty interrupt level select:
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* 0 - Generate interrupt when FIFO is half empty
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* 1 - Generate interrupt when FIFO is empty
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*/
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#define EP93XX_I2S_TXCTRL_TXEMPTY_LVL BIT(0)
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#define EP93XX_I2S_TXCTRL_TXUFIE BIT(1) /* Transmit interrupt enable */
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#define EP93XX_I2S_CLKCFG_LRS (1 << 0) /* lrclk polarity */
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#define EP93XX_I2S_CLKCFG_CKP (1 << 1) /* Bit clock polarity */
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#define EP93XX_I2S_CLKCFG_REL (1 << 2) /* First bit transition */
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#define EP93XX_I2S_CLKCFG_MASTER (1 << 3) /* Master mode */
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#define EP93XX_I2S_CLKCFG_NBCG (1 << 4) /* Not bit clock gating */
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#define EP93XX_I2S_GLSTS_TX0_FIFO_FULL BIT(12)
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struct ep93xx_i2s_info {
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struct clk *mclk;
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struct clk *sclk;
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struct clk *lrclk;
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void __iomem *regs;
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struct snd_dmaengine_dai_dma_data dma_params_rx;
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struct snd_dmaengine_dai_dma_data dma_params_tx;
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};
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static struct ep93xx_dma_data ep93xx_i2s_dma_data[] = {
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[SNDRV_PCM_STREAM_PLAYBACK] = {
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.name = "i2s-pcm-out",
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.port = EP93XX_DMA_I2S1,
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.direction = DMA_MEM_TO_DEV,
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},
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[SNDRV_PCM_STREAM_CAPTURE] = {
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.name = "i2s-pcm-in",
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.port = EP93XX_DMA_I2S1,
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.direction = DMA_DEV_TO_MEM,
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},
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};
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static inline void ep93xx_i2s_write_reg(struct ep93xx_i2s_info *info,
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unsigned reg, unsigned val)
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{
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__raw_writel(val, info->regs + reg);
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}
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static inline unsigned ep93xx_i2s_read_reg(struct ep93xx_i2s_info *info,
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unsigned reg)
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{
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return __raw_readl(info->regs + reg);
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}
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static void ep93xx_i2s_enable(struct ep93xx_i2s_info *info, int stream)
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{
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unsigned base_reg;
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if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
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(ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
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/* Enable clocks */
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clk_enable(info->mclk);
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clk_enable(info->sclk);
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clk_enable(info->lrclk);
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/* Enable i2s */
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ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 1);
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}
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/* Enable fifo */
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if (stream == SNDRV_PCM_STREAM_PLAYBACK)
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base_reg = EP93XX_I2S_TX0EN;
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else
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base_reg = EP93XX_I2S_RX0EN;
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ep93xx_i2s_write_reg(info, base_reg, 1);
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/* Enable TX IRQs (FIFO empty or underflow) */
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if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG) &&
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stream == SNDRV_PCM_STREAM_PLAYBACK)
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ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCTRL,
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EP93XX_I2S_TXCTRL_TXEMPTY_LVL |
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EP93XX_I2S_TXCTRL_TXUFIE);
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}
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static void ep93xx_i2s_disable(struct ep93xx_i2s_info *info, int stream)
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{
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unsigned base_reg;
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/* Disable IRQs */
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if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG) &&
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stream == SNDRV_PCM_STREAM_PLAYBACK)
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ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCTRL, 0);
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/* Disable fifo */
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if (stream == SNDRV_PCM_STREAM_PLAYBACK)
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base_reg = EP93XX_I2S_TX0EN;
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else
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base_reg = EP93XX_I2S_RX0EN;
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ep93xx_i2s_write_reg(info, base_reg, 0);
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if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
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(ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
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/* Disable i2s */
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ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 0);
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/* Disable clocks */
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clk_disable(info->lrclk);
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clk_disable(info->sclk);
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clk_disable(info->mclk);
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}
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}
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/*
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* According to documentation I2S controller can handle underflow conditions
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* just fine, but in reality the state machine is sometimes confused so that
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* the whole stream is shifted by one byte. The watchdog below disables the TX
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* FIFO, fills the buffer with zeroes and re-enables the FIFO. State machine
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* is being reset and by filling the buffer we get some time before next
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* underflow happens.
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*/
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static irqreturn_t ep93xx_i2s_interrupt(int irq, void *dev_id)
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{
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struct ep93xx_i2s_info *info = dev_id;
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/* Disable FIFO */
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ep93xx_i2s_write_reg(info, EP93XX_I2S_TX0EN, 0);
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/*
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* Fill TX FIFO with zeroes, this way we can defer next IRQs as much as
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* possible and get more time for DMA to catch up. Actually there are
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* only 8 samples in this FIFO, so even on 8kHz maximum deferral here is
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* 1ms.
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*/
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while (!(ep93xx_i2s_read_reg(info, EP93XX_I2S_GLSTS) &
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EP93XX_I2S_GLSTS_TX0_FIFO_FULL)) {
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ep93xx_i2s_write_reg(info, EP93XX_I2S_I2STX0LFT, 0);
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ep93xx_i2s_write_reg(info, EP93XX_I2S_I2STX0RT, 0);
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}
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/* Re-enable FIFO */
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ep93xx_i2s_write_reg(info, EP93XX_I2S_TX0EN, 1);
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return IRQ_HANDLED;
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}
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static int ep93xx_i2s_dai_probe(struct snd_soc_dai *dai)
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{
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struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
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info->dma_params_tx.filter_data =
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&ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_PLAYBACK];
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info->dma_params_rx.filter_data =
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&ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_CAPTURE];
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dai->playback_dma_data = &info->dma_params_tx;
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dai->capture_dma_data = &info->dma_params_rx;
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return 0;
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}
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static void ep93xx_i2s_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
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ep93xx_i2s_disable(info, substream->stream);
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}
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static int ep93xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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unsigned int fmt)
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{
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struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
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unsigned int clk_cfg;
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unsigned int txlin_ctrl = 0;
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unsigned int rxlin_ctrl = 0;
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clk_cfg = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXCLKCFG);
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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clk_cfg |= EP93XX_I2S_CLKCFG_REL;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
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break;
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case SND_SOC_DAIFMT_RIGHT_J:
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clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
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rxlin_ctrl |= EP93XX_I2S_RXLINCTRLDATA_R_JUST;
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txlin_ctrl |= EP93XX_I2S_TXLINCTRLDATA_R_JUST;
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break;
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default:
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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/* CPU is master */
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clk_cfg |= EP93XX_I2S_CLKCFG_MASTER;
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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/* Codec is master */
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clk_cfg &= ~EP93XX_I2S_CLKCFG_MASTER;
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break;
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default:
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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/* Negative bit clock, lrclk low on left word */
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clk_cfg &= ~(EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_LRS);
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break;
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case SND_SOC_DAIFMT_NB_IF:
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/* Negative bit clock, lrclk low on right word */
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clk_cfg &= ~EP93XX_I2S_CLKCFG_CKP;
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clk_cfg |= EP93XX_I2S_CLKCFG_LRS;
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break;
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case SND_SOC_DAIFMT_IB_NF:
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/* Positive bit clock, lrclk low on left word */
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clk_cfg |= EP93XX_I2S_CLKCFG_CKP;
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clk_cfg &= ~EP93XX_I2S_CLKCFG_LRS;
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break;
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case SND_SOC_DAIFMT_IB_IF:
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/* Positive bit clock, lrclk low on right word */
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clk_cfg |= EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_LRS;
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break;
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}
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/* Write new register values */
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ep93xx_i2s_write_reg(info, EP93XX_I2S_RXCLKCFG, clk_cfg);
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ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCLKCFG, clk_cfg);
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ep93xx_i2s_write_reg(info, EP93XX_I2S_RXLINCTRLDATA, rxlin_ctrl);
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ep93xx_i2s_write_reg(info, EP93XX_I2S_TXLINCTRLDATA, txlin_ctrl);
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return 0;
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}
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static int ep93xx_i2s_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
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unsigned word_len, div, sdiv, lrdiv;
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int err;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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word_len = EP93XX_I2S_WRDLEN_16;
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break;
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case SNDRV_PCM_FORMAT_S24_LE:
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word_len = EP93XX_I2S_WRDLEN_24;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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word_len = EP93XX_I2S_WRDLEN_32;
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break;
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default:
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return -EINVAL;
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}
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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ep93xx_i2s_write_reg(info, EP93XX_I2S_TXWRDLEN, word_len);
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else
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ep93xx_i2s_write_reg(info, EP93XX_I2S_RXWRDLEN, word_len);
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/*
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* EP93xx I2S module can be setup so SCLK / LRCLK value can be
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* 32, 64, 128. MCLK / SCLK value can be 2 and 4.
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* We set LRCLK equal to `rate' and minimum SCLK / LRCLK
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* value is 64, because our sample size is 32 bit * 2 channels.
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* I2S standard permits us to transmit more bits than
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* the codec uses.
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*/
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div = clk_get_rate(info->mclk) / params_rate(params);
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sdiv = 4;
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if (div > (256 + 512) / 2) {
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lrdiv = 128;
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} else {
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lrdiv = 64;
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if (div < (128 + 256) / 2)
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sdiv = 2;
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}
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err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv);
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if (err)
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return err;
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err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv);
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if (err)
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return err;
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ep93xx_i2s_enable(info, substream->stream);
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return 0;
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}
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static int ep93xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
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unsigned int freq, int dir)
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{
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struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
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if (dir == SND_SOC_CLOCK_IN || clk_id != 0)
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return -EINVAL;
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return clk_set_rate(info->mclk, freq);
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}
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#ifdef CONFIG_PM
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static int ep93xx_i2s_suspend(struct snd_soc_dai *dai)
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{
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struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
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if (!dai->active)
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return 0;
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ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_PLAYBACK);
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ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_CAPTURE);
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return 0;
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}
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static int ep93xx_i2s_resume(struct snd_soc_dai *dai)
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{
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struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
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if (!dai->active)
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return 0;
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ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_PLAYBACK);
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ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_CAPTURE);
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return 0;
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}
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#else
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#define ep93xx_i2s_suspend NULL
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#define ep93xx_i2s_resume NULL
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#endif
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static const struct snd_soc_dai_ops ep93xx_i2s_dai_ops = {
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.shutdown = ep93xx_i2s_shutdown,
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.hw_params = ep93xx_i2s_hw_params,
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.set_sysclk = ep93xx_i2s_set_sysclk,
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.set_fmt = ep93xx_i2s_set_dai_fmt,
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};
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#define EP93XX_I2S_FORMATS (SNDRV_PCM_FMTBIT_S32_LE)
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static struct snd_soc_dai_driver ep93xx_i2s_dai = {
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.symmetric_rates= 1,
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.probe = ep93xx_i2s_dai_probe,
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.suspend = ep93xx_i2s_suspend,
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.resume = ep93xx_i2s_resume,
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.playback = {
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.channels_min = 2,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_192000,
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.formats = EP93XX_I2S_FORMATS,
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},
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.capture = {
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.channels_min = 2,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_192000,
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.formats = EP93XX_I2S_FORMATS,
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},
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.ops = &ep93xx_i2s_dai_ops,
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};
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static const struct snd_soc_component_driver ep93xx_i2s_component = {
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.name = "ep93xx-i2s",
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};
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static int ep93xx_i2s_probe(struct platform_device *pdev)
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{
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struct ep93xx_i2s_info *info;
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struct resource *res;
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int err;
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info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
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if (!info)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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info->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(info->regs))
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return PTR_ERR(info->regs);
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if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG)) {
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int irq = platform_get_irq(pdev, 0);
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if (irq <= 0)
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return irq < 0 ? irq : -ENODEV;
|
|
|
|
err = devm_request_irq(&pdev->dev, irq, ep93xx_i2s_interrupt, 0,
|
|
pdev->name, info);
|
|
if (err)
|
|
return err;
|
|
}
|
|
|
|
info->mclk = clk_get(&pdev->dev, "mclk");
|
|
if (IS_ERR(info->mclk)) {
|
|
err = PTR_ERR(info->mclk);
|
|
goto fail;
|
|
}
|
|
|
|
info->sclk = clk_get(&pdev->dev, "sclk");
|
|
if (IS_ERR(info->sclk)) {
|
|
err = PTR_ERR(info->sclk);
|
|
goto fail_put_mclk;
|
|
}
|
|
|
|
info->lrclk = clk_get(&pdev->dev, "lrclk");
|
|
if (IS_ERR(info->lrclk)) {
|
|
err = PTR_ERR(info->lrclk);
|
|
goto fail_put_sclk;
|
|
}
|
|
|
|
dev_set_drvdata(&pdev->dev, info);
|
|
|
|
err = snd_soc_register_component(&pdev->dev, &ep93xx_i2s_component,
|
|
&ep93xx_i2s_dai, 1);
|
|
if (err)
|
|
goto fail_put_lrclk;
|
|
|
|
err = devm_ep93xx_pcm_platform_register(&pdev->dev);
|
|
if (err)
|
|
goto fail_unregister;
|
|
|
|
return 0;
|
|
|
|
fail_unregister:
|
|
snd_soc_unregister_component(&pdev->dev);
|
|
fail_put_lrclk:
|
|
clk_put(info->lrclk);
|
|
fail_put_sclk:
|
|
clk_put(info->sclk);
|
|
fail_put_mclk:
|
|
clk_put(info->mclk);
|
|
fail:
|
|
return err;
|
|
}
|
|
|
|
static int ep93xx_i2s_remove(struct platform_device *pdev)
|
|
{
|
|
struct ep93xx_i2s_info *info = dev_get_drvdata(&pdev->dev);
|
|
|
|
snd_soc_unregister_component(&pdev->dev);
|
|
clk_put(info->lrclk);
|
|
clk_put(info->sclk);
|
|
clk_put(info->mclk);
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver ep93xx_i2s_driver = {
|
|
.probe = ep93xx_i2s_probe,
|
|
.remove = ep93xx_i2s_remove,
|
|
.driver = {
|
|
.name = "ep93xx-i2s",
|
|
},
|
|
};
|
|
|
|
module_platform_driver(ep93xx_i2s_driver);
|
|
|
|
MODULE_ALIAS("platform:ep93xx-i2s");
|
|
MODULE_AUTHOR("Ryan Mallon");
|
|
MODULE_DESCRIPTION("EP93XX I2S driver");
|
|
MODULE_LICENSE("GPL");
|