619 строки
16 KiB
C
619 строки
16 KiB
C
/*
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* linux/sound/soc/m8m/hi6210_i2s.c - I2S IP driver
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*
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* Copyright (C) 2015 Linaro, Ltd
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* Author: Andy Green <andy.green@linaro.org>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* This driver only deals with S2 interface (BT)
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/jiffies.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include <linux/interrupt.h>
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#include <linux/reset.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/mfd/syscon.h>
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#include <linux/reset-controller.h>
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#include "hi6210-i2s.h"
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struct hi6210_i2s {
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struct device *dev;
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struct reset_control *rc;
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struct clk *clk[8];
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int clocks;
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struct snd_soc_dai_driver dai;
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void __iomem *base;
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struct regmap *sysctrl;
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phys_addr_t base_phys;
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struct snd_dmaengine_dai_dma_data dma_data[2];
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int clk_rate;
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spinlock_t lock;
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int rate;
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int format;
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u8 bits;
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u8 channels;
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u8 id;
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u8 channel_length;
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u8 use;
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u32 master:1;
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u32 status:1;
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};
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#define SC_PERIPH_CLKEN1 0x210
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#define SC_PERIPH_CLKDIS1 0x214
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#define SC_PERIPH_CLKEN3 0x230
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#define SC_PERIPH_CLKDIS3 0x234
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#define SC_PERIPH_CLKEN12 0x270
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#define SC_PERIPH_CLKDIS12 0x274
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#define SC_PERIPH_RSTEN1 0x310
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#define SC_PERIPH_RSTDIS1 0x314
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#define SC_PERIPH_RSTSTAT1 0x318
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#define SC_PERIPH_RSTEN2 0x320
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#define SC_PERIPH_RSTDIS2 0x324
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#define SC_PERIPH_RSTSTAT2 0x328
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#define SOC_PMCTRL_BBPPLLALIAS 0x48
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enum {
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CLK_DACODEC,
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CLK_I2S_BASE,
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};
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static inline void hi6210_write_reg(struct hi6210_i2s *i2s, int reg, u32 val)
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{
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writel(val, i2s->base + reg);
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}
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static inline u32 hi6210_read_reg(struct hi6210_i2s *i2s, int reg)
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{
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return readl(i2s->base + reg);
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}
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static int hi6210_i2s_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *cpu_dai)
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{
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struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
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int ret, n;
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u32 val;
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/* deassert reset on ABB */
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regmap_read(i2s->sysctrl, SC_PERIPH_RSTSTAT2, &val);
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if (val & BIT(4))
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regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS2, BIT(4));
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for (n = 0; n < i2s->clocks; n++) {
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ret = clk_prepare_enable(i2s->clk[n]);
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if (ret) {
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while (n--)
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clk_disable_unprepare(i2s->clk[n]);
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return ret;
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}
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}
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ret = clk_set_rate(i2s->clk[CLK_I2S_BASE], 49152000);
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if (ret) {
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dev_err(i2s->dev, "%s: setting 49.152MHz base rate failed %d\n",
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__func__, ret);
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return ret;
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}
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/* enable clock before frequency division */
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regmap_write(i2s->sysctrl, SC_PERIPH_CLKEN12, BIT(9));
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/* enable codec working clock / == "codec bus clock" */
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regmap_write(i2s->sysctrl, SC_PERIPH_CLKEN1, BIT(5));
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/* deassert reset on codec / interface clock / working clock */
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regmap_write(i2s->sysctrl, SC_PERIPH_RSTEN1, BIT(5));
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regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS1, BIT(5));
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/* not interested in i2s irqs */
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val = hi6210_read_reg(i2s, HII2S_CODEC_IRQ_MASK);
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val |= 0x3f;
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hi6210_write_reg(i2s, HII2S_CODEC_IRQ_MASK, val);
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/* reset the stereo downlink fifo */
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val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);
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val |= (BIT(5) | BIT(4));
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hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);
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val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);
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val &= ~(BIT(5) | BIT(4));
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hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);
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val = hi6210_read_reg(i2s, HII2S_SW_RST_N);
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val &= ~(HII2S_SW_RST_N__ST_DL_WORDLEN_MASK <<
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HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT);
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val |= (HII2S_BITS_16 << HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT);
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hi6210_write_reg(i2s, HII2S_SW_RST_N, val);
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val = hi6210_read_reg(i2s, HII2S_MISC_CFG);
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/* mux 11/12 = APB not i2s */
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val &= ~HII2S_MISC_CFG__ST_DL_TEST_SEL;
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/* BT R ch 0 = mixer op of DACR ch */
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val &= ~HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL;
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val &= ~HII2S_MISC_CFG__S2_DOUT_TEST_SEL;
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val |= HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL;
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/* BT L ch = 1 = mux 7 = "mixer output of DACL */
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val |= HII2S_MISC_CFG__S2_DOUT_TEST_SEL;
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hi6210_write_reg(i2s, HII2S_MISC_CFG, val);
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val = hi6210_read_reg(i2s, HII2S_SW_RST_N);
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val |= HII2S_SW_RST_N__SW_RST_N;
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hi6210_write_reg(i2s, HII2S_SW_RST_N, val);
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return 0;
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}
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static void hi6210_i2s_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *cpu_dai)
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{
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struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
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int n;
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for (n = 0; n < i2s->clocks; n++)
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clk_disable_unprepare(i2s->clk[n]);
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regmap_write(i2s->sysctrl, SC_PERIPH_RSTEN1, BIT(5));
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}
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static void hi6210_i2s_txctrl(struct snd_soc_dai *cpu_dai, int on)
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{
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struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
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u32 val;
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spin_lock(&i2s->lock);
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if (on) {
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/* enable S2 TX */
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val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
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val |= HII2S_I2S_CFG__S2_IF_TX_EN;
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hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
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} else {
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/* disable S2 TX */
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val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
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val &= ~HII2S_I2S_CFG__S2_IF_TX_EN;
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hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
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}
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spin_unlock(&i2s->lock);
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}
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static void hi6210_i2s_rxctrl(struct snd_soc_dai *cpu_dai, int on)
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{
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struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
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u32 val;
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spin_lock(&i2s->lock);
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if (on) {
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val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
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val |= HII2S_I2S_CFG__S2_IF_RX_EN;
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hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
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} else {
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val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
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val &= ~HII2S_I2S_CFG__S2_IF_RX_EN;
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hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
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}
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spin_unlock(&i2s->lock);
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}
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static int hi6210_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
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{
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struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
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/*
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* We don't actually set the hardware until the hw_params
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* call, but we need to validate the user input here.
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*/
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBM_CFM:
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case SND_SOC_DAIFMT_CBS_CFS:
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break;
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default:
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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case SND_SOC_DAIFMT_LEFT_J:
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case SND_SOC_DAIFMT_RIGHT_J:
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break;
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default:
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return -EINVAL;
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}
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i2s->format = fmt;
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i2s->master = (i2s->format & SND_SOC_DAIFMT_MASTER_MASK) ==
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SND_SOC_DAIFMT_CBS_CFS;
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return 0;
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}
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static int hi6210_i2s_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *cpu_dai)
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{
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struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
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u32 bits = 0, rate = 0, signed_data = 0, fmt = 0;
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u32 val;
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struct snd_dmaengine_dai_dma_data *dma_data;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_U16_LE:
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signed_data = HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
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/* fall through */
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case SNDRV_PCM_FORMAT_S16_LE:
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bits = HII2S_BITS_16;
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break;
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case SNDRV_PCM_FORMAT_U24_LE:
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signed_data = HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
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/* fall through */
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case SNDRV_PCM_FORMAT_S24_LE:
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bits = HII2S_BITS_24;
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break;
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default:
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dev_err(cpu_dai->dev, "Bad format\n");
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return -EINVAL;
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}
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switch (params_rate(params)) {
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case 8000:
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rate = HII2S_FS_RATE_8KHZ;
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break;
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case 16000:
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rate = HII2S_FS_RATE_16KHZ;
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break;
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case 32000:
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rate = HII2S_FS_RATE_32KHZ;
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break;
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case 48000:
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rate = HII2S_FS_RATE_48KHZ;
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break;
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case 96000:
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rate = HII2S_FS_RATE_96KHZ;
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break;
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case 192000:
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rate = HII2S_FS_RATE_192KHZ;
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break;
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default:
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dev_err(cpu_dai->dev, "Bad rate: %d\n", params_rate(params));
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return -EINVAL;
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}
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if (!(params_channels(params))) {
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dev_err(cpu_dai->dev, "Bad channels\n");
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return -EINVAL;
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}
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dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
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switch (bits) {
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case HII2S_BITS_24:
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i2s->bits = 32;
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dma_data->addr_width = 3;
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break;
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default:
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i2s->bits = 16;
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dma_data->addr_width = 2;
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break;
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}
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i2s->rate = params_rate(params);
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i2s->channels = params_channels(params);
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i2s->channel_length = i2s->channels * i2s->bits;
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val = hi6210_read_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG);
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val &= ~((HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_MASK <<
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HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT) |
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(HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_MASK <<
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HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_SHIFT) |
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(HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_MASK <<
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HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_SHIFT) |
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(HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_MASK <<
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HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_SHIFT));
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val |= ((16 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT) |
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(30 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_SHIFT) |
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(16 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_SHIFT) |
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(30 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_SHIFT));
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hi6210_write_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG, val);
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val = hi6210_read_reg(i2s, HII2S_IF_CLK_EN_CFG);
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val |= (BIT(19) | BIT(18) | BIT(17) |
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HII2S_IF_CLK_EN_CFG__S2_IF_CLK_EN |
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HII2S_IF_CLK_EN_CFG__S2_OL_MIXER_EN |
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HII2S_IF_CLK_EN_CFG__S2_OL_SRC_EN |
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HII2S_IF_CLK_EN_CFG__ST_DL_R_EN |
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HII2S_IF_CLK_EN_CFG__ST_DL_L_EN);
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hi6210_write_reg(i2s, HII2S_IF_CLK_EN_CFG, val);
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val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG);
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val &= ~(HII2S_DIG_FILTER_CLK_EN_CFG__DACR_SDM_EN |
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HII2S_DIG_FILTER_CLK_EN_CFG__DACR_HBF2I_EN |
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HII2S_DIG_FILTER_CLK_EN_CFG__DACR_AGC_EN |
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HII2S_DIG_FILTER_CLK_EN_CFG__DACL_SDM_EN |
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HII2S_DIG_FILTER_CLK_EN_CFG__DACL_HBF2I_EN |
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HII2S_DIG_FILTER_CLK_EN_CFG__DACL_AGC_EN);
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val |= (HII2S_DIG_FILTER_CLK_EN_CFG__DACR_MIXER_EN |
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HII2S_DIG_FILTER_CLK_EN_CFG__DACL_MIXER_EN);
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hi6210_write_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG, val);
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val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG);
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val &= ~(HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN2_MUTE |
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HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN2_MUTE);
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hi6210_write_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG, val);
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val = hi6210_read_reg(i2s, HII2S_MUX_TOP_MODULE_CFG);
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val &= ~(HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN1_MUTE |
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HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN2_MUTE |
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HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN1_MUTE |
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HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN2_MUTE);
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hi6210_write_reg(i2s, HII2S_MUX_TOP_MODULE_CFG, val);
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switch (i2s->format & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBM_CFM:
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i2s->master = false;
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val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
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val |= HII2S_I2S_CFG__S2_MST_SLV;
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hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
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break;
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case SND_SOC_DAIFMT_CBS_CFS:
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i2s->master = true;
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val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
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val &= ~HII2S_I2S_CFG__S2_MST_SLV;
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hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
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break;
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default:
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WARN_ONCE(1, "Invalid i2s->fmt MASTER_MASK. This shouldn't happen\n");
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return -EINVAL;
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}
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switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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fmt = HII2S_FORMAT_I2S;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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fmt = HII2S_FORMAT_LEFT_JUST;
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break;
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case SND_SOC_DAIFMT_RIGHT_J:
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fmt = HII2S_FORMAT_RIGHT_JUST;
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break;
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default:
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WARN_ONCE(1, "Invalid i2s->fmt FORMAT_MASK. This shouldn't happen\n");
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return -EINVAL;
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}
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val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
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val &= ~(HII2S_I2S_CFG__S2_FUNC_MODE_MASK <<
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HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT);
|
|
val |= fmt << HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT;
|
|
hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
|
|
|
|
|
|
val = hi6210_read_reg(i2s, HII2S_CLK_SEL);
|
|
val &= ~(HII2S_CLK_SEL__I2S_BT_FM_SEL | /* BT gets the I2S */
|
|
HII2S_CLK_SEL__EXT_12_288MHZ_SEL);
|
|
hi6210_write_reg(i2s, HII2S_CLK_SEL, val);
|
|
|
|
dma_data->maxburst = 2;
|
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
dma_data->addr = i2s->base_phys + HII2S_ST_DL_CHANNEL;
|
|
else
|
|
dma_data->addr = i2s->base_phys + HII2S_STEREO_UPLINK_CHANNEL;
|
|
|
|
switch (i2s->channels) {
|
|
case 1:
|
|
val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
|
|
val |= HII2S_I2S_CFG__S2_FRAME_MODE;
|
|
hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
|
|
break;
|
|
default:
|
|
val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
|
|
val &= ~HII2S_I2S_CFG__S2_FRAME_MODE;
|
|
hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
|
|
break;
|
|
}
|
|
|
|
/* clear loopback, set signed type and word length */
|
|
val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
|
|
val &= ~HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
|
|
val &= ~(HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_MASK <<
|
|
HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT);
|
|
val &= ~(HII2S_I2S_CFG__S2_DIRECT_LOOP_MASK <<
|
|
HII2S_I2S_CFG__S2_DIRECT_LOOP_SHIFT);
|
|
val |= signed_data;
|
|
val |= (bits << HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT);
|
|
hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
|
|
|
|
|
|
if (!i2s->master)
|
|
return 0;
|
|
|
|
/* set DAC and related units to correct rate */
|
|
val = hi6210_read_reg(i2s, HII2S_FS_CFG);
|
|
val &= ~(HII2S_FS_CFG__FS_S2_MASK << HII2S_FS_CFG__FS_S2_SHIFT);
|
|
val &= ~(HII2S_FS_CFG__FS_DACLR_MASK << HII2S_FS_CFG__FS_DACLR_SHIFT);
|
|
val &= ~(HII2S_FS_CFG__FS_ST_DL_R_MASK <<
|
|
HII2S_FS_CFG__FS_ST_DL_R_SHIFT);
|
|
val &= ~(HII2S_FS_CFG__FS_ST_DL_L_MASK <<
|
|
HII2S_FS_CFG__FS_ST_DL_L_SHIFT);
|
|
val |= (rate << HII2S_FS_CFG__FS_S2_SHIFT);
|
|
val |= (rate << HII2S_FS_CFG__FS_DACLR_SHIFT);
|
|
val |= (rate << HII2S_FS_CFG__FS_ST_DL_R_SHIFT);
|
|
val |= (rate << HII2S_FS_CFG__FS_ST_DL_L_SHIFT);
|
|
hi6210_write_reg(i2s, HII2S_FS_CFG, val);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int hi6210_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
|
|
struct snd_soc_dai *cpu_dai)
|
|
{
|
|
pr_debug("%s\n", __func__);
|
|
switch (cmd) {
|
|
case SNDRV_PCM_TRIGGER_START:
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
|
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
|
|
hi6210_i2s_rxctrl(cpu_dai, 1);
|
|
else
|
|
hi6210_i2s_txctrl(cpu_dai, 1);
|
|
break;
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
|
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
|
|
hi6210_i2s_rxctrl(cpu_dai, 0);
|
|
else
|
|
hi6210_i2s_txctrl(cpu_dai, 0);
|
|
break;
|
|
default:
|
|
dev_err(cpu_dai->dev, "unknown cmd\n");
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int hi6210_i2s_dai_probe(struct snd_soc_dai *dai)
|
|
{
|
|
struct hi6210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
|
|
|
|
snd_soc_dai_init_dma_data(dai,
|
|
&i2s->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
|
|
&i2s->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
static const struct snd_soc_dai_ops hi6210_i2s_dai_ops = {
|
|
.trigger = hi6210_i2s_trigger,
|
|
.hw_params = hi6210_i2s_hw_params,
|
|
.set_fmt = hi6210_i2s_set_fmt,
|
|
.startup = hi6210_i2s_startup,
|
|
.shutdown = hi6210_i2s_shutdown,
|
|
};
|
|
|
|
static const struct snd_soc_dai_driver hi6210_i2s_dai_init = {
|
|
.probe = hi6210_i2s_dai_probe,
|
|
.playback = {
|
|
.channels_min = 2,
|
|
.channels_max = 2,
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE |
|
|
SNDRV_PCM_FMTBIT_U16_LE,
|
|
.rates = SNDRV_PCM_RATE_48000,
|
|
},
|
|
.capture = {
|
|
.channels_min = 2,
|
|
.channels_max = 2,
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE |
|
|
SNDRV_PCM_FMTBIT_U16_LE,
|
|
.rates = SNDRV_PCM_RATE_48000,
|
|
},
|
|
.ops = &hi6210_i2s_dai_ops,
|
|
};
|
|
|
|
static const struct snd_soc_component_driver hi6210_i2s_i2s_comp = {
|
|
.name = "hi6210_i2s-i2s",
|
|
};
|
|
|
|
static int hi6210_i2s_probe(struct platform_device *pdev)
|
|
{
|
|
struct device_node *node = pdev->dev.of_node;
|
|
struct device *dev = &pdev->dev;
|
|
struct hi6210_i2s *i2s;
|
|
struct resource *res;
|
|
int ret;
|
|
|
|
i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
|
|
if (!i2s)
|
|
return -ENOMEM;
|
|
|
|
i2s->dev = dev;
|
|
spin_lock_init(&i2s->lock);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
i2s->base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(i2s->base))
|
|
return PTR_ERR(i2s->base);
|
|
|
|
i2s->base_phys = (phys_addr_t)res->start;
|
|
i2s->dai = hi6210_i2s_dai_init;
|
|
|
|
dev_set_drvdata(&pdev->dev, i2s);
|
|
|
|
i2s->sysctrl = syscon_regmap_lookup_by_phandle(node,
|
|
"hisilicon,sysctrl-syscon");
|
|
if (IS_ERR(i2s->sysctrl))
|
|
return PTR_ERR(i2s->sysctrl);
|
|
|
|
i2s->clk[CLK_DACODEC] = devm_clk_get(&pdev->dev, "dacodec");
|
|
if (IS_ERR_OR_NULL(i2s->clk[CLK_DACODEC]))
|
|
return PTR_ERR(i2s->clk[CLK_DACODEC]);
|
|
i2s->clocks++;
|
|
|
|
i2s->clk[CLK_I2S_BASE] = devm_clk_get(&pdev->dev, "i2s-base");
|
|
if (IS_ERR_OR_NULL(i2s->clk[CLK_I2S_BASE]))
|
|
return PTR_ERR(i2s->clk[CLK_I2S_BASE]);
|
|
i2s->clocks++;
|
|
|
|
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = devm_snd_soc_register_component(&pdev->dev, &hi6210_i2s_i2s_comp,
|
|
&i2s->dai, 1);
|
|
return ret;
|
|
}
|
|
|
|
static const struct of_device_id hi6210_i2s_dt_ids[] = {
|
|
{ .compatible = "hisilicon,hi6210-i2s" },
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, hi6210_i2s_dt_ids);
|
|
|
|
static struct platform_driver hi6210_i2s_driver = {
|
|
.probe = hi6210_i2s_probe,
|
|
.driver = {
|
|
.name = "hi6210_i2s",
|
|
.of_match_table = hi6210_i2s_dt_ids,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(hi6210_i2s_driver);
|
|
|
|
MODULE_DESCRIPTION("Hisilicon HI6210 I2S driver");
|
|
MODULE_AUTHOR("Andy Green <andy.green@linaro.org>");
|
|
MODULE_LICENSE("GPL");
|