643 строки
16 KiB
C
643 строки
16 KiB
C
/*
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* bxt-sst.c - DSP library functions for BXT platform
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*
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* Copyright (C) 2015-16 Intel Corp
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* Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
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* Jeeja KP <jeeja.kp@intel.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/firmware.h>
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#include <linux/device.h>
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#include "../common/sst-dsp.h"
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#include "../common/sst-dsp-priv.h"
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#include "skl-sst-ipc.h"
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#define BXT_BASEFW_TIMEOUT 3000
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#define BXT_INIT_TIMEOUT 300
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#define BXT_ROM_INIT_TIMEOUT 70
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#define BXT_IPC_PURGE_FW 0x01004000
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#define BXT_ROM_INIT 0x5
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#define BXT_ADSP_SRAM0_BASE 0x80000
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/* Firmware status window */
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#define BXT_ADSP_FW_STATUS BXT_ADSP_SRAM0_BASE
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#define BXT_ADSP_ERROR_CODE (BXT_ADSP_FW_STATUS + 0x4)
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#define BXT_ADSP_SRAM1_BASE 0xA0000
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#define BXT_INSTANCE_ID 0
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#define BXT_BASE_FW_MODULE_ID 0
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#define BXT_ADSP_FW_BIN_HDR_OFFSET 0x2000
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/* Delay before scheduling D0i3 entry */
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#define BXT_D0I3_DELAY 5000
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#define BXT_FW_ROM_INIT_RETRY 3
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static unsigned int bxt_get_errorcode(struct sst_dsp *ctx)
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{
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return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE);
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}
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static int
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bxt_load_library(struct sst_dsp *ctx, struct skl_lib_info *linfo, int lib_count)
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{
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struct snd_dma_buffer dmab;
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struct skl_sst *skl = ctx->thread_context;
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struct firmware stripped_fw;
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int ret = 0, i, dma_id, stream_tag;
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/* library indices start from 1 to N. 0 represents base FW */
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for (i = 1; i < lib_count; i++) {
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ret = skl_prepare_lib_load(skl, &skl->lib_info[i], &stripped_fw,
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BXT_ADSP_FW_BIN_HDR_OFFSET, i);
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if (ret < 0)
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goto load_library_failed;
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stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40,
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stripped_fw.size, &dmab);
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if (stream_tag <= 0) {
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dev_err(ctx->dev, "Lib prepare DMA err: %x\n",
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stream_tag);
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ret = stream_tag;
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goto load_library_failed;
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}
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dma_id = stream_tag - 1;
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memcpy(dmab.area, stripped_fw.data, stripped_fw.size);
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ctx->dsp_ops.trigger(ctx->dev, true, stream_tag);
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ret = skl_sst_ipc_load_library(&skl->ipc, dma_id, i, true);
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if (ret < 0)
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dev_err(ctx->dev, "IPC Load Lib for %s fail: %d\n",
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linfo[i].name, ret);
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ctx->dsp_ops.trigger(ctx->dev, false, stream_tag);
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ctx->dsp_ops.cleanup(ctx->dev, &dmab, stream_tag);
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}
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return ret;
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load_library_failed:
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skl_release_library(linfo, lib_count);
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return ret;
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}
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/*
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* First boot sequence has some extra steps. Core 0 waits for power
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* status on core 1, so power up core 1 also momentarily, keep it in
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* reset/stall and then turn it off
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*/
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static int sst_bxt_prepare_fw(struct sst_dsp *ctx,
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const void *fwdata, u32 fwsize)
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{
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int stream_tag, ret;
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stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab);
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if (stream_tag <= 0) {
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dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n",
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stream_tag);
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return stream_tag;
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}
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ctx->dsp_ops.stream_tag = stream_tag;
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memcpy(ctx->dmab.area, fwdata, fwsize);
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/* Step 1: Power up core 0 and core1 */
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ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK |
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SKL_DSP_CORE_MASK(1));
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if (ret < 0) {
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dev_err(ctx->dev, "dsp core0/1 power up failed\n");
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goto base_fw_load_failed;
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}
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/* Step 2: Purge FW request */
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sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY |
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(BXT_IPC_PURGE_FW | ((stream_tag - 1) << 9)));
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/* Step 3: Unset core0 reset state & unstall/run core0 */
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ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK);
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if (ret < 0) {
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dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret);
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ret = -EIO;
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goto base_fw_load_failed;
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}
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/* Step 4: Wait for DONE Bit */
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ret = sst_dsp_register_poll(ctx, SKL_ADSP_REG_HIPCIE,
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SKL_ADSP_REG_HIPCIE_DONE,
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SKL_ADSP_REG_HIPCIE_DONE,
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BXT_INIT_TIMEOUT, "HIPCIE Done");
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if (ret < 0) {
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dev_err(ctx->dev, "Timeout for Purge Request%d\n", ret);
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goto base_fw_load_failed;
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}
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/* Step 5: power down core1 */
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ret = skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
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if (ret < 0) {
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dev_err(ctx->dev, "dsp core1 power down failed\n");
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goto base_fw_load_failed;
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}
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/* Step 6: Enable Interrupt */
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skl_ipc_int_enable(ctx);
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skl_ipc_op_int_enable(ctx);
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/* Step 7: Wait for ROM init */
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ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK,
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SKL_FW_INIT, BXT_ROM_INIT_TIMEOUT, "ROM Load");
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if (ret < 0) {
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dev_err(ctx->dev, "Timeout for ROM init, ret:%d\n", ret);
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goto base_fw_load_failed;
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}
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return ret;
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base_fw_load_failed:
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ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag);
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skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
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skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
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return ret;
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}
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static int sst_transfer_fw_host_dma(struct sst_dsp *ctx)
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{
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int ret;
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ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag);
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ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK,
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BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot");
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ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag);
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ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag);
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return ret;
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}
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static int bxt_load_base_firmware(struct sst_dsp *ctx)
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{
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struct firmware stripped_fw;
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struct skl_sst *skl = ctx->thread_context;
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int ret, i;
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if (ctx->fw == NULL) {
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ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev);
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if (ret < 0) {
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dev_err(ctx->dev, "Request firmware failed %d\n", ret);
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return ret;
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}
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}
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/* prase uuids on first boot */
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if (skl->is_first_boot) {
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ret = snd_skl_parse_uuids(ctx, ctx->fw, BXT_ADSP_FW_BIN_HDR_OFFSET, 0);
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if (ret < 0)
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goto sst_load_base_firmware_failed;
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}
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stripped_fw.data = ctx->fw->data;
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stripped_fw.size = ctx->fw->size;
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skl_dsp_strip_extended_manifest(&stripped_fw);
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for (i = 0; i < BXT_FW_ROM_INIT_RETRY; i++) {
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ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size);
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if (ret == 0)
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break;
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}
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if (ret < 0) {
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dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
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sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
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sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
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dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret);
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goto sst_load_base_firmware_failed;
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}
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ret = sst_transfer_fw_host_dma(ctx);
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if (ret < 0) {
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dev_err(ctx->dev, "Transfer firmware failed %d\n", ret);
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dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
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sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
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sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
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skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
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} else {
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dev_dbg(ctx->dev, "Firmware download successful\n");
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ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
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msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
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if (ret == 0) {
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dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n");
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skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
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ret = -EIO;
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} else {
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ret = 0;
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skl->fw_loaded = true;
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}
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}
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return ret;
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sst_load_base_firmware_failed:
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release_firmware(ctx->fw);
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ctx->fw = NULL;
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return ret;
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}
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/*
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* Decide the D0i3 state that can be targeted based on the usecase
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* ref counts and DSP state
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*
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* Decision Matrix: (X= dont care; state = target state)
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*
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* DSP state != SKL_DSP_RUNNING ; state = no d0i3
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*
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* DSP state == SKL_DSP_RUNNING , the following matrix applies
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* non_d0i3 >0; streaming =X; non_streaming =X; state = no d0i3
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* non_d0i3 =X; streaming =0; non_streaming =0; state = no d0i3
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* non_d0i3 =0; streaming >0; non_streaming =X; state = streaming d0i3
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* non_d0i3 =0; streaming =0; non_streaming =X; state = non-streaming d0i3
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*/
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static int bxt_d0i3_target_state(struct sst_dsp *ctx)
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{
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struct skl_sst *skl = ctx->thread_context;
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struct skl_d0i3_data *d0i3 = &skl->d0i3;
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if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING)
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return SKL_DSP_D0I3_NONE;
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if (d0i3->non_d0i3)
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return SKL_DSP_D0I3_NONE;
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else if (d0i3->streaming)
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return SKL_DSP_D0I3_STREAMING;
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else if (d0i3->non_streaming)
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return SKL_DSP_D0I3_NON_STREAMING;
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else
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return SKL_DSP_D0I3_NONE;
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}
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static void bxt_set_dsp_D0i3(struct work_struct *work)
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{
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int ret;
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struct skl_ipc_d0ix_msg msg;
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struct skl_sst *skl = container_of(work,
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struct skl_sst, d0i3.work.work);
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struct sst_dsp *ctx = skl->dsp;
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struct skl_d0i3_data *d0i3 = &skl->d0i3;
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int target_state;
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dev_dbg(ctx->dev, "In %s:\n", __func__);
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/* D0i3 entry allowed only if core 0 alone is running */
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if (skl_dsp_get_enabled_cores(ctx) != SKL_DSP_CORE0_MASK) {
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dev_warn(ctx->dev,
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"D0i3 allowed when only core0 running:Exit\n");
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return;
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}
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target_state = bxt_d0i3_target_state(ctx);
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if (target_state == SKL_DSP_D0I3_NONE)
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return;
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msg.instance_id = 0;
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msg.module_id = 0;
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msg.wake = 1;
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msg.streaming = 0;
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if (target_state == SKL_DSP_D0I3_STREAMING)
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msg.streaming = 1;
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ret = skl_ipc_set_d0ix(&skl->ipc, &msg);
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if (ret < 0) {
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dev_err(ctx->dev, "Failed to set DSP to D0i3 state\n");
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return;
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}
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/* Set Vendor specific register D0I3C.I3 to enable D0i3*/
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if (skl->update_d0i3c)
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skl->update_d0i3c(skl->dev, true);
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d0i3->state = target_state;
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skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING_D0I3;
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}
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static int bxt_schedule_dsp_D0i3(struct sst_dsp *ctx)
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{
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struct skl_sst *skl = ctx->thread_context;
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struct skl_d0i3_data *d0i3 = &skl->d0i3;
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/* Schedule D0i3 only if the usecase ref counts are appropriate */
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if (bxt_d0i3_target_state(ctx) != SKL_DSP_D0I3_NONE) {
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dev_dbg(ctx->dev, "%s: Schedule D0i3\n", __func__);
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schedule_delayed_work(&d0i3->work,
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msecs_to_jiffies(BXT_D0I3_DELAY));
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}
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return 0;
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}
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static int bxt_set_dsp_D0i0(struct sst_dsp *ctx)
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{
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int ret;
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struct skl_ipc_d0ix_msg msg;
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struct skl_sst *skl = ctx->thread_context;
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dev_dbg(ctx->dev, "In %s:\n", __func__);
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/* First Cancel any pending attempt to put DSP to D0i3 */
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cancel_delayed_work_sync(&skl->d0i3.work);
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/* If DSP is currently in D0i3, bring it to D0i0 */
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if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING_D0I3)
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return 0;
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dev_dbg(ctx->dev, "Set DSP to D0i0\n");
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msg.instance_id = 0;
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msg.module_id = 0;
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msg.streaming = 0;
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msg.wake = 0;
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if (skl->d0i3.state == SKL_DSP_D0I3_STREAMING)
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msg.streaming = 1;
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/* Clear Vendor specific register D0I3C.I3 to disable D0i3*/
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if (skl->update_d0i3c)
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skl->update_d0i3c(skl->dev, false);
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ret = skl_ipc_set_d0ix(&skl->ipc, &msg);
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if (ret < 0) {
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dev_err(ctx->dev, "Failed to set DSP to D0i0\n");
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return ret;
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}
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skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING;
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skl->d0i3.state = SKL_DSP_D0I3_NONE;
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return 0;
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}
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static int bxt_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id)
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{
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struct skl_sst *skl = ctx->thread_context;
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int ret;
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struct skl_ipc_dxstate_info dx;
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unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
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if (skl->fw_loaded == false) {
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skl->boot_complete = false;
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ret = bxt_load_base_firmware(ctx);
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if (ret < 0) {
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dev_err(ctx->dev, "reload fw failed: %d\n", ret);
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return ret;
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}
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if (skl->lib_count > 1) {
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ret = bxt_load_library(ctx, skl->lib_info,
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skl->lib_count);
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if (ret < 0) {
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dev_err(ctx->dev, "reload libs failed: %d\n", ret);
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return ret;
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}
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}
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skl->cores.state[core_id] = SKL_DSP_RUNNING;
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return ret;
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}
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/* If core 0 is being turned on, turn on core 1 as well */
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if (core_id == SKL_DSP_CORE0_ID)
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ret = skl_dsp_core_power_up(ctx, core_mask |
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SKL_DSP_CORE_MASK(1));
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else
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ret = skl_dsp_core_power_up(ctx, core_mask);
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if (ret < 0)
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goto err;
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if (core_id == SKL_DSP_CORE0_ID) {
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/*
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* Enable interrupt after SPA is set and before
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* DSP is unstalled
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*/
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skl_ipc_int_enable(ctx);
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skl_ipc_op_int_enable(ctx);
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skl->boot_complete = false;
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}
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ret = skl_dsp_start_core(ctx, core_mask);
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if (ret < 0)
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goto err;
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if (core_id == SKL_DSP_CORE0_ID) {
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ret = wait_event_timeout(skl->boot_wait,
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skl->boot_complete,
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msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
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/* If core 1 was turned on for booting core 0, turn it off */
|
|
skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
|
|
if (ret == 0) {
|
|
dev_err(ctx->dev, "%s: DSP boot timeout\n", __func__);
|
|
dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
|
|
sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
|
|
sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
|
|
dev_err(ctx->dev, "Failed to set core0 to D0 state\n");
|
|
ret = -EIO;
|
|
goto err;
|
|
}
|
|
}
|
|
|
|
/* Tell FW if additional core in now On */
|
|
|
|
if (core_id != SKL_DSP_CORE0_ID) {
|
|
dx.core_mask = core_mask;
|
|
dx.dx_mask = core_mask;
|
|
|
|
ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID,
|
|
BXT_BASE_FW_MODULE_ID, &dx);
|
|
if (ret < 0) {
|
|
dev_err(ctx->dev, "IPC set_dx for core %d fail: %d\n",
|
|
core_id, ret);
|
|
goto err;
|
|
}
|
|
}
|
|
|
|
skl->cores.state[core_id] = SKL_DSP_RUNNING;
|
|
return 0;
|
|
err:
|
|
if (core_id == SKL_DSP_CORE0_ID)
|
|
core_mask |= SKL_DSP_CORE_MASK(1);
|
|
skl_dsp_disable_core(ctx, core_mask);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int bxt_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id)
|
|
{
|
|
int ret;
|
|
struct skl_ipc_dxstate_info dx;
|
|
struct skl_sst *skl = ctx->thread_context;
|
|
unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
|
|
|
|
dx.core_mask = core_mask;
|
|
dx.dx_mask = SKL_IPC_D3_MASK;
|
|
|
|
dev_dbg(ctx->dev, "core mask=%x dx_mask=%x\n",
|
|
dx.core_mask, dx.dx_mask);
|
|
|
|
ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID,
|
|
BXT_BASE_FW_MODULE_ID, &dx);
|
|
if (ret < 0) {
|
|
dev_err(ctx->dev,
|
|
"Failed to set DSP to D3:core id = %d;Continue reset\n",
|
|
core_id);
|
|
/*
|
|
* In case of D3 failure, re-download the firmware, so set
|
|
* fw_loaded to false.
|
|
*/
|
|
skl->fw_loaded = false;
|
|
}
|
|
|
|
if (core_id == SKL_DSP_CORE0_ID) {
|
|
/* disable Interrupt */
|
|
skl_ipc_op_int_disable(ctx);
|
|
skl_ipc_int_disable(ctx);
|
|
}
|
|
ret = skl_dsp_disable_core(ctx, core_mask);
|
|
if (ret < 0) {
|
|
dev_err(ctx->dev, "Failed to disable core %d\n", ret);
|
|
return ret;
|
|
}
|
|
skl->cores.state[core_id] = SKL_DSP_RESET;
|
|
return 0;
|
|
}
|
|
|
|
static const struct skl_dsp_fw_ops bxt_fw_ops = {
|
|
.set_state_D0 = bxt_set_dsp_D0,
|
|
.set_state_D3 = bxt_set_dsp_D3,
|
|
.set_state_D0i3 = bxt_schedule_dsp_D0i3,
|
|
.set_state_D0i0 = bxt_set_dsp_D0i0,
|
|
.load_fw = bxt_load_base_firmware,
|
|
.get_fw_errcode = bxt_get_errorcode,
|
|
.load_library = bxt_load_library,
|
|
};
|
|
|
|
static struct sst_ops skl_ops = {
|
|
.irq_handler = skl_dsp_sst_interrupt,
|
|
.write = sst_shim32_write,
|
|
.read = sst_shim32_read,
|
|
.ram_read = sst_memcpy_fromio_32,
|
|
.ram_write = sst_memcpy_toio_32,
|
|
.free = skl_dsp_free,
|
|
};
|
|
|
|
static struct sst_dsp_device skl_dev = {
|
|
.thread = skl_dsp_irq_thread_handler,
|
|
.ops = &skl_ops,
|
|
};
|
|
|
|
int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
|
|
const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
|
|
struct skl_sst **dsp)
|
|
{
|
|
struct skl_sst *skl;
|
|
struct sst_dsp *sst;
|
|
int ret;
|
|
|
|
ret = skl_sst_ctx_init(dev, irq, fw_name, dsp_ops, dsp, &skl_dev);
|
|
if (ret < 0) {
|
|
dev_err(dev, "%s: no device\n", __func__);
|
|
return ret;
|
|
}
|
|
|
|
skl = *dsp;
|
|
sst = skl->dsp;
|
|
sst->fw_ops = bxt_fw_ops;
|
|
sst->addr.lpe = mmio_base;
|
|
sst->addr.shim = mmio_base;
|
|
sst->addr.sram0_base = BXT_ADSP_SRAM0_BASE;
|
|
sst->addr.sram1_base = BXT_ADSP_SRAM1_BASE;
|
|
sst->addr.w0_stat_sz = SKL_ADSP_W0_STAT_SZ;
|
|
sst->addr.w0_up_sz = SKL_ADSP_W0_UP_SZ;
|
|
|
|
sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ),
|
|
SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ);
|
|
|
|
ret = skl_ipc_init(dev, skl);
|
|
if (ret) {
|
|
skl_dsp_free(sst);
|
|
return ret;
|
|
}
|
|
|
|
/* set the D0i3 check */
|
|
skl->ipc.ops.check_dsp_lp_on = skl_ipc_check_D0i0;
|
|
|
|
skl->boot_complete = false;
|
|
init_waitqueue_head(&skl->boot_wait);
|
|
INIT_DELAYED_WORK(&skl->d0i3.work, bxt_set_dsp_D0i3);
|
|
skl->d0i3.state = SKL_DSP_D0I3_NONE;
|
|
|
|
return skl_dsp_acquire_irq(sst);
|
|
}
|
|
EXPORT_SYMBOL_GPL(bxt_sst_dsp_init);
|
|
|
|
int bxt_sst_init_fw(struct device *dev, struct skl_sst *ctx)
|
|
{
|
|
int ret;
|
|
struct sst_dsp *sst = ctx->dsp;
|
|
|
|
ret = sst->fw_ops.load_fw(sst);
|
|
if (ret < 0) {
|
|
dev_err(dev, "Load base fw failed: %x\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
skl_dsp_init_core_state(sst);
|
|
|
|
if (ctx->lib_count > 1) {
|
|
ret = sst->fw_ops.load_library(sst, ctx->lib_info,
|
|
ctx->lib_count);
|
|
if (ret < 0) {
|
|
dev_err(dev, "Load Library failed : %x\n", ret);
|
|
return ret;
|
|
}
|
|
}
|
|
ctx->is_first_boot = false;
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(bxt_sst_init_fw);
|
|
|
|
void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx)
|
|
{
|
|
|
|
skl_release_library(ctx->lib_info, ctx->lib_count);
|
|
if (ctx->dsp->fw)
|
|
release_firmware(ctx->dsp->fw);
|
|
skl_freeup_uuid_list(ctx);
|
|
skl_ipc_free(&ctx->ipc);
|
|
ctx->dsp->ops->free(ctx->dsp);
|
|
}
|
|
EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("Intel Broxton IPC driver");
|