498 строки
12 KiB
C
498 строки
12 KiB
C
/*
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* cnl-sst.c - DSP library functions for CNL platform
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*
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* Copyright (C) 2016-17, Intel Corporation.
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*
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* Author: Guneshwor Singh <guneshwor.o.singh@intel.com>
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*
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* Modified from:
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* HDA DSP library functions for SKL platform
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* Copyright (C) 2014-15, Intel Corporation.
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*
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/firmware.h>
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#include <linux/device.h>
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#include "../common/sst-dsp.h"
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#include "../common/sst-dsp-priv.h"
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#include "../common/sst-ipc.h"
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#include "cnl-sst-dsp.h"
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#include "skl-sst-dsp.h"
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#include "skl-sst-ipc.h"
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#define CNL_FW_ROM_INIT 0x1
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#define CNL_FW_INIT 0x5
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#define CNL_IPC_PURGE 0x01004000
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#define CNL_INIT_TIMEOUT 300
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#define CNL_BASEFW_TIMEOUT 3000
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#define CNL_ADSP_SRAM0_BASE 0x80000
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/* Firmware status window */
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#define CNL_ADSP_FW_STATUS CNL_ADSP_SRAM0_BASE
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#define CNL_ADSP_ERROR_CODE (CNL_ADSP_FW_STATUS + 0x4)
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#define CNL_INSTANCE_ID 0
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#define CNL_BASE_FW_MODULE_ID 0
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#define CNL_ADSP_FW_HDR_OFFSET 0x2000
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#define CNL_ROM_CTRL_DMA_ID 0x9
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static int cnl_prepare_fw(struct sst_dsp *ctx, const void *fwdata, u32 fwsize)
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{
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int ret, stream_tag;
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stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab);
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if (stream_tag <= 0) {
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dev_err(ctx->dev, "dma prepare failed: 0%#x\n", stream_tag);
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return stream_tag;
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}
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ctx->dsp_ops.stream_tag = stream_tag;
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memcpy(ctx->dmab.area, fwdata, fwsize);
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/* purge FW request */
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sst_dsp_shim_write(ctx, CNL_ADSP_REG_HIPCIDR,
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CNL_ADSP_REG_HIPCIDR_BUSY | (CNL_IPC_PURGE |
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((stream_tag - 1) << CNL_ROM_CTRL_DMA_ID)));
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ret = cnl_dsp_enable_core(ctx, SKL_DSP_CORE0_MASK);
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if (ret < 0) {
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dev_err(ctx->dev, "dsp boot core failed ret: %d\n", ret);
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ret = -EIO;
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goto base_fw_load_failed;
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}
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/* enable interrupt */
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cnl_ipc_int_enable(ctx);
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cnl_ipc_op_int_enable(ctx);
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ret = sst_dsp_register_poll(ctx, CNL_ADSP_FW_STATUS, CNL_FW_STS_MASK,
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CNL_FW_ROM_INIT, CNL_INIT_TIMEOUT,
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"rom load");
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if (ret < 0) {
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dev_err(ctx->dev, "rom init timeout, ret: %d\n", ret);
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goto base_fw_load_failed;
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}
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return 0;
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base_fw_load_failed:
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ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag);
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cnl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
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return ret;
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}
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static int sst_transfer_fw_host_dma(struct sst_dsp *ctx)
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{
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int ret;
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ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag);
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ret = sst_dsp_register_poll(ctx, CNL_ADSP_FW_STATUS, CNL_FW_STS_MASK,
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CNL_FW_INIT, CNL_BASEFW_TIMEOUT,
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"firmware boot");
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ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag);
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ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag);
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return ret;
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}
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static int cnl_load_base_firmware(struct sst_dsp *ctx)
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{
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struct firmware stripped_fw;
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struct skl_sst *cnl = ctx->thread_context;
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int ret;
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if (!ctx->fw) {
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ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev);
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if (ret < 0) {
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dev_err(ctx->dev, "request firmware failed: %d\n", ret);
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goto cnl_load_base_firmware_failed;
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}
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}
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/* parse uuids if first boot */
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if (cnl->is_first_boot) {
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ret = snd_skl_parse_uuids(ctx, ctx->fw,
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CNL_ADSP_FW_HDR_OFFSET, 0);
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if (ret < 0)
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goto cnl_load_base_firmware_failed;
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}
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stripped_fw.data = ctx->fw->data;
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stripped_fw.size = ctx->fw->size;
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skl_dsp_strip_extended_manifest(&stripped_fw);
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ret = cnl_prepare_fw(ctx, stripped_fw.data, stripped_fw.size);
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if (ret < 0) {
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dev_err(ctx->dev, "prepare firmware failed: %d\n", ret);
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goto cnl_load_base_firmware_failed;
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}
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ret = sst_transfer_fw_host_dma(ctx);
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if (ret < 0) {
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dev_err(ctx->dev, "transfer firmware failed: %d\n", ret);
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cnl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
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goto cnl_load_base_firmware_failed;
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}
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ret = wait_event_timeout(cnl->boot_wait, cnl->boot_complete,
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msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
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if (ret == 0) {
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dev_err(ctx->dev, "FW ready timed-out\n");
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cnl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
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ret = -EIO;
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goto cnl_load_base_firmware_failed;
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}
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cnl->fw_loaded = true;
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return 0;
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cnl_load_base_firmware_failed:
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release_firmware(ctx->fw);
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ctx->fw = NULL;
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return ret;
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}
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static int cnl_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id)
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{
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struct skl_sst *cnl = ctx->thread_context;
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unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
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struct skl_ipc_dxstate_info dx;
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int ret;
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if (!cnl->fw_loaded) {
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cnl->boot_complete = false;
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ret = cnl_load_base_firmware(ctx);
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if (ret < 0) {
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dev_err(ctx->dev, "fw reload failed: %d\n", ret);
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return ret;
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}
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cnl->cores.state[core_id] = SKL_DSP_RUNNING;
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return ret;
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}
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ret = cnl_dsp_enable_core(ctx, core_mask);
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if (ret < 0) {
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dev_err(ctx->dev, "enable dsp core %d failed: %d\n",
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core_id, ret);
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goto err;
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}
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if (core_id == SKL_DSP_CORE0_ID) {
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/* enable interrupt */
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cnl_ipc_int_enable(ctx);
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cnl_ipc_op_int_enable(ctx);
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cnl->boot_complete = false;
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ret = wait_event_timeout(cnl->boot_wait, cnl->boot_complete,
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msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
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if (ret == 0) {
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dev_err(ctx->dev,
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"dsp boot timeout, status=%#x error=%#x\n",
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sst_dsp_shim_read(ctx, CNL_ADSP_FW_STATUS),
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sst_dsp_shim_read(ctx, CNL_ADSP_ERROR_CODE));
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goto err;
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}
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} else {
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dx.core_mask = core_mask;
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dx.dx_mask = core_mask;
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ret = skl_ipc_set_dx(&cnl->ipc, CNL_INSTANCE_ID,
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CNL_BASE_FW_MODULE_ID, &dx);
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if (ret < 0) {
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dev_err(ctx->dev, "set_dx failed, core: %d ret: %d\n",
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core_id, ret);
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goto err;
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}
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}
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cnl->cores.state[core_id] = SKL_DSP_RUNNING;
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return 0;
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err:
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cnl_dsp_disable_core(ctx, core_mask);
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return ret;
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}
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static int cnl_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id)
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{
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struct skl_sst *cnl = ctx->thread_context;
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unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
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struct skl_ipc_dxstate_info dx;
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int ret;
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dx.core_mask = core_mask;
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dx.dx_mask = SKL_IPC_D3_MASK;
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ret = skl_ipc_set_dx(&cnl->ipc, CNL_INSTANCE_ID,
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CNL_BASE_FW_MODULE_ID, &dx);
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if (ret < 0) {
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dev_err(ctx->dev,
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"dsp core %d to d3 failed; continue reset\n",
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core_id);
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cnl->fw_loaded = false;
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}
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/* disable interrupts if core 0 */
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if (core_id == SKL_DSP_CORE0_ID) {
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skl_ipc_op_int_disable(ctx);
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skl_ipc_int_disable(ctx);
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}
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ret = cnl_dsp_disable_core(ctx, core_mask);
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if (ret < 0) {
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dev_err(ctx->dev, "disable dsp core %d failed: %d\n",
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core_id, ret);
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return ret;
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}
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cnl->cores.state[core_id] = SKL_DSP_RESET;
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return ret;
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}
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static unsigned int cnl_get_errno(struct sst_dsp *ctx)
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{
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return sst_dsp_shim_read(ctx, CNL_ADSP_ERROR_CODE);
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}
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static const struct skl_dsp_fw_ops cnl_fw_ops = {
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.set_state_D0 = cnl_set_dsp_D0,
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.set_state_D3 = cnl_set_dsp_D3,
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.load_fw = cnl_load_base_firmware,
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.get_fw_errcode = cnl_get_errno,
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};
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static struct sst_ops cnl_ops = {
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.irq_handler = cnl_dsp_sst_interrupt,
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.write = sst_shim32_write,
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.read = sst_shim32_read,
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.ram_read = sst_memcpy_fromio_32,
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.ram_write = sst_memcpy_toio_32,
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.free = cnl_dsp_free,
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};
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#define CNL_IPC_GLB_NOTIFY_RSP_SHIFT 29
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#define CNL_IPC_GLB_NOTIFY_RSP_MASK 0x1
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#define CNL_IPC_GLB_NOTIFY_RSP_TYPE(x) (((x) >> CNL_IPC_GLB_NOTIFY_RSP_SHIFT) \
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& CNL_IPC_GLB_NOTIFY_RSP_MASK)
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static irqreturn_t cnl_dsp_irq_thread_handler(int irq, void *context)
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{
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struct sst_dsp *dsp = context;
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struct skl_sst *cnl = sst_dsp_get_thread_context(dsp);
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struct sst_generic_ipc *ipc = &cnl->ipc;
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struct skl_ipc_header header = {0};
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u32 hipcida, hipctdr, hipctdd;
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int ipc_irq = 0;
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/* here we handle ipc interrupts only */
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if (!(dsp->intr_status & CNL_ADSPIS_IPC))
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return IRQ_NONE;
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hipcida = sst_dsp_shim_read_unlocked(dsp, CNL_ADSP_REG_HIPCIDA);
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hipctdr = sst_dsp_shim_read_unlocked(dsp, CNL_ADSP_REG_HIPCTDR);
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/* reply message from dsp */
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if (hipcida & CNL_ADSP_REG_HIPCIDA_DONE) {
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sst_dsp_shim_update_bits(dsp, CNL_ADSP_REG_HIPCCTL,
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CNL_ADSP_REG_HIPCCTL_DONE, 0);
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/* clear done bit - tell dsp operation is complete */
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sst_dsp_shim_update_bits_forced(dsp, CNL_ADSP_REG_HIPCIDA,
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CNL_ADSP_REG_HIPCIDA_DONE, CNL_ADSP_REG_HIPCIDA_DONE);
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ipc_irq = 1;
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/* unmask done interrupt */
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sst_dsp_shim_update_bits(dsp, CNL_ADSP_REG_HIPCCTL,
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CNL_ADSP_REG_HIPCCTL_DONE, CNL_ADSP_REG_HIPCCTL_DONE);
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}
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/* new message from dsp */
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if (hipctdr & CNL_ADSP_REG_HIPCTDR_BUSY) {
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hipctdd = sst_dsp_shim_read_unlocked(dsp, CNL_ADSP_REG_HIPCTDD);
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header.primary = hipctdr;
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header.extension = hipctdd;
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dev_dbg(dsp->dev, "IPC irq: Firmware respond primary:%x",
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header.primary);
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dev_dbg(dsp->dev, "IPC irq: Firmware respond extension:%x",
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header.extension);
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if (CNL_IPC_GLB_NOTIFY_RSP_TYPE(header.primary)) {
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/* Handle Immediate reply from DSP Core */
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skl_ipc_process_reply(ipc, header);
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} else {
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dev_dbg(dsp->dev, "IPC irq: Notification from firmware\n");
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skl_ipc_process_notification(ipc, header);
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}
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/* clear busy interrupt */
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sst_dsp_shim_update_bits_forced(dsp, CNL_ADSP_REG_HIPCTDR,
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CNL_ADSP_REG_HIPCTDR_BUSY, CNL_ADSP_REG_HIPCTDR_BUSY);
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/* set done bit to ack dsp */
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sst_dsp_shim_update_bits_forced(dsp, CNL_ADSP_REG_HIPCTDA,
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CNL_ADSP_REG_HIPCTDA_DONE, CNL_ADSP_REG_HIPCTDA_DONE);
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ipc_irq = 1;
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}
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if (ipc_irq == 0)
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return IRQ_NONE;
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cnl_ipc_int_enable(dsp);
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/* continue to send any remaining messages */
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schedule_work(&ipc->kwork);
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return IRQ_HANDLED;
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}
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static struct sst_dsp_device cnl_dev = {
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.thread = cnl_dsp_irq_thread_handler,
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.ops = &cnl_ops,
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};
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static void cnl_ipc_tx_msg(struct sst_generic_ipc *ipc, struct ipc_message *msg)
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{
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struct skl_ipc_header *header = (struct skl_ipc_header *)(&msg->header);
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if (msg->tx_size)
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sst_dsp_outbox_write(ipc->dsp, msg->tx_data, msg->tx_size);
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sst_dsp_shim_write_unlocked(ipc->dsp, CNL_ADSP_REG_HIPCIDD,
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header->extension);
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sst_dsp_shim_write_unlocked(ipc->dsp, CNL_ADSP_REG_HIPCIDR,
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header->primary | CNL_ADSP_REG_HIPCIDR_BUSY);
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}
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static bool cnl_ipc_is_dsp_busy(struct sst_dsp *dsp)
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{
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u32 hipcidr;
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hipcidr = sst_dsp_shim_read_unlocked(dsp, CNL_ADSP_REG_HIPCIDR);
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return (hipcidr & CNL_ADSP_REG_HIPCIDR_BUSY);
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}
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static int cnl_ipc_init(struct device *dev, struct skl_sst *cnl)
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{
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struct sst_generic_ipc *ipc;
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int err;
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ipc = &cnl->ipc;
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ipc->dsp = cnl->dsp;
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ipc->dev = dev;
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ipc->tx_data_max_size = CNL_ADSP_W1_SZ;
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ipc->rx_data_max_size = CNL_ADSP_W0_UP_SZ;
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err = sst_ipc_init(ipc);
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if (err)
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return err;
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/*
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* overriding tx_msg and is_dsp_busy since
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* ipc registers are different for cnl
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*/
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ipc->ops.tx_msg = cnl_ipc_tx_msg;
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ipc->ops.tx_data_copy = skl_ipc_tx_data_copy;
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ipc->ops.is_dsp_busy = cnl_ipc_is_dsp_busy;
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return 0;
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}
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int cnl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
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const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
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struct skl_sst **dsp)
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{
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struct skl_sst *cnl;
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struct sst_dsp *sst;
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int ret;
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ret = skl_sst_ctx_init(dev, irq, fw_name, dsp_ops, dsp, &cnl_dev);
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if (ret < 0) {
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dev_err(dev, "%s: no device\n", __func__);
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return ret;
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}
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cnl = *dsp;
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sst = cnl->dsp;
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sst->fw_ops = cnl_fw_ops;
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sst->addr.lpe = mmio_base;
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sst->addr.shim = mmio_base;
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sst->addr.sram0_base = CNL_ADSP_SRAM0_BASE;
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sst->addr.sram1_base = CNL_ADSP_SRAM1_BASE;
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sst->addr.w0_stat_sz = CNL_ADSP_W0_STAT_SZ;
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sst->addr.w0_up_sz = CNL_ADSP_W0_UP_SZ;
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sst_dsp_mailbox_init(sst, (CNL_ADSP_SRAM0_BASE + CNL_ADSP_W0_STAT_SZ),
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CNL_ADSP_W0_UP_SZ, CNL_ADSP_SRAM1_BASE,
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CNL_ADSP_W1_SZ);
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ret = cnl_ipc_init(dev, cnl);
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if (ret) {
|
|
skl_dsp_free(sst);
|
|
return ret;
|
|
}
|
|
|
|
cnl->boot_complete = false;
|
|
init_waitqueue_head(&cnl->boot_wait);
|
|
|
|
return skl_dsp_acquire_irq(sst);
|
|
}
|
|
EXPORT_SYMBOL_GPL(cnl_sst_dsp_init);
|
|
|
|
int cnl_sst_init_fw(struct device *dev, struct skl_sst *ctx)
|
|
{
|
|
int ret;
|
|
struct sst_dsp *sst = ctx->dsp;
|
|
|
|
ret = ctx->dsp->fw_ops.load_fw(sst);
|
|
if (ret < 0) {
|
|
dev_err(dev, "load base fw failed: %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
skl_dsp_init_core_state(sst);
|
|
|
|
ctx->is_first_boot = false;
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(cnl_sst_init_fw);
|
|
|
|
void cnl_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx)
|
|
{
|
|
if (ctx->dsp->fw)
|
|
release_firmware(ctx->dsp->fw);
|
|
|
|
skl_freeup_uuid_list(ctx);
|
|
cnl_ipc_free(&ctx->ipc);
|
|
|
|
ctx->dsp->ops->free(ctx->dsp);
|
|
}
|
|
EXPORT_SYMBOL_GPL(cnl_sst_dsp_cleanup);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("Intel Cannonlake IPC driver");
|