499 строки
12 KiB
C
499 строки
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2011 NXP Semiconductors
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*
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* Code portions referenced from the i2x-pxa and i2c-pnx drivers
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*
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* Make SMBus byte and word transactions work on LPC178x/7x
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* Copyright (c) 2012
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* Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
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* Anton Protopopov, Emcraft Systems, antonp@emcraft.com
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*
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* Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
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*/
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#include <linux/clk.h>
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#include <linux/errno.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/time.h>
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/* LPC24xx register offsets and bits */
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#define LPC24XX_I2CONSET 0x00
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#define LPC24XX_I2STAT 0x04
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#define LPC24XX_I2DAT 0x08
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#define LPC24XX_I2ADDR 0x0c
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#define LPC24XX_I2SCLH 0x10
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#define LPC24XX_I2SCLL 0x14
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#define LPC24XX_I2CONCLR 0x18
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#define LPC24XX_AA BIT(2)
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#define LPC24XX_SI BIT(3)
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#define LPC24XX_STO BIT(4)
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#define LPC24XX_STA BIT(5)
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#define LPC24XX_I2EN BIT(6)
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#define LPC24XX_STO_AA (LPC24XX_STO | LPC24XX_AA)
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#define LPC24XX_CLEAR_ALL (LPC24XX_AA | LPC24XX_SI | LPC24XX_STO | \
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LPC24XX_STA | LPC24XX_I2EN)
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/* I2C SCL clock has different duty cycle depending on mode */
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#define I2C_STD_MODE_DUTY 46
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#define I2C_FAST_MODE_DUTY 36
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#define I2C_FAST_MODE_PLUS_DUTY 38
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/*
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* 26 possible I2C status codes, but codes applicable only
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* to master are listed here and used in this driver
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*/
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enum {
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M_BUS_ERROR = 0x00,
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M_START = 0x08,
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M_REPSTART = 0x10,
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MX_ADDR_W_ACK = 0x18,
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MX_ADDR_W_NACK = 0x20,
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MX_DATA_W_ACK = 0x28,
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MX_DATA_W_NACK = 0x30,
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M_DATA_ARB_LOST = 0x38,
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MR_ADDR_R_ACK = 0x40,
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MR_ADDR_R_NACK = 0x48,
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MR_DATA_R_ACK = 0x50,
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MR_DATA_R_NACK = 0x58,
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M_I2C_IDLE = 0xf8,
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};
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struct lpc2k_i2c {
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void __iomem *base;
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struct clk *clk;
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int irq;
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wait_queue_head_t wait;
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struct i2c_adapter adap;
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struct i2c_msg *msg;
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int msg_idx;
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int msg_status;
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int is_last;
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};
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static void i2c_lpc2k_reset(struct lpc2k_i2c *i2c)
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{
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/* Will force clear all statuses */
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writel(LPC24XX_CLEAR_ALL, i2c->base + LPC24XX_I2CONCLR);
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writel(0, i2c->base + LPC24XX_I2ADDR);
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writel(LPC24XX_I2EN, i2c->base + LPC24XX_I2CONSET);
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}
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static int i2c_lpc2k_clear_arb(struct lpc2k_i2c *i2c)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(1000);
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/*
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* If the transfer needs to abort for some reason, we'll try to
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* force a stop condition to clear any pending bus conditions
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*/
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writel(LPC24XX_STO, i2c->base + LPC24XX_I2CONSET);
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/* Wait for status change */
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while (readl(i2c->base + LPC24XX_I2STAT) != M_I2C_IDLE) {
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if (time_after(jiffies, timeout)) {
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/* Bus was not idle, try to reset adapter */
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i2c_lpc2k_reset(i2c);
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return -EBUSY;
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}
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cpu_relax();
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}
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return 0;
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}
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static void i2c_lpc2k_pump_msg(struct lpc2k_i2c *i2c)
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{
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unsigned char data;
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u32 status;
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/*
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* I2C in the LPC2xxx series is basically a state machine.
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* Just run through the steps based on the current status.
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*/
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status = readl(i2c->base + LPC24XX_I2STAT);
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switch (status) {
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case M_START:
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case M_REPSTART:
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/* Start bit was just sent out, send out addr and dir */
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data = i2c_8bit_addr_from_msg(i2c->msg);
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writel(data, i2c->base + LPC24XX_I2DAT);
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writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR);
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break;
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case MX_ADDR_W_ACK:
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case MX_DATA_W_ACK:
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/*
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* Address or data was sent out with an ACK. If there is more
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* data to send, send it now
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*/
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if (i2c->msg_idx < i2c->msg->len) {
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writel(i2c->msg->buf[i2c->msg_idx],
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i2c->base + LPC24XX_I2DAT);
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} else if (i2c->is_last) {
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/* Last message, send stop */
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writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET);
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writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
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i2c->msg_status = 0;
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disable_irq_nosync(i2c->irq);
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} else {
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i2c->msg_status = 0;
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disable_irq_nosync(i2c->irq);
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}
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i2c->msg_idx++;
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break;
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case MR_ADDR_R_ACK:
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/* Receive first byte from slave */
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if (i2c->msg->len == 1) {
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/* Last byte, return NACK */
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writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONCLR);
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} else {
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/* Not last byte, return ACK */
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writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONSET);
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}
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writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR);
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break;
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case MR_DATA_R_NACK:
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/*
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* The I2C shows NACK status on reads, so we need to accept
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* the NACK as an ACK here. This should be ok, as the real
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* BACK would of been caught on the address write.
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*/
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case MR_DATA_R_ACK:
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/* Data was received */
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if (i2c->msg_idx < i2c->msg->len) {
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i2c->msg->buf[i2c->msg_idx] =
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readl(i2c->base + LPC24XX_I2DAT);
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}
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/* If transfer is done, send STOP */
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if (i2c->msg_idx >= i2c->msg->len - 1 && i2c->is_last) {
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writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET);
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writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
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i2c->msg_status = 0;
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}
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/* Message is done */
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if (i2c->msg_idx >= i2c->msg->len - 1) {
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i2c->msg_status = 0;
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disable_irq_nosync(i2c->irq);
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}
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/*
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* One pre-last data input, send NACK to tell the slave that
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* this is going to be the last data byte to be transferred.
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*/
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if (i2c->msg_idx >= i2c->msg->len - 2) {
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/* One byte left to receive - NACK */
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writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONCLR);
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} else {
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/* More than one byte left to receive - ACK */
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writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONSET);
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}
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writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR);
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i2c->msg_idx++;
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break;
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case MX_ADDR_W_NACK:
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case MX_DATA_W_NACK:
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case MR_ADDR_R_NACK:
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/* NACK processing is done */
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writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET);
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i2c->msg_status = -ENXIO;
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disable_irq_nosync(i2c->irq);
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break;
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case M_DATA_ARB_LOST:
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/* Arbitration lost */
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i2c->msg_status = -EAGAIN;
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/* Release the I2C bus */
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writel(LPC24XX_STA | LPC24XX_STO, i2c->base + LPC24XX_I2CONCLR);
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disable_irq_nosync(i2c->irq);
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break;
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default:
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/* Unexpected statuses */
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i2c->msg_status = -EIO;
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disable_irq_nosync(i2c->irq);
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break;
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}
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/* Exit on failure or all bytes transferred */
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if (i2c->msg_status != -EBUSY)
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wake_up(&i2c->wait);
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/*
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* If `msg_status` is zero, then `lpc2k_process_msg()`
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* is responsible for clearing the SI flag.
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*/
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if (i2c->msg_status != 0)
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writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
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}
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static int lpc2k_process_msg(struct lpc2k_i2c *i2c, int msgidx)
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{
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/* A new transfer is kicked off by initiating a start condition */
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if (!msgidx) {
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writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONSET);
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} else {
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/*
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* A multi-message I2C transfer continues where the
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* previous I2C transfer left off and uses the
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* current condition of the I2C adapter.
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*/
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if (unlikely(i2c->msg->flags & I2C_M_NOSTART)) {
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WARN_ON(i2c->msg->len == 0);
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if (!(i2c->msg->flags & I2C_M_RD)) {
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/* Start transmit of data */
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writel(i2c->msg->buf[0],
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i2c->base + LPC24XX_I2DAT);
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i2c->msg_idx++;
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}
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} else {
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/* Start or repeated start */
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writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONSET);
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}
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writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
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}
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enable_irq(i2c->irq);
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/* Wait for transfer completion */
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if (wait_event_timeout(i2c->wait, i2c->msg_status != -EBUSY,
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msecs_to_jiffies(1000)) == 0) {
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disable_irq_nosync(i2c->irq);
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return -ETIMEDOUT;
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}
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return i2c->msg_status;
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}
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static int i2c_lpc2k_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
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int msg_num)
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{
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struct lpc2k_i2c *i2c = i2c_get_adapdata(adap);
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int ret, i;
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u32 stat;
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/* Check for bus idle condition */
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stat = readl(i2c->base + LPC24XX_I2STAT);
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if (stat != M_I2C_IDLE) {
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/* Something is holding the bus, try to clear it */
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return i2c_lpc2k_clear_arb(i2c);
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}
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/* Process a single message at a time */
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for (i = 0; i < msg_num; i++) {
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/* Save message pointer and current message data index */
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i2c->msg = &msgs[i];
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i2c->msg_idx = 0;
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i2c->msg_status = -EBUSY;
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i2c->is_last = (i == (msg_num - 1));
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ret = lpc2k_process_msg(i2c, i);
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if (ret)
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return ret;
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}
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return msg_num;
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}
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static irqreturn_t i2c_lpc2k_handler(int irq, void *dev_id)
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{
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struct lpc2k_i2c *i2c = dev_id;
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if (readl(i2c->base + LPC24XX_I2CONSET) & LPC24XX_SI) {
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i2c_lpc2k_pump_msg(i2c);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static u32 i2c_lpc2k_functionality(struct i2c_adapter *adap)
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{
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/* Only emulated SMBus for now */
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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}
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static const struct i2c_algorithm i2c_lpc2k_algorithm = {
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.master_xfer = i2c_lpc2k_xfer,
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.functionality = i2c_lpc2k_functionality,
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};
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static int i2c_lpc2k_probe(struct platform_device *pdev)
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{
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struct lpc2k_i2c *i2c;
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u32 bus_clk_rate;
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u32 scl_high;
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u32 clkrate;
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int ret;
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i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
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if (!i2c)
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return -ENOMEM;
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i2c->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(i2c->base))
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return PTR_ERR(i2c->base);
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i2c->irq = platform_get_irq(pdev, 0);
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if (i2c->irq < 0)
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return i2c->irq;
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init_waitqueue_head(&i2c->wait);
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i2c->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(i2c->clk)) {
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dev_err(&pdev->dev, "error getting clock\n");
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return PTR_ERR(i2c->clk);
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}
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ret = clk_prepare_enable(i2c->clk);
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if (ret) {
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dev_err(&pdev->dev, "unable to enable clock.\n");
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return ret;
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}
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ret = devm_request_irq(&pdev->dev, i2c->irq, i2c_lpc2k_handler, 0,
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dev_name(&pdev->dev), i2c);
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if (ret < 0) {
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dev_err(&pdev->dev, "can't request interrupt.\n");
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goto fail_clk;
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}
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disable_irq_nosync(i2c->irq);
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/* Place controller is a known state */
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i2c_lpc2k_reset(i2c);
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ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
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&bus_clk_rate);
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if (ret)
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bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ;
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clkrate = clk_get_rate(i2c->clk);
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if (clkrate == 0) {
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dev_err(&pdev->dev, "can't get I2C base clock\n");
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ret = -EINVAL;
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goto fail_clk;
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}
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/* Setup I2C dividers to generate clock with proper duty cycle */
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clkrate = clkrate / bus_clk_rate;
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if (bus_clk_rate <= I2C_MAX_STANDARD_MODE_FREQ)
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scl_high = (clkrate * I2C_STD_MODE_DUTY) / 100;
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else if (bus_clk_rate <= I2C_MAX_FAST_MODE_FREQ)
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scl_high = (clkrate * I2C_FAST_MODE_DUTY) / 100;
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else
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scl_high = (clkrate * I2C_FAST_MODE_PLUS_DUTY) / 100;
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writel(scl_high, i2c->base + LPC24XX_I2SCLH);
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writel(clkrate - scl_high, i2c->base + LPC24XX_I2SCLL);
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platform_set_drvdata(pdev, i2c);
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i2c_set_adapdata(&i2c->adap, i2c);
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i2c->adap.owner = THIS_MODULE;
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strlcpy(i2c->adap.name, "LPC2K I2C adapter", sizeof(i2c->adap.name));
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i2c->adap.algo = &i2c_lpc2k_algorithm;
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i2c->adap.dev.parent = &pdev->dev;
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i2c->adap.dev.of_node = pdev->dev.of_node;
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ret = i2c_add_adapter(&i2c->adap);
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if (ret < 0)
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goto fail_clk;
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dev_info(&pdev->dev, "LPC2K I2C adapter\n");
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return 0;
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fail_clk:
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clk_disable_unprepare(i2c->clk);
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return ret;
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}
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static int i2c_lpc2k_remove(struct platform_device *dev)
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{
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struct lpc2k_i2c *i2c = platform_get_drvdata(dev);
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i2c_del_adapter(&i2c->adap);
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clk_disable_unprepare(i2c->clk);
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return 0;
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}
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#ifdef CONFIG_PM
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static int i2c_lpc2k_suspend(struct device *dev)
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{
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struct lpc2k_i2c *i2c = dev_get_drvdata(dev);
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clk_disable(i2c->clk);
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return 0;
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}
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static int i2c_lpc2k_resume(struct device *dev)
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{
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struct lpc2k_i2c *i2c = dev_get_drvdata(dev);
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clk_enable(i2c->clk);
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i2c_lpc2k_reset(i2c);
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return 0;
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}
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static const struct dev_pm_ops i2c_lpc2k_dev_pm_ops = {
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.suspend_noirq = i2c_lpc2k_suspend,
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.resume_noirq = i2c_lpc2k_resume,
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};
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#define I2C_LPC2K_DEV_PM_OPS (&i2c_lpc2k_dev_pm_ops)
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#else
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#define I2C_LPC2K_DEV_PM_OPS NULL
|
|
#endif
|
|
|
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static const struct of_device_id lpc2k_i2c_match[] = {
|
|
{ .compatible = "nxp,lpc1788-i2c" },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, lpc2k_i2c_match);
|
|
|
|
static struct platform_driver i2c_lpc2k_driver = {
|
|
.probe = i2c_lpc2k_probe,
|
|
.remove = i2c_lpc2k_remove,
|
|
.driver = {
|
|
.name = "lpc2k-i2c",
|
|
.pm = I2C_LPC2K_DEV_PM_OPS,
|
|
.of_match_table = lpc2k_i2c_match,
|
|
},
|
|
};
|
|
module_platform_driver(i2c_lpc2k_driver);
|
|
|
|
MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
|
|
MODULE_DESCRIPTION("I2C driver for LPC2xxx devices");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:lpc2k-i2c");
|