664 строки
16 KiB
C
664 строки
16 KiB
C
/*
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* SN Platform GRU Driver
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*
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* GRU HANDLE DEFINITION
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*
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* Copyright (c) 2008 Silicon Graphics, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __GRUHANDLES_H__
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#define __GRUHANDLES_H__
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#include "gru_instructions.h"
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/*
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* Manifest constants for GRU Memory Map
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*/
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#define GRU_GSEG0_BASE 0
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#define GRU_MCS_BASE (64 * 1024 * 1024)
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#define GRU_SIZE (128UL * 1024 * 1024)
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/* Handle & resource counts */
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#define GRU_NUM_CB 128
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#define GRU_NUM_DSR_BYTES (32 * 1024)
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#define GRU_NUM_TFM 16
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#define GRU_NUM_TGH 24
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#define GRU_NUM_CBE 128
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#define GRU_NUM_TFH 128
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#define GRU_NUM_CCH 16
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#define GRU_NUM_GSH 1
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/* Maximum resource counts that can be reserved by user programs */
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#define GRU_NUM_USER_CBR GRU_NUM_CBE
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#define GRU_NUM_USER_DSR_BYTES GRU_NUM_DSR_BYTES
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/* Bytes per handle & handle stride. Code assumes all cb, tfh, cbe handles
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* are the same */
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#define GRU_HANDLE_BYTES 64
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#define GRU_HANDLE_STRIDE 256
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/* Base addresses of handles */
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#define GRU_TFM_BASE (GRU_MCS_BASE + 0x00000)
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#define GRU_TGH_BASE (GRU_MCS_BASE + 0x08000)
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#define GRU_CBE_BASE (GRU_MCS_BASE + 0x10000)
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#define GRU_TFH_BASE (GRU_MCS_BASE + 0x18000)
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#define GRU_CCH_BASE (GRU_MCS_BASE + 0x20000)
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#define GRU_GSH_BASE (GRU_MCS_BASE + 0x30000)
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/* User gseg constants */
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#define GRU_GSEG_STRIDE (4 * 1024 * 1024)
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#define GSEG_BASE(a) ((a) & ~(GRU_GSEG_PAGESIZE - 1))
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/* Data segment constants */
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#define GRU_DSR_AU_BYTES 1024
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#define GRU_DSR_CL (GRU_NUM_DSR_BYTES / GRU_CACHE_LINE_BYTES)
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#define GRU_DSR_AU_CL (GRU_DSR_AU_BYTES / GRU_CACHE_LINE_BYTES)
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#define GRU_DSR_AU (GRU_NUM_DSR_BYTES / GRU_DSR_AU_BYTES)
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/* Control block constants */
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#define GRU_CBR_AU_SIZE 2
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#define GRU_CBR_AU (GRU_NUM_CBE / GRU_CBR_AU_SIZE)
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/* Convert resource counts to the number of AU */
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#define GRU_DS_BYTES_TO_AU(n) DIV_ROUND_UP(n, GRU_DSR_AU_BYTES)
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#define GRU_CB_COUNT_TO_AU(n) DIV_ROUND_UP(n, GRU_CBR_AU_SIZE)
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/* UV limits */
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#define GRU_CHIPLETS_PER_HUB 2
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#define GRU_HUBS_PER_BLADE 1
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#define GRU_CHIPLETS_PER_BLADE (GRU_HUBS_PER_BLADE * GRU_CHIPLETS_PER_HUB)
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/* User GRU Gseg offsets */
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#define GRU_CB_BASE 0
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#define GRU_CB_LIMIT (GRU_CB_BASE + GRU_HANDLE_STRIDE * GRU_NUM_CBE)
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#define GRU_DS_BASE 0x20000
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#define GRU_DS_LIMIT (GRU_DS_BASE + GRU_NUM_DSR_BYTES)
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/* Convert a GRU physical address to the chiplet offset */
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#define GSEGPOFF(h) ((h) & (GRU_SIZE - 1))
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/* Convert an arbitrary handle address to the beginning of the GRU segment */
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#ifndef __PLUGIN__
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#define GRUBASE(h) ((void *)((unsigned long)(h) & ~(GRU_SIZE - 1)))
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#else
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extern void *gmu_grubase(void *h);
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#define GRUBASE(h) gmu_grubase(h)
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#endif
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/* General addressing macros. */
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static inline void *get_gseg_base_address(void *base, int ctxnum)
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{
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return (void *)(base + GRU_GSEG0_BASE + GRU_GSEG_STRIDE * ctxnum);
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}
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static inline void *get_gseg_base_address_cb(void *base, int ctxnum, int line)
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{
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return (void *)(get_gseg_base_address(base, ctxnum) +
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GRU_CB_BASE + GRU_HANDLE_STRIDE * line);
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}
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static inline void *get_gseg_base_address_ds(void *base, int ctxnum, int line)
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{
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return (void *)(get_gseg_base_address(base, ctxnum) + GRU_DS_BASE +
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GRU_CACHE_LINE_BYTES * line);
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}
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static inline struct gru_tlb_fault_map *get_tfm(void *base, int ctxnum)
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{
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return (struct gru_tlb_fault_map *)(base + GRU_TFM_BASE +
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ctxnum * GRU_HANDLE_STRIDE);
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}
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static inline struct gru_tlb_global_handle *get_tgh(void *base, int ctxnum)
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{
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return (struct gru_tlb_global_handle *)(base + GRU_TGH_BASE +
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ctxnum * GRU_HANDLE_STRIDE);
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}
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static inline struct gru_control_block_extended *get_cbe(void *base, int ctxnum)
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{
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return (struct gru_control_block_extended *)(base + GRU_CBE_BASE +
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ctxnum * GRU_HANDLE_STRIDE);
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}
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static inline struct gru_tlb_fault_handle *get_tfh(void *base, int ctxnum)
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{
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return (struct gru_tlb_fault_handle *)(base + GRU_TFH_BASE +
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ctxnum * GRU_HANDLE_STRIDE);
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}
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static inline struct gru_context_configuration_handle *get_cch(void *base,
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int ctxnum)
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{
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return (struct gru_context_configuration_handle *)(base +
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GRU_CCH_BASE + ctxnum * GRU_HANDLE_STRIDE);
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}
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static inline unsigned long get_cb_number(void *cb)
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{
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return (((unsigned long)cb - GRU_CB_BASE) % GRU_GSEG_PAGESIZE) /
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GRU_HANDLE_STRIDE;
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}
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/* byte offset to a specific GRU chiplet. (p=pnode, c=chiplet (0 or 1)*/
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static inline unsigned long gru_chiplet_paddr(unsigned long paddr, int pnode,
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int chiplet)
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{
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return paddr + GRU_SIZE * (2 * pnode + chiplet);
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}
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static inline void *gru_chiplet_vaddr(void *vaddr, int pnode, int chiplet)
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{
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return vaddr + GRU_SIZE * (2 * pnode + chiplet);
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}
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/*
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* Global TLB Fault Map
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* Bitmap of outstanding TLB misses needing interrupt/polling service.
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*
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*/
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struct gru_tlb_fault_map {
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unsigned long fault_bits[BITS_TO_LONGS(GRU_NUM_CBE)];
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unsigned long fill0[2];
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unsigned long done_bits[BITS_TO_LONGS(GRU_NUM_CBE)];
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unsigned long fill1[2];
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};
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/*
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* TGH - TLB Global Handle
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* Used for TLB flushing.
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*
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*/
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struct gru_tlb_global_handle {
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unsigned int cmd:1; /* DW 0 */
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unsigned int delresp:1;
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unsigned int opc:1;
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unsigned int fill1:5;
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unsigned int fill2:8;
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unsigned int status:2;
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unsigned long fill3:2;
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unsigned int state:3;
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unsigned long fill4:1;
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unsigned int cause:3;
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unsigned long fill5:37;
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unsigned long vaddr:64; /* DW 1 */
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unsigned int asid:24; /* DW 2 */
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unsigned int fill6:8;
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unsigned int pagesize:5;
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unsigned int fill7:11;
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unsigned int global:1;
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unsigned int fill8:15;
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unsigned long vaddrmask:39; /* DW 3 */
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unsigned int fill9:9;
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unsigned int n:10;
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unsigned int fill10:6;
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unsigned int ctxbitmap:16; /* DW4 */
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unsigned long fill11[3];
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};
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enum gru_tgh_cmd {
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TGHCMD_START
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};
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enum gru_tgh_opc {
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TGHOP_TLBNOP,
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TGHOP_TLBINV
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};
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enum gru_tgh_status {
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TGHSTATUS_IDLE,
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TGHSTATUS_EXCEPTION,
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TGHSTATUS_ACTIVE
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};
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enum gru_tgh_state {
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TGHSTATE_IDLE,
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TGHSTATE_PE_INVAL,
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TGHSTATE_INTERRUPT_INVAL,
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TGHSTATE_WAITDONE,
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TGHSTATE_RESTART_CTX,
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};
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/*
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* TFH - TLB Global Handle
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* Used for TLB dropins into the GRU TLB.
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*
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*/
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struct gru_tlb_fault_handle {
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unsigned int cmd:1; /* DW 0 - low 32*/
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unsigned int delresp:1;
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unsigned int fill0:2;
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unsigned int opc:3;
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unsigned int fill1:9;
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unsigned int status:2;
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unsigned int fill2:1;
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unsigned int color:1;
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unsigned int state:3;
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unsigned int fill3:1;
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unsigned int cause:7; /* DW 0 - high 32 */
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unsigned int fill4:1;
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unsigned int indexway:12;
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unsigned int fill5:4;
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unsigned int ctxnum:4;
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unsigned int fill6:12;
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unsigned long missvaddr:64; /* DW 1 */
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unsigned int missasid:24; /* DW 2 */
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unsigned int fill7:8;
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unsigned int fillasid:24;
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unsigned int dirty:1;
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unsigned int gaa:2;
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unsigned long fill8:5;
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unsigned long pfn:41; /* DW 3 */
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unsigned int fill9:7;
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unsigned int pagesize:5;
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unsigned int fill10:11;
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unsigned long fillvaddr:64; /* DW 4 */
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unsigned long fill11[3];
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};
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enum gru_tfh_opc {
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TFHOP_NOOP,
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TFHOP_RESTART,
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TFHOP_WRITE_ONLY,
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TFHOP_WRITE_RESTART,
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TFHOP_EXCEPTION,
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TFHOP_USER_POLLING_MODE = 7,
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};
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enum tfh_status {
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TFHSTATUS_IDLE,
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TFHSTATUS_EXCEPTION,
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TFHSTATUS_ACTIVE,
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};
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enum tfh_state {
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TFHSTATE_INACTIVE,
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TFHSTATE_IDLE,
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TFHSTATE_MISS_UPM,
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TFHSTATE_MISS_FMM,
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TFHSTATE_HW_ERR,
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TFHSTATE_WRITE_TLB,
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TFHSTATE_RESTART_CBR,
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};
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/* TFH cause bits */
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enum tfh_cause {
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TFHCAUSE_NONE,
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TFHCAUSE_TLB_MISS,
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TFHCAUSE_TLB_MOD,
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TFHCAUSE_HW_ERROR_RR,
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TFHCAUSE_HW_ERROR_MAIN_ARRAY,
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TFHCAUSE_HW_ERROR_VALID,
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TFHCAUSE_HW_ERROR_PAGESIZE,
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TFHCAUSE_INSTRUCTION_EXCEPTION,
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TFHCAUSE_UNCORRECTIBLE_ERROR,
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};
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/* GAA values */
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#define GAA_RAM 0x0
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#define GAA_NCRAM 0x2
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#define GAA_MMIO 0x1
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#define GAA_REGISTER 0x3
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/* GRU paddr shift for pfn. (NOTE: shift is NOT by actual pagesize) */
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#define GRU_PADDR_SHIFT 12
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/*
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* Context Configuration handle
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* Used to allocate resources to a GSEG context.
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*
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*/
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struct gru_context_configuration_handle {
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unsigned int cmd:1; /* DW0 */
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unsigned int delresp:1;
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unsigned int opc:3;
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unsigned int unmap_enable:1;
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unsigned int req_slice_set_enable:1;
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unsigned int req_slice:2;
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unsigned int cb_int_enable:1;
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unsigned int tlb_int_enable:1;
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unsigned int tfm_fault_bit_enable:1;
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unsigned int tlb_int_select:4;
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unsigned int status:2;
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unsigned int state:2;
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unsigned int reserved2:4;
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unsigned int cause:4;
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unsigned int tfm_done_bit_enable:1;
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unsigned int unused:3;
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unsigned int dsr_allocation_map;
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unsigned long cbr_allocation_map; /* DW1 */
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unsigned int asid[8]; /* DW 2 - 5 */
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unsigned short sizeavail[8]; /* DW 6 - 7 */
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} __attribute__ ((packed));
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enum gru_cch_opc {
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CCHOP_START = 1,
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CCHOP_ALLOCATE,
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CCHOP_INTERRUPT,
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CCHOP_DEALLOCATE,
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CCHOP_INTERRUPT_SYNC,
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};
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enum gru_cch_status {
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CCHSTATUS_IDLE,
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CCHSTATUS_EXCEPTION,
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CCHSTATUS_ACTIVE,
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};
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enum gru_cch_state {
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CCHSTATE_INACTIVE,
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CCHSTATE_MAPPED,
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CCHSTATE_ACTIVE,
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CCHSTATE_INTERRUPTED,
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};
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/* CCH Exception cause */
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enum gru_cch_cause {
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CCHCAUSE_REGION_REGISTER_WRITE_ERROR = 1,
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CCHCAUSE_ILLEGAL_OPCODE = 2,
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CCHCAUSE_INVALID_START_REQUEST = 3,
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CCHCAUSE_INVALID_ALLOCATION_REQUEST = 4,
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CCHCAUSE_INVALID_DEALLOCATION_REQUEST = 5,
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CCHCAUSE_INVALID_INTERRUPT_REQUEST = 6,
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CCHCAUSE_CCH_BUSY = 7,
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CCHCAUSE_NO_CBRS_TO_ALLOCATE = 8,
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CCHCAUSE_BAD_TFM_CONFIG = 9,
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CCHCAUSE_CBR_RESOURCES_OVERSUBSCRIPED = 10,
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CCHCAUSE_DSR_RESOURCES_OVERSUBSCRIPED = 11,
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CCHCAUSE_CBR_DEALLOCATION_ERROR = 12,
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};
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/*
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* CBE - Control Block Extended
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* Maintains internal GRU state for active CBs.
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*
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*/
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struct gru_control_block_extended {
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unsigned int reserved0:1; /* DW 0 - low */
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unsigned int imacpy:3;
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unsigned int reserved1:4;
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unsigned int xtypecpy:3;
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unsigned int iaa0cpy:2;
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unsigned int iaa1cpy:2;
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unsigned int reserved2:1;
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unsigned int opccpy:8;
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unsigned int exopccpy:8;
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unsigned int idef2cpy:22; /* DW 0 - high */
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unsigned int reserved3:10;
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unsigned int idef4cpy:22; /* DW 1 */
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unsigned int reserved4:10;
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unsigned int idef4upd:22;
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unsigned int reserved5:10;
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unsigned long idef1upd:64; /* DW 2 */
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unsigned long idef5cpy:64; /* DW 3 */
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unsigned long idef6cpy:64; /* DW 4 */
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unsigned long idef3upd:64; /* DW 5 */
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unsigned long idef5upd:64; /* DW 6 */
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unsigned int idef2upd:22; /* DW 7 */
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unsigned int reserved6:10;
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unsigned int ecause:20;
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unsigned int cbrstate:4;
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unsigned int cbrexecstatus:8;
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};
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enum gru_cbr_state {
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CBRSTATE_INACTIVE,
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CBRSTATE_IDLE,
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CBRSTATE_PE_CHECK,
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CBRSTATE_QUEUED,
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CBRSTATE_WAIT_RESPONSE,
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CBRSTATE_INTERRUPTED,
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CBRSTATE_INTERRUPTED_MISS_FMM,
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CBRSTATE_BUSY_INTERRUPT_MISS_FMM,
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CBRSTATE_INTERRUPTED_MISS_UPM,
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CBRSTATE_BUSY_INTERRUPTED_MISS_UPM,
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CBRSTATE_REQUEST_ISSUE,
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CBRSTATE_BUSY_INTERRUPT,
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};
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/* CBE cbrexecstatus bits */
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#define CBR_EXS_ABORT_OCC_BIT 0
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#define CBR_EXS_INT_OCC_BIT 1
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#define CBR_EXS_PENDING_BIT 2
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#define CBR_EXS_QUEUED_BIT 3
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#define CBR_EXS_TLBHW_BIT 4
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#define CBR_EXS_EXCEPTION_BIT 5
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#define CBR_EXS_ABORT_OCC (1 << CBR_EXS_ABORT_OCC_BIT)
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#define CBR_EXS_INT_OCC (1 << CBR_EXS_INT_OCC_BIT)
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#define CBR_EXS_PENDING (1 << CBR_EXS_PENDING_BIT)
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#define CBR_EXS_QUEUED (1 << CBR_EXS_QUEUED_BIT)
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#define CBR_EXS_TLBHW (1 << CBR_EXS_TLBHW_BIT)
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#define CBR_EXS_EXCEPTION (1 << CBR_EXS_EXCEPTION_BIT)
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/* CBE ecause bits - defined in gru_instructions.h */
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/*
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* Convert a processor pagesize into the strange encoded pagesize used by the
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* GRU. Processor pagesize is encoded as log of bytes per page. (or PAGE_SHIFT)
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* pagesize log pagesize grupagesize
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* 4k 12 0
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* 16k 14 1
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* 64k 16 2
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* 256k 18 3
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* 1m 20 4
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* 2m 21 5
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* 4m 22 6
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* 16m 24 7
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* 64m 26 8
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* ...
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*/
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#define GRU_PAGESIZE(sh) ((((sh) > 20 ? (sh) + 2: (sh)) >> 1) - 6)
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#define GRU_SIZEAVAIL(sh) (1UL << GRU_PAGESIZE(sh))
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/* minimum TLB purge count to ensure a full purge */
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#define GRUMAXINVAL 1024UL
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/* Extract the status field from a kernel handle */
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|
#define GET_MSEG_HANDLE_STATUS(h) (((*(unsigned long *)(h)) >> 16) & 3)
|
|
|
|
static inline void start_instruction(void *h)
|
|
{
|
|
unsigned long *w0 = h;
|
|
|
|
wmb(); /* setting CMD bit must be last */
|
|
*w0 = *w0 | 1;
|
|
gru_flush_cache(h);
|
|
}
|
|
|
|
static inline int wait_instruction_complete(void *h)
|
|
{
|
|
int status;
|
|
|
|
do {
|
|
cpu_relax();
|
|
barrier();
|
|
status = GET_MSEG_HANDLE_STATUS(h);
|
|
} while (status == CCHSTATUS_ACTIVE);
|
|
return status;
|
|
}
|
|
|
|
#if defined CONFIG_IA64
|
|
static inline void cch_allocate_set_asids(
|
|
struct gru_context_configuration_handle *cch, int asidval)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i <= RGN_HPAGE; i++) { /* assume HPAGE is last region */
|
|
cch->asid[i] = (asidval++);
|
|
#if 0
|
|
/* ZZZ hugepages not supported yet */
|
|
if (i == RGN_HPAGE)
|
|
cch->sizeavail[i] = GRU_SIZEAVAIL(hpage_shift);
|
|
else
|
|
#endif
|
|
cch->sizeavail[i] = GRU_SIZEAVAIL(PAGE_SHIFT);
|
|
}
|
|
}
|
|
#elif defined CONFIG_X86_64
|
|
static inline void cch_allocate_set_asids(
|
|
struct gru_context_configuration_handle *cch, int asidval)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
cch->asid[i] = asidval++;
|
|
cch->sizeavail[i] = GRU_SIZEAVAIL(PAGE_SHIFT) |
|
|
GRU_SIZEAVAIL(21);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
static inline int cch_allocate(struct gru_context_configuration_handle *cch,
|
|
int asidval, unsigned long cbrmap,
|
|
unsigned long dsrmap)
|
|
{
|
|
cch_allocate_set_asids(cch, asidval);
|
|
cch->dsr_allocation_map = dsrmap;
|
|
cch->cbr_allocation_map = cbrmap;
|
|
cch->opc = CCHOP_ALLOCATE;
|
|
start_instruction(cch);
|
|
return wait_instruction_complete(cch);
|
|
}
|
|
|
|
static inline int cch_start(struct gru_context_configuration_handle *cch)
|
|
{
|
|
cch->opc = CCHOP_START;
|
|
start_instruction(cch);
|
|
return wait_instruction_complete(cch);
|
|
}
|
|
|
|
static inline int cch_interrupt(struct gru_context_configuration_handle *cch)
|
|
{
|
|
cch->opc = CCHOP_INTERRUPT;
|
|
start_instruction(cch);
|
|
return wait_instruction_complete(cch);
|
|
}
|
|
|
|
static inline int cch_deallocate(struct gru_context_configuration_handle *cch)
|
|
{
|
|
cch->opc = CCHOP_DEALLOCATE;
|
|
start_instruction(cch);
|
|
return wait_instruction_complete(cch);
|
|
}
|
|
|
|
static inline int cch_interrupt_sync(struct gru_context_configuration_handle
|
|
*cch)
|
|
{
|
|
cch->opc = CCHOP_INTERRUPT_SYNC;
|
|
start_instruction(cch);
|
|
return wait_instruction_complete(cch);
|
|
}
|
|
|
|
static inline int tgh_invalidate(struct gru_tlb_global_handle *tgh,
|
|
unsigned long vaddr, unsigned long vaddrmask,
|
|
int asid, int pagesize, int global, int n,
|
|
unsigned short ctxbitmap)
|
|
{
|
|
tgh->vaddr = vaddr;
|
|
tgh->asid = asid;
|
|
tgh->pagesize = pagesize;
|
|
tgh->n = n;
|
|
tgh->global = global;
|
|
tgh->vaddrmask = vaddrmask;
|
|
tgh->ctxbitmap = ctxbitmap;
|
|
tgh->opc = TGHOP_TLBINV;
|
|
start_instruction(tgh);
|
|
return wait_instruction_complete(tgh);
|
|
}
|
|
|
|
static inline void tfh_write_only(struct gru_tlb_fault_handle *tfh,
|
|
unsigned long pfn, unsigned long vaddr,
|
|
int asid, int dirty, int pagesize)
|
|
{
|
|
tfh->fillasid = asid;
|
|
tfh->fillvaddr = vaddr;
|
|
tfh->pfn = pfn;
|
|
tfh->dirty = dirty;
|
|
tfh->pagesize = pagesize;
|
|
tfh->opc = TFHOP_WRITE_ONLY;
|
|
start_instruction(tfh);
|
|
}
|
|
|
|
static inline void tfh_write_restart(struct gru_tlb_fault_handle *tfh,
|
|
unsigned long paddr, int gaa,
|
|
unsigned long vaddr, int asid, int dirty,
|
|
int pagesize)
|
|
{
|
|
tfh->fillasid = asid;
|
|
tfh->fillvaddr = vaddr;
|
|
tfh->pfn = paddr >> GRU_PADDR_SHIFT;
|
|
tfh->gaa = gaa;
|
|
tfh->dirty = dirty;
|
|
tfh->pagesize = pagesize;
|
|
tfh->opc = TFHOP_WRITE_RESTART;
|
|
start_instruction(tfh);
|
|
}
|
|
|
|
static inline void tfh_restart(struct gru_tlb_fault_handle *tfh)
|
|
{
|
|
tfh->opc = TFHOP_RESTART;
|
|
start_instruction(tfh);
|
|
}
|
|
|
|
static inline void tfh_user_polling_mode(struct gru_tlb_fault_handle *tfh)
|
|
{
|
|
tfh->opc = TFHOP_USER_POLLING_MODE;
|
|
start_instruction(tfh);
|
|
}
|
|
|
|
static inline void tfh_exception(struct gru_tlb_fault_handle *tfh)
|
|
{
|
|
tfh->opc = TFHOP_EXCEPTION;
|
|
start_instruction(tfh);
|
|
}
|
|
|
|
#endif /* __GRUHANDLES_H__ */
|