455 строки
13 KiB
C
455 строки
13 KiB
C
/*
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* Atheros AR71XX/AR724X/AR913X common routines
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*
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* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
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* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
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*
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* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <asm/div64.h>
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "common.h"
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#define AR71XX_BASE_FREQ 40000000
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#define AR724X_BASE_FREQ 40000000
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static struct clk *clks[3];
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static struct clk_onecell_data clk_data = {
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.clks = clks,
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.clk_num = ARRAY_SIZE(clks),
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};
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static struct clk *__init ath79_add_sys_clkdev(
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const char *id, unsigned long rate)
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{
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struct clk *clk;
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int err;
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clk = clk_register_fixed_rate(NULL, id, NULL, CLK_IS_ROOT, rate);
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if (!clk)
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panic("failed to allocate %s clock structure", id);
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err = clk_register_clkdev(clk, id, NULL);
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if (err)
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panic("unable to register %s clock device", id);
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return clk;
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}
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static void __init ar71xx_clocks_init(void)
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{
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unsigned long ref_rate;
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unsigned long cpu_rate;
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unsigned long ddr_rate;
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unsigned long ahb_rate;
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u32 pll;
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u32 freq;
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u32 div;
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ref_rate = AR71XX_BASE_FREQ;
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pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
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div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
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freq = div * ref_rate;
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div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
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cpu_rate = freq / div;
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div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
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ddr_rate = freq / div;
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div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
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ahb_rate = cpu_rate / div;
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ath79_add_sys_clkdev("ref", ref_rate);
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clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
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clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
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clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
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clk_add_alias("wdt", NULL, "ahb", NULL);
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clk_add_alias("uart", NULL, "ahb", NULL);
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}
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static void __init ar724x_clocks_init(void)
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{
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unsigned long ref_rate;
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unsigned long cpu_rate;
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unsigned long ddr_rate;
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unsigned long ahb_rate;
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u32 pll;
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u32 freq;
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u32 div;
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ref_rate = AR724X_BASE_FREQ;
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pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
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div = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
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freq = div * ref_rate;
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div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
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freq /= div;
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cpu_rate = freq;
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div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
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ddr_rate = freq / div;
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div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
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ahb_rate = cpu_rate / div;
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ath79_add_sys_clkdev("ref", ref_rate);
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clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
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clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
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clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
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clk_add_alias("wdt", NULL, "ahb", NULL);
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clk_add_alias("uart", NULL, "ahb", NULL);
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}
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static void __init ar933x_clocks_init(void)
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{
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unsigned long ref_rate;
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unsigned long cpu_rate;
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unsigned long ddr_rate;
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unsigned long ahb_rate;
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u32 clock_ctrl;
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u32 cpu_config;
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u32 freq;
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u32 t;
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t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
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if (t & AR933X_BOOTSTRAP_REF_CLK_40)
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ref_rate = (40 * 1000 * 1000);
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else
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ref_rate = (25 * 1000 * 1000);
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clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
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if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
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cpu_rate = ref_rate;
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ahb_rate = ref_rate;
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ddr_rate = ref_rate;
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} else {
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cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
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t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
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freq = ref_rate / t;
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t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
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AR933X_PLL_CPU_CONFIG_NINT_MASK;
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freq *= t;
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t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
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if (t == 0)
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t = 1;
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freq >>= t;
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t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
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AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
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cpu_rate = freq / t;
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t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
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AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
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ddr_rate = freq / t;
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t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
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AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
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ahb_rate = freq / t;
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}
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ath79_add_sys_clkdev("ref", ref_rate);
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clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
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clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
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clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
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clk_add_alias("wdt", NULL, "ahb", NULL);
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clk_add_alias("uart", NULL, "ref", NULL);
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}
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static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
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u32 frac, u32 out_div)
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{
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u64 t;
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u32 ret;
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t = ref;
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t *= nint;
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do_div(t, ref_div);
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ret = t;
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t = ref;
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t *= nfrac;
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do_div(t, ref_div * frac);
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ret += t;
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ret /= (1 << out_div);
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return ret;
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}
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static void __init ar934x_clocks_init(void)
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{
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unsigned long ref_rate;
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unsigned long cpu_rate;
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unsigned long ddr_rate;
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unsigned long ahb_rate;
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u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
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u32 cpu_pll, ddr_pll;
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u32 bootstrap;
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void __iomem *dpll_base;
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dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE);
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bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
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if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
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ref_rate = 40 * 1000 * 1000;
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else
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ref_rate = 25 * 1000 * 1000;
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pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
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if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
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out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
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AR934X_SRIF_DPLL2_OUTDIV_MASK;
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pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);
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nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
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AR934X_SRIF_DPLL1_NINT_MASK;
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nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
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ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
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AR934X_SRIF_DPLL1_REFDIV_MASK;
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frac = 1 << 18;
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} else {
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pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
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out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
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ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
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nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
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AR934X_PLL_CPU_CONFIG_NINT_MASK;
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nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
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AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
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frac = 1 << 6;
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}
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cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
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nfrac, frac, out_div);
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pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
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if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
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out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
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AR934X_SRIF_DPLL2_OUTDIV_MASK;
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pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);
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nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
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AR934X_SRIF_DPLL1_NINT_MASK;
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nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
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ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
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AR934X_SRIF_DPLL1_REFDIV_MASK;
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frac = 1 << 18;
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} else {
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pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
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out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
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AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
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ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
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AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
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nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
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AR934X_PLL_DDR_CONFIG_NINT_MASK;
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nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
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AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
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frac = 1 << 10;
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}
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ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
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nfrac, frac, out_div);
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clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
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postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
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AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
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if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
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cpu_rate = ref_rate;
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else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
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cpu_rate = cpu_pll / (postdiv + 1);
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else
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cpu_rate = ddr_pll / (postdiv + 1);
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postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
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AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
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if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
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ddr_rate = ref_rate;
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else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
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ddr_rate = ddr_pll / (postdiv + 1);
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else
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ddr_rate = cpu_pll / (postdiv + 1);
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postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
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AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
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if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
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ahb_rate = ref_rate;
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else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
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ahb_rate = ddr_pll / (postdiv + 1);
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else
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ahb_rate = cpu_pll / (postdiv + 1);
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ath79_add_sys_clkdev("ref", ref_rate);
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clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
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clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
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clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
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clk_add_alias("wdt", NULL, "ref", NULL);
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clk_add_alias("uart", NULL, "ref", NULL);
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iounmap(dpll_base);
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}
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static void __init qca955x_clocks_init(void)
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{
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unsigned long ref_rate;
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unsigned long cpu_rate;
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unsigned long ddr_rate;
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unsigned long ahb_rate;
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u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
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u32 cpu_pll, ddr_pll;
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u32 bootstrap;
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bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
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if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
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ref_rate = 40 * 1000 * 1000;
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else
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ref_rate = 25 * 1000 * 1000;
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pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
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out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
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ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
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nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
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QCA955X_PLL_CPU_CONFIG_NINT_MASK;
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frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
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QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
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cpu_pll = nint * ref_rate / ref_div;
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cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
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cpu_pll /= (1 << out_div);
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pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
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out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
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QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
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ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
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QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
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nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
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QCA955X_PLL_DDR_CONFIG_NINT_MASK;
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frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
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QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
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ddr_pll = nint * ref_rate / ref_div;
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ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
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ddr_pll /= (1 << out_div);
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clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
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postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
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QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
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if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
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cpu_rate = ref_rate;
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else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
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cpu_rate = ddr_pll / (postdiv + 1);
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else
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cpu_rate = cpu_pll / (postdiv + 1);
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postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
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QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
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if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
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ddr_rate = ref_rate;
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else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
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ddr_rate = cpu_pll / (postdiv + 1);
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else
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ddr_rate = ddr_pll / (postdiv + 1);
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postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
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QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
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if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
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ahb_rate = ref_rate;
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else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
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ahb_rate = ddr_pll / (postdiv + 1);
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else
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ahb_rate = cpu_pll / (postdiv + 1);
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ath79_add_sys_clkdev("ref", ref_rate);
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clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
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clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
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clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
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clk_add_alias("wdt", NULL, "ref", NULL);
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clk_add_alias("uart", NULL, "ref", NULL);
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}
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void __init ath79_clocks_init(void)
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{
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if (soc_is_ar71xx())
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ar71xx_clocks_init();
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else if (soc_is_ar724x() || soc_is_ar913x())
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ar724x_clocks_init();
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else if (soc_is_ar933x())
|
|
ar933x_clocks_init();
|
|
else if (soc_is_ar934x())
|
|
ar934x_clocks_init();
|
|
else if (soc_is_qca955x())
|
|
qca955x_clocks_init();
|
|
else
|
|
BUG();
|
|
|
|
of_clk_init(NULL);
|
|
}
|
|
|
|
unsigned long __init
|
|
ath79_get_sys_clk_rate(const char *id)
|
|
{
|
|
struct clk *clk;
|
|
unsigned long rate;
|
|
|
|
clk = clk_get(NULL, id);
|
|
if (IS_ERR(clk))
|
|
panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));
|
|
|
|
rate = clk_get_rate(clk);
|
|
clk_put(clk);
|
|
|
|
return rate;
|
|
}
|
|
|
|
#ifdef CONFIG_OF
|
|
static void __init ath79_clocks_init_dt(struct device_node *np)
|
|
{
|
|
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
|
}
|
|
|
|
CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
|
|
CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
|
|
CLK_OF_DECLARE(ar9130, "qca,ar9130-pll", ath79_clocks_init_dt);
|
|
CLK_OF_DECLARE(ar9330, "qca,ar9330-pll", ath79_clocks_init_dt);
|
|
CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
|
|
CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
|
|
#endif
|