202 строки
5.9 KiB
C
202 строки
5.9 KiB
C
/* atomic.h: These still suck, but the I-cache hit rate is higher.
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*
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* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 2000 Anton Blanchard (anton@linuxcare.com.au)
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* Copyright (C) 2007 Kyle McMartin (kyle@parisc-linux.org)
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*
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* Additions by Keith M Wesolowski (wesolows@foobazco.org) based
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* on asm-parisc/atomic.h Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>.
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*/
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#ifndef __ARCH_SPARC_ATOMIC__
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#define __ARCH_SPARC_ATOMIC__
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#include <linux/types.h>
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typedef struct { volatile int counter; } atomic_t;
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#ifdef __KERNEL__
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/* Emulate cmpxchg() the same way we emulate atomics,
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* by hashing the object address and indexing into an array
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* of spinlocks to get a bit of performance...
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*
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* See arch/sparc/lib/atomic32.c for implementation.
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*
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* Cribbed from <asm-parisc/atomic.h>
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*/
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#define __HAVE_ARCH_CMPXCHG 1
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/* bug catcher for when unsupported size is used - won't link */
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extern void __cmpxchg_called_with_bad_pointer(void);
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/* we only need to support cmpxchg of a u32 on sparc */
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extern unsigned long __cmpxchg_u32(volatile u32 *m, u32 old, u32 new_);
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/* don't worry...optimizer will get rid of most of this */
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static __inline__ unsigned long
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__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size)
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{
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switch(size) {
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case 4:
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return __cmpxchg_u32((u32 *)ptr, (u32)old, (u32)new_);
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default:
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__cmpxchg_called_with_bad_pointer();
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break;
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}
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return old;
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}
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#define cmpxchg(ptr,o,n) ({ \
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__typeof__(*(ptr)) _o_ = (o); \
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__typeof__(*(ptr)) _n_ = (n); \
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(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
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(unsigned long)_n_, sizeof(*(ptr))); \
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})
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#define ATOMIC_INIT(i) { (i) }
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extern int __atomic_add_return(int, atomic_t *);
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extern int atomic_cmpxchg(atomic_t *, int, int);
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#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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extern int atomic_add_unless(atomic_t *, int, int);
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extern void atomic_set(atomic_t *, int);
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#define atomic_read(v) ((v)->counter)
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#define atomic_add(i, v) ((void)__atomic_add_return( (int)(i), (v)))
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#define atomic_sub(i, v) ((void)__atomic_add_return(-(int)(i), (v)))
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#define atomic_inc(v) ((void)__atomic_add_return( 1, (v)))
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#define atomic_dec(v) ((void)__atomic_add_return( -1, (v)))
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#define atomic_add_return(i, v) (__atomic_add_return( (int)(i), (v)))
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#define atomic_sub_return(i, v) (__atomic_add_return(-(int)(i), (v)))
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#define atomic_inc_return(v) (__atomic_add_return( 1, (v)))
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#define atomic_dec_return(v) (__atomic_add_return( -1, (v)))
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#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
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/*
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* atomic_inc_and_test - increment and test
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* @v: pointer of type atomic_t
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*
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* Atomically increments @v by 1
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* and returns true if the result is zero, or false for all
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* other cases.
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*/
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#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
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#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)
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#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
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#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
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/* This is the old 24-bit implementation. It's still used internally
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* by some sparc-specific code, notably the semaphore implementation.
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*/
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typedef struct { volatile int counter; } atomic24_t;
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#ifndef CONFIG_SMP
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#define ATOMIC24_INIT(i) { (i) }
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#define atomic24_read(v) ((v)->counter)
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#define atomic24_set(v, i) (((v)->counter) = i)
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#else
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/* We do the bulk of the actual work out of line in two common
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* routines in assembler, see arch/sparc/lib/atomic.S for the
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* "fun" details.
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*
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* For SMP the trick is you embed the spin lock byte within
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* the word, use the low byte so signedness is easily retained
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* via a quick arithmetic shift. It looks like this:
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*
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* ----------------------------------------
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* | signed 24-bit counter value | lock | atomic_t
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* ----------------------------------------
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* 31 8 7 0
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*/
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#define ATOMIC24_INIT(i) { ((i) << 8) }
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static inline int atomic24_read(const atomic24_t *v)
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{
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int ret = v->counter;
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while(ret & 0xff)
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ret = v->counter;
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return ret >> 8;
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}
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#define atomic24_set(v, i) (((v)->counter) = ((i) << 8))
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#endif
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static inline int __atomic24_add(int i, atomic24_t *v)
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{
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register volatile int *ptr asm("g1");
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register int increment asm("g2");
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register int tmp1 asm("g3");
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register int tmp2 asm("g4");
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register int tmp3 asm("g7");
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ptr = &v->counter;
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increment = i;
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__asm__ __volatile__(
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"mov %%o7, %%g4\n\t"
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"call ___atomic24_add\n\t"
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" add %%o7, 8, %%o7\n"
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: "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)
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: "0" (increment), "r" (ptr)
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: "memory", "cc");
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return increment;
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}
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static inline int __atomic24_sub(int i, atomic24_t *v)
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{
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register volatile int *ptr asm("g1");
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register int increment asm("g2");
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register int tmp1 asm("g3");
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register int tmp2 asm("g4");
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register int tmp3 asm("g7");
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ptr = &v->counter;
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increment = i;
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__asm__ __volatile__(
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"mov %%o7, %%g4\n\t"
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"call ___atomic24_sub\n\t"
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" add %%o7, 8, %%o7\n"
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: "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)
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: "0" (increment), "r" (ptr)
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: "memory", "cc");
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return increment;
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}
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#define atomic24_add(i, v) ((void)__atomic24_add((i), (v)))
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#define atomic24_sub(i, v) ((void)__atomic24_sub((i), (v)))
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#define atomic24_dec_return(v) __atomic24_sub(1, (v))
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#define atomic24_inc_return(v) __atomic24_add(1, (v))
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#define atomic24_sub_and_test(i, v) (__atomic24_sub((i), (v)) == 0)
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#define atomic24_dec_and_test(v) (__atomic24_sub(1, (v)) == 0)
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#define atomic24_inc(v) ((void)__atomic24_add(1, (v)))
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#define atomic24_dec(v) ((void)__atomic24_sub(1, (v)))
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#define atomic24_add_negative(i, v) (__atomic24_add((i), (v)) < 0)
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/* Atomic operations are already serializing */
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#define smp_mb__before_atomic_dec() barrier()
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#define smp_mb__after_atomic_dec() barrier()
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#define smp_mb__before_atomic_inc() barrier()
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#define smp_mb__after_atomic_inc() barrier()
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#endif /* !(__KERNEL__) */
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#include <asm-generic/atomic.h>
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#endif /* !(__ARCH_SPARC_ATOMIC__) */
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