537 строки
14 KiB
C
537 строки
14 KiB
C
/* Geode LX framebuffer driver
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*
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* Copyright (C) 2006-2007, Advanced Micro Devices,Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/fb.h>
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#include <linux/uaccess.h>
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#include <linux/delay.h>
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#include "lxfb.h"
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/* TODO
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* Support panel scaling
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* Add acceleration
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* Add support for interlacing (TV out)
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* Support compression
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*/
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/* This is the complete list of PLL frequencies that we can set -
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* we will choose the closest match to the incoming clock.
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* freq is the frequency of the dotclock * 1000 (for example,
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* 24823 = 24.983 Mhz).
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* pllval is the corresponding PLL value
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*/
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static const struct {
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unsigned int pllval;
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unsigned int freq;
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} pll_table[] = {
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{ 0x000031AC, 24923 },
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{ 0x0000215D, 25175 },
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{ 0x00001087, 27000 },
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{ 0x0000216C, 28322 },
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{ 0x0000218D, 28560 },
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{ 0x000010C9, 31200 },
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{ 0x00003147, 31500 },
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{ 0x000010A7, 33032 },
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{ 0x00002159, 35112 },
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{ 0x00004249, 35500 },
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{ 0x00000057, 36000 },
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{ 0x0000219A, 37889 },
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{ 0x00002158, 39168 },
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{ 0x00000045, 40000 },
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{ 0x00000089, 43163 },
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{ 0x000010E7, 44900 },
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{ 0x00002136, 45720 },
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{ 0x00003207, 49500 },
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{ 0x00002187, 50000 },
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{ 0x00004286, 56250 },
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{ 0x000010E5, 60065 },
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{ 0x00004214, 65000 },
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{ 0x00001105, 68179 },
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{ 0x000031E4, 74250 },
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{ 0x00003183, 75000 },
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{ 0x00004284, 78750 },
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{ 0x00001104, 81600 },
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{ 0x00006363, 94500 },
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{ 0x00005303, 97520 },
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{ 0x00002183, 100187 },
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{ 0x00002122, 101420 },
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{ 0x00001081, 108000 },
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{ 0x00006201, 113310 },
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{ 0x00000041, 119650 },
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{ 0x000041A1, 129600 },
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{ 0x00002182, 133500 },
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{ 0x000041B1, 135000 },
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{ 0x00000051, 144000 },
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{ 0x000041E1, 148500 },
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{ 0x000062D1, 157500 },
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{ 0x000031A1, 162000 },
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{ 0x00000061, 169203 },
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{ 0x00004231, 172800 },
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{ 0x00002151, 175500 },
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{ 0x000052E1, 189000 },
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{ 0x00000071, 192000 },
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{ 0x00003201, 198000 },
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{ 0x00004291, 202500 },
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{ 0x00001101, 204750 },
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{ 0x00007481, 218250 },
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{ 0x00004170, 229500 },
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{ 0x00006210, 234000 },
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{ 0x00003140, 251182 },
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{ 0x00006250, 261000 },
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{ 0x000041C0, 278400 },
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{ 0x00005220, 280640 },
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{ 0x00000050, 288000 },
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{ 0x000041E0, 297000 },
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{ 0x00002130, 320207 }
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};
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static void lx_set_dotpll(u32 pllval)
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{
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u32 dotpll_lo, dotpll_hi;
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int i;
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rdmsr(MSR_LX_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
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if ((dotpll_lo & GLCP_DOTPLL_LOCK) && (dotpll_hi == pllval))
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return;
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dotpll_hi = pllval;
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dotpll_lo &= ~(GLCP_DOTPLL_BYPASS | GLCP_DOTPLL_HALFPIX);
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dotpll_lo |= GLCP_DOTPLL_RESET;
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wrmsr(MSR_LX_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
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/* Wait 100us for the PLL to lock */
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udelay(100);
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/* Now, loop for the lock bit */
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for (i = 0; i < 1000; i++) {
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rdmsr(MSR_LX_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
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if (dotpll_lo & GLCP_DOTPLL_LOCK)
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break;
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}
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/* Clear the reset bit */
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dotpll_lo &= ~GLCP_DOTPLL_RESET;
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wrmsr(MSR_LX_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
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}
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/* Set the clock based on the frequency specified by the current mode */
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static void lx_set_clock(struct fb_info *info)
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{
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unsigned int diff, min, best = 0;
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unsigned int freq, i;
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freq = (unsigned int) (0x3b9aca00 / info->var.pixclock);
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min = abs(pll_table[0].freq - freq);
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for (i = 0; i < ARRAY_SIZE(pll_table); i++) {
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diff = abs(pll_table[i].freq - freq);
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if (diff < min) {
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min = diff;
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best = i;
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}
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}
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lx_set_dotpll(pll_table[best].pllval & 0x7FFF);
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}
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static void lx_graphics_disable(struct fb_info *info)
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{
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struct lxfb_par *par = info->par;
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unsigned int val, gcfg;
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/* Note: This assumes that the video is in a quitet state */
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writel(0, par->df_regs + DF_ALPHA_CONTROL_1);
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writel(0, par->df_regs + DF_ALPHA_CONTROL_1 + 32);
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writel(0, par->df_regs + DF_ALPHA_CONTROL_1 + 64);
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/* Turn off the VGA and video enable */
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val = readl (par->dc_regs + DC_GENERAL_CFG) &
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~(DC_GCFG_VGAE | DC_GCFG_VIDE);
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writel(val, par->dc_regs + DC_GENERAL_CFG);
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val = readl(par->df_regs + DF_VIDEO_CFG) & ~DF_VCFG_VID_EN;
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writel(val, par->df_regs + DF_VIDEO_CFG);
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writel( DC_IRQ_MASK | DC_VSYNC_IRQ_MASK |
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DC_IRQ_STATUS | DC_VSYNC_IRQ_STATUS,
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par->dc_regs + DC_IRQ);
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val = readl(par->dc_regs + DC_GENLCK_CTRL) & ~DC_GENLCK_ENABLE;
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writel(val, par->dc_regs + DC_GENLCK_CTRL);
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val = readl(par->dc_regs + DC_COLOR_KEY) & ~DC_CLR_KEY_ENABLE;
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writel(val & ~DC_CLR_KEY_ENABLE, par->dc_regs + DC_COLOR_KEY);
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/* We don't actually blank the panel, due to the long latency
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involved with bringing it back */
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val = readl(par->df_regs + DF_MISC) | DF_MISC_DAC_PWRDN;
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writel(val, par->df_regs + DF_MISC);
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/* Turn off the display */
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val = readl(par->df_regs + DF_DISPLAY_CFG);
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writel(val & ~(DF_DCFG_CRT_EN | DF_DCFG_HSYNC_EN | DF_DCFG_VSYNC_EN |
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DF_DCFG_DAC_BL_EN), par->df_regs + DF_DISPLAY_CFG);
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gcfg = readl(par->dc_regs + DC_GENERAL_CFG);
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gcfg &= ~(DC_GCFG_CMPE | DC_GCFG_DECE);
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writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
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/* Turn off the TGEN */
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val = readl(par->dc_regs + DC_DISPLAY_CFG);
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val &= ~DC_DCFG_TGEN;
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writel(val, par->dc_regs + DC_DISPLAY_CFG);
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/* Wait 1000 usecs to ensure that the TGEN is clear */
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udelay(1000);
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/* Turn off the FIFO loader */
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gcfg &= ~DC_GCFG_DFLE;
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writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
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/* Lastly, wait for the GP to go idle */
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do {
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val = readl(par->gp_regs + GP_BLT_STATUS);
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} while ((val & GP_BS_BLT_BUSY) || !(val & GP_BS_CB_EMPTY));
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}
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static void lx_graphics_enable(struct fb_info *info)
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{
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struct lxfb_par *par = info->par;
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u32 temp, config;
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/* Set the video request register */
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writel(0, par->df_regs + DF_VIDEO_REQUEST);
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/* Set up the polarities */
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config = readl(par->df_regs + DF_DISPLAY_CFG);
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config &= ~(DF_DCFG_CRT_SYNC_SKW_MASK | DF_DCFG_PWR_SEQ_DLY_MASK |
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DF_DCFG_CRT_HSYNC_POL | DF_DCFG_CRT_VSYNC_POL);
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config |= (DF_DCFG_CRT_SYNC_SKW_INIT | DF_DCFG_PWR_SEQ_DLY_INIT |
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DF_DCFG_GV_PAL_BYP);
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if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
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config |= DF_DCFG_CRT_HSYNC_POL;
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if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
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config |= DF_DCFG_CRT_VSYNC_POL;
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if (par->output & OUTPUT_PANEL) {
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u32 msrlo, msrhi;
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writel(DF_DEFAULT_TFT_PMTIM1,
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par->df_regs + DF_PANEL_TIM1);
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writel(DF_DEFAULT_TFT_PMTIM2,
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par->df_regs + DF_PANEL_TIM2);
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writel(DF_DEFAULT_TFT_DITHCTL,
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par->df_regs + DF_DITHER_CONTROL);
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msrlo = DF_DEFAULT_TFT_PAD_SEL_LOW;
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msrhi = DF_DEFAULT_TFT_PAD_SEL_HIGH;
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wrmsr(MSR_LX_DF_PADSEL, msrlo, msrhi);
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}
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if (par->output & OUTPUT_CRT) {
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config |= DF_DCFG_CRT_EN | DF_DCFG_HSYNC_EN |
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DF_DCFG_VSYNC_EN | DF_DCFG_DAC_BL_EN;
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}
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writel(config, par->df_regs + DF_DISPLAY_CFG);
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/* Turn the CRT dacs back on */
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if (par->output & OUTPUT_CRT) {
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temp = readl(par->df_regs + DF_MISC);
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temp &= ~(DF_MISC_DAC_PWRDN | DF_MISC_A_PWRDN);
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writel(temp, par->df_regs + DF_MISC);
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}
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/* Turn the panel on (if it isn't already) */
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if (par->output & OUTPUT_PANEL) {
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temp = readl(par->df_regs + DF_FP_PM);
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if (!(temp & 0x09))
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writel(temp | DF_FP_PM_P, par->df_regs + DF_FP_PM);
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}
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temp = readl(par->df_regs + DF_MISC);
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temp = readl(par->df_regs + DF_DISPLAY_CFG);
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}
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unsigned int lx_framebuffer_size(void)
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{
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unsigned int val;
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/* The frame buffer size is reported by a VSM in VSA II */
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/* Virtual Register Class = 0x02 */
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/* VG_MEM_SIZE (1MB units) = 0x00 */
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outw(0xFC53, 0xAC1C);
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outw(0x0200, 0xAC1C);
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val = (unsigned int)(inw(0xAC1E)) & 0xFE;
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return (val << 20);
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}
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void lx_set_mode(struct fb_info *info)
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{
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struct lxfb_par *par = info->par;
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u64 msrval;
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unsigned int max, dv, val, size;
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unsigned int gcfg, dcfg;
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int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
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int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
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/* Unlock the DC registers */
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writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK);
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lx_graphics_disable(info);
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lx_set_clock(info);
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/* Set output mode */
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rdmsrl(MSR_LX_DF_GLCONFIG, msrval);
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msrval &= ~DF_CONFIG_OUTPUT_MASK;
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if (par->output & OUTPUT_PANEL) {
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msrval |= DF_OUTPUT_PANEL;
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if (par->output & OUTPUT_CRT)
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msrval |= DF_SIMULTANEOUS_CRT_AND_FP;
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else
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msrval &= ~DF_SIMULTANEOUS_CRT_AND_FP;
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} else {
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msrval |= DF_OUTPUT_CRT;
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}
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wrmsrl(MSR_LX_DF_GLCONFIG, msrval);
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/* Clear the various buffers */
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/* FIXME: Adjust for panning here */
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writel(0, par->dc_regs + DC_FB_START);
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writel(0, par->dc_regs + DC_CB_START);
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writel(0, par->dc_regs + DC_CURSOR_START);
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/* FIXME: Add support for interlacing */
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/* FIXME: Add support for scaling */
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val = readl(par->dc_regs + DC_GENLCK_CTRL);
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val &= ~(DC_GC_ALPHA_FLICK_ENABLE |
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DC_GC_FLICKER_FILTER_ENABLE | DC_GC_FLICKER_FILTER_MASK);
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/* Default scaling params */
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writel((0x4000 << 16) | 0x4000, par->dc_regs + DC_GFX_SCALE);
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writel(0, par->dc_regs + DC_IRQ_FILT_CTL);
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writel(val, par->dc_regs + DC_GENLCK_CTRL);
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/* FIXME: Support compression */
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if (info->fix.line_length > 4096)
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dv = DC_DV_LINE_SIZE_8192;
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else if (info->fix.line_length > 2048)
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dv = DC_DV_LINE_SIZE_4096;
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else if (info->fix.line_length > 1024)
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dv = DC_DV_LINE_SIZE_2048;
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else
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dv = DC_DV_LINE_SIZE_1024;
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max = info->fix.line_length * info->var.yres;
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max = (max + 0x3FF) & 0xFFFFFC00;
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writel(max | DC_DV_TOP_ENABLE, par->dc_regs + DC_DV_TOP);
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val = readl(par->dc_regs + DC_DV_CTL) & ~DC_DV_LINE_SIZE_MASK;
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writel(val | dv, par->dc_regs + DC_DV_CTL);
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size = info->var.xres * (info->var.bits_per_pixel >> 3);
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writel(info->fix.line_length >> 3, par->dc_regs + DC_GRAPHICS_PITCH);
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writel((size + 7) >> 3, par->dc_regs + DC_LINE_SIZE);
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/* Set default watermark values */
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rdmsrl(MSR_LX_DC_SPARE, msrval);
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msrval &= ~(DC_SPARE_DISABLE_CFIFO_HGO | DC_SPARE_VFIFO_ARB_SELECT |
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DC_SPARE_LOAD_WM_LPEN_MASK | DC_SPARE_WM_LPEN_OVRD |
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DC_SPARE_DISABLE_INIT_VID_PRI | DC_SPARE_DISABLE_VFIFO_WM);
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msrval |= DC_SPARE_DISABLE_VFIFO_WM | DC_SPARE_DISABLE_INIT_VID_PRI;
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wrmsrl(MSR_LX_DC_SPARE, msrval);
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gcfg = DC_GCFG_DFLE; /* Display fifo enable */
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gcfg |= 0xB600; /* Set default priority */
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gcfg |= DC_GCFG_FDTY; /* Set the frame dirty mode */
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dcfg = DC_DCFG_VDEN; /* Enable video data */
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dcfg |= DC_DCFG_GDEN; /* Enable graphics */
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dcfg |= DC_DCFG_TGEN; /* Turn on the timing generator */
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dcfg |= DC_DCFG_TRUP; /* Update timings immediately */
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dcfg |= DC_DCFG_PALB; /* Palette bypass in > 8 bpp modes */
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dcfg |= DC_DCFG_VISL;
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dcfg |= DC_DCFG_DCEN; /* Always center the display */
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/* Set the current BPP mode */
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switch (info->var.bits_per_pixel) {
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case 8:
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dcfg |= DC_DCFG_DISP_MODE_8BPP;
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break;
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case 16:
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dcfg |= DC_DCFG_DISP_MODE_16BPP | DC_DCFG_16BPP;
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break;
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case 32:
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case 24:
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dcfg |= DC_DCFG_DISP_MODE_24BPP;
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break;
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}
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/* Now - set up the timings */
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hactive = info->var.xres;
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hblankstart = hactive;
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hsyncstart = hblankstart + info->var.right_margin;
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hsyncend = hsyncstart + info->var.hsync_len;
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hblankend = hsyncend + info->var.left_margin;
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htotal = hblankend;
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vactive = info->var.yres;
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vblankstart = vactive;
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vsyncstart = vblankstart + info->var.lower_margin;
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vsyncend = vsyncstart + info->var.vsync_len;
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vblankend = vsyncend + info->var.upper_margin;
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vtotal = vblankend;
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writel((hactive - 1) | ((htotal - 1) << 16),
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par->dc_regs + DC_H_ACTIVE_TIMING);
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writel((hblankstart - 1) | ((hblankend - 1) << 16),
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par->dc_regs + DC_H_BLANK_TIMING);
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writel((hsyncstart - 1) | ((hsyncend - 1) << 16),
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par->dc_regs + DC_H_SYNC_TIMING);
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writel((vactive - 1) | ((vtotal - 1) << 16),
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par->dc_regs + DC_V_ACTIVE_TIMING);
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writel((vblankstart - 1) | ((vblankend - 1) << 16),
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par->dc_regs + DC_V_BLANK_TIMING);
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writel((vsyncstart - 1) | ((vsyncend - 1) << 16),
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par->dc_regs + DC_V_SYNC_TIMING);
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writel( (info->var.xres - 1) << 16 | (info->var.yres - 1),
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par->dc_regs + DC_FB_ACTIVE);
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/* And re-enable the graphics output */
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lx_graphics_enable(info);
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/* Write the two main configuration registers */
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writel(dcfg, par->dc_regs + DC_DISPLAY_CFG);
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writel(0, par->dc_regs + DC_ARB_CFG);
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writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
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/* Lock the DC registers */
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writel(0, par->dc_regs + DC_UNLOCK);
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}
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void lx_set_palette_reg(struct fb_info *info, unsigned regno,
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unsigned red, unsigned green, unsigned blue)
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{
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struct lxfb_par *par = info->par;
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int val;
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/* Hardware palette is in RGB 8-8-8 format. */
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val = (red << 8) & 0xff0000;
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val |= (green) & 0x00ff00;
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val |= (blue >> 8) & 0x0000ff;
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writel(regno, par->dc_regs + DC_PAL_ADDRESS);
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writel(val, par->dc_regs + DC_PAL_DATA);
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}
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int lx_blank_display(struct fb_info *info, int blank_mode)
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{
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struct lxfb_par *par = info->par;
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u32 dcfg, fp_pm;
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int blank, hsync, vsync;
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/* CRT power saving modes. */
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switch (blank_mode) {
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case FB_BLANK_UNBLANK:
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blank = 0; hsync = 1; vsync = 1;
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break;
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case FB_BLANK_NORMAL:
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blank = 1; hsync = 1; vsync = 1;
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break;
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case FB_BLANK_VSYNC_SUSPEND:
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blank = 1; hsync = 1; vsync = 0;
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break;
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case FB_BLANK_HSYNC_SUSPEND:
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blank = 1; hsync = 0; vsync = 1;
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break;
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case FB_BLANK_POWERDOWN:
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blank = 1; hsync = 0; vsync = 0;
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break;
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default:
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return -EINVAL;
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}
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dcfg = readl(par->df_regs + DF_DISPLAY_CFG);
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dcfg &= ~(DF_DCFG_DAC_BL_EN
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| DF_DCFG_HSYNC_EN | DF_DCFG_VSYNC_EN);
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if (!blank)
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dcfg |= DF_DCFG_DAC_BL_EN;
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if (hsync)
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dcfg |= DF_DCFG_HSYNC_EN;
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if (vsync)
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dcfg |= DF_DCFG_VSYNC_EN;
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writel(dcfg, par->df_regs + DF_DISPLAY_CFG);
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/* Power on/off flat panel */
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if (par->output & OUTPUT_PANEL) {
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fp_pm = readl(par->df_regs + DF_FP_PM);
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if (blank_mode == FB_BLANK_POWERDOWN)
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fp_pm &= ~DF_FP_PM_P;
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else
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fp_pm |= DF_FP_PM_P;
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writel(fp_pm, par->df_regs + DF_FP_PM);
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}
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return 0;
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}
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