614 строки
17 KiB
C
614 строки
17 KiB
C
/*
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* Support PCI/PCIe on PowerNV platforms
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*
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* Currently supports only P5IOC2
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*
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* Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/msi.h>
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#include <asm/sections.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#include <asm/ppc-pci.h>
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#include <asm/opal.h>
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#include <asm/iommu.h>
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#include <asm/tce.h>
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#include <asm/firmware.h>
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#include "powernv.h"
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#include "pci.h"
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/* Delay in usec */
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#define PCI_RESET_DELAY_US 3000000
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#define cfg_dbg(fmt...) do { } while(0)
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//#define cfg_dbg(fmt...) printk(fmt)
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#ifdef CONFIG_PCI_MSI
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static int pnv_msi_check_device(struct pci_dev* pdev, int nvec, int type)
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{
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struct pci_controller *hose = pci_bus_to_host(pdev->bus);
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struct pnv_phb *phb = hose->private_data;
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return (phb && phb->msi_map) ? 0 : -ENODEV;
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}
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static unsigned int pnv_get_one_msi(struct pnv_phb *phb)
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{
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unsigned long flags;
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unsigned int id, rc;
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spin_lock_irqsave(&phb->lock, flags);
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id = find_next_zero_bit(phb->msi_map, phb->msi_count, phb->msi_next);
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if (id >= phb->msi_count && phb->msi_next)
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id = find_next_zero_bit(phb->msi_map, phb->msi_count, 0);
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if (id >= phb->msi_count) {
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rc = 0;
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goto out;
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}
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__set_bit(id, phb->msi_map);
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rc = id + phb->msi_base;
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out:
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spin_unlock_irqrestore(&phb->lock, flags);
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return rc;
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}
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static void pnv_put_msi(struct pnv_phb *phb, unsigned int hwirq)
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{
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unsigned long flags;
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unsigned int id;
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if (WARN_ON(hwirq < phb->msi_base ||
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hwirq >= (phb->msi_base + phb->msi_count)))
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return;
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id = hwirq - phb->msi_base;
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spin_lock_irqsave(&phb->lock, flags);
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__clear_bit(id, phb->msi_map);
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spin_unlock_irqrestore(&phb->lock, flags);
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}
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static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
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{
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struct pci_controller *hose = pci_bus_to_host(pdev->bus);
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struct pnv_phb *phb = hose->private_data;
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struct msi_desc *entry;
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struct msi_msg msg;
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unsigned int hwirq, virq;
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int rc;
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if (WARN_ON(!phb))
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return -ENODEV;
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list_for_each_entry(entry, &pdev->msi_list, list) {
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if (!entry->msi_attrib.is_64 && !phb->msi32_support) {
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pr_warn("%s: Supports only 64-bit MSIs\n",
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pci_name(pdev));
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return -ENXIO;
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}
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hwirq = pnv_get_one_msi(phb);
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if (!hwirq) {
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pr_warn("%s: Failed to find a free MSI\n",
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pci_name(pdev));
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return -ENOSPC;
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}
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virq = irq_create_mapping(NULL, hwirq);
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if (virq == NO_IRQ) {
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pr_warn("%s: Failed to map MSI to linux irq\n",
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pci_name(pdev));
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pnv_put_msi(phb, hwirq);
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return -ENOMEM;
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}
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rc = phb->msi_setup(phb, pdev, hwirq, entry->msi_attrib.is_64,
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&msg);
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if (rc) {
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pr_warn("%s: Failed to setup MSI\n", pci_name(pdev));
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irq_dispose_mapping(virq);
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pnv_put_msi(phb, hwirq);
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return rc;
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}
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irq_set_msi_desc(virq, entry);
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write_msi_msg(virq, &msg);
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}
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return 0;
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}
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static void pnv_teardown_msi_irqs(struct pci_dev *pdev)
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{
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struct pci_controller *hose = pci_bus_to_host(pdev->bus);
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struct pnv_phb *phb = hose->private_data;
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struct msi_desc *entry;
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if (WARN_ON(!phb))
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return;
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list_for_each_entry(entry, &pdev->msi_list, list) {
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if (entry->irq == NO_IRQ)
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continue;
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irq_set_msi_desc(entry->irq, NULL);
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pnv_put_msi(phb, virq_to_hw(entry->irq));
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irq_dispose_mapping(entry->irq);
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}
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}
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#endif /* CONFIG_PCI_MSI */
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static void pnv_pci_dump_p7ioc_diag_data(struct pnv_phb *phb)
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{
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struct OpalIoP7IOCPhbErrorData *data = &phb->diag.p7ioc;
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int i;
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pr_info("PHB %d diagnostic data:\n", phb->hose->global_number);
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pr_info(" brdgCtl = 0x%08x\n", data->brdgCtl);
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pr_info(" portStatusReg = 0x%08x\n", data->portStatusReg);
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pr_info(" rootCmplxStatus = 0x%08x\n", data->rootCmplxStatus);
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pr_info(" busAgentStatus = 0x%08x\n", data->busAgentStatus);
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pr_info(" deviceStatus = 0x%08x\n", data->deviceStatus);
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pr_info(" slotStatus = 0x%08x\n", data->slotStatus);
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pr_info(" linkStatus = 0x%08x\n", data->linkStatus);
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pr_info(" devCmdStatus = 0x%08x\n", data->devCmdStatus);
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pr_info(" devSecStatus = 0x%08x\n", data->devSecStatus);
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pr_info(" rootErrorStatus = 0x%08x\n", data->rootErrorStatus);
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pr_info(" uncorrErrorStatus = 0x%08x\n", data->uncorrErrorStatus);
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pr_info(" corrErrorStatus = 0x%08x\n", data->corrErrorStatus);
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pr_info(" tlpHdr1 = 0x%08x\n", data->tlpHdr1);
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pr_info(" tlpHdr2 = 0x%08x\n", data->tlpHdr2);
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pr_info(" tlpHdr3 = 0x%08x\n", data->tlpHdr3);
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pr_info(" tlpHdr4 = 0x%08x\n", data->tlpHdr4);
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pr_info(" sourceId = 0x%08x\n", data->sourceId);
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pr_info(" errorClass = 0x%016llx\n", data->errorClass);
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pr_info(" correlator = 0x%016llx\n", data->correlator);
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pr_info(" p7iocPlssr = 0x%016llx\n", data->p7iocPlssr);
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pr_info(" p7iocCsr = 0x%016llx\n", data->p7iocCsr);
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pr_info(" lemFir = 0x%016llx\n", data->lemFir);
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pr_info(" lemErrorMask = 0x%016llx\n", data->lemErrorMask);
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pr_info(" lemWOF = 0x%016llx\n", data->lemWOF);
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pr_info(" phbErrorStatus = 0x%016llx\n", data->phbErrorStatus);
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pr_info(" phbFirstErrorStatus = 0x%016llx\n", data->phbFirstErrorStatus);
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pr_info(" phbErrorLog0 = 0x%016llx\n", data->phbErrorLog0);
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pr_info(" phbErrorLog1 = 0x%016llx\n", data->phbErrorLog1);
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pr_info(" mmioErrorStatus = 0x%016llx\n", data->mmioErrorStatus);
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pr_info(" mmioFirstErrorStatus = 0x%016llx\n", data->mmioFirstErrorStatus);
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pr_info(" mmioErrorLog0 = 0x%016llx\n", data->mmioErrorLog0);
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pr_info(" mmioErrorLog1 = 0x%016llx\n", data->mmioErrorLog1);
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pr_info(" dma0ErrorStatus = 0x%016llx\n", data->dma0ErrorStatus);
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pr_info(" dma0FirstErrorStatus = 0x%016llx\n", data->dma0FirstErrorStatus);
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pr_info(" dma0ErrorLog0 = 0x%016llx\n", data->dma0ErrorLog0);
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pr_info(" dma0ErrorLog1 = 0x%016llx\n", data->dma0ErrorLog1);
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pr_info(" dma1ErrorStatus = 0x%016llx\n", data->dma1ErrorStatus);
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pr_info(" dma1FirstErrorStatus = 0x%016llx\n", data->dma1FirstErrorStatus);
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pr_info(" dma1ErrorLog0 = 0x%016llx\n", data->dma1ErrorLog0);
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pr_info(" dma1ErrorLog1 = 0x%016llx\n", data->dma1ErrorLog1);
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for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) {
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if ((data->pestA[i] >> 63) == 0 &&
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(data->pestB[i] >> 63) == 0)
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continue;
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pr_info(" PE[%3d] PESTA = 0x%016llx\n", i, data->pestA[i]);
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pr_info(" PESTB = 0x%016llx\n", data->pestB[i]);
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}
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}
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static void pnv_pci_dump_phb_diag_data(struct pnv_phb *phb)
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{
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switch(phb->model) {
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case PNV_PHB_MODEL_P7IOC:
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pnv_pci_dump_p7ioc_diag_data(phb);
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break;
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default:
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pr_warning("PCI %d: Can't decode this PHB diag data\n",
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phb->hose->global_number);
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}
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}
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static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no)
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{
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unsigned long flags, rc;
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int has_diag;
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spin_lock_irqsave(&phb->lock, flags);
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rc = opal_pci_get_phb_diag_data(phb->opal_id, phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE);
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has_diag = (rc == OPAL_SUCCESS);
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rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
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OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
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if (rc) {
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pr_warning("PCI %d: Failed to clear EEH freeze state"
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" for PE#%d, err %ld\n",
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phb->hose->global_number, pe_no, rc);
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/* For now, let's only display the diag buffer when we fail to clear
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* the EEH status. We'll do more sensible things later when we have
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* proper EEH support. We need to make sure we don't pollute ourselves
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* with the normal errors generated when probing empty slots
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*/
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if (has_diag)
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pnv_pci_dump_phb_diag_data(phb);
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else
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pr_warning("PCI %d: No diag data available\n",
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phb->hose->global_number);
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}
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spin_unlock_irqrestore(&phb->lock, flags);
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}
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static void pnv_pci_config_check_eeh(struct pnv_phb *phb, struct pci_bus *bus,
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u32 bdfn)
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{
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s64 rc;
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u8 fstate;
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u16 pcierr;
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u32 pe_no;
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/* Get PE# if we support IODA */
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pe_no = phb->bdfn_to_pe ? phb->bdfn_to_pe(phb, bus, bdfn & 0xff) : 0;
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/* Read freeze status */
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rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, &fstate, &pcierr,
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NULL);
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if (rc) {
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pr_warning("PCI %d: Failed to read EEH status for PE#%d,"
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" err %lld\n", phb->hose->global_number, pe_no, rc);
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return;
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}
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cfg_dbg(" -> EEH check, bdfn=%04x PE%d fstate=%x\n",
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bdfn, pe_no, fstate);
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if (fstate != 0)
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pnv_pci_handle_eeh_config(phb, pe_no);
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}
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static int pnv_pci_read_config(struct pci_bus *bus,
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unsigned int devfn,
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int where, int size, u32 *val)
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{
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struct pci_controller *hose = pci_bus_to_host(bus);
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struct pnv_phb *phb = hose->private_data;
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u32 bdfn = (((uint64_t)bus->number) << 8) | devfn;
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s64 rc;
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if (hose == NULL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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switch (size) {
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case 1: {
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u8 v8;
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rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8);
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*val = (rc == OPAL_SUCCESS) ? v8 : 0xff;
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break;
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}
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case 2: {
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u16 v16;
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rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where,
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&v16);
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*val = (rc == OPAL_SUCCESS) ? v16 : 0xffff;
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break;
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}
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case 4: {
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u32 v32;
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rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32);
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*val = (rc == OPAL_SUCCESS) ? v32 : 0xffffffff;
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break;
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}
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default:
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return PCIBIOS_FUNC_NOT_SUPPORTED;
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}
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cfg_dbg("pnv_pci_read_config bus: %x devfn: %x +%x/%x -> %08x\n",
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bus->number, devfn, where, size, *val);
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/* Check if the PHB got frozen due to an error (no response) */
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pnv_pci_config_check_eeh(phb, bus, bdfn);
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return PCIBIOS_SUCCESSFUL;
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}
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static int pnv_pci_write_config(struct pci_bus *bus,
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unsigned int devfn,
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int where, int size, u32 val)
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{
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struct pci_controller *hose = pci_bus_to_host(bus);
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struct pnv_phb *phb = hose->private_data;
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u32 bdfn = (((uint64_t)bus->number) << 8) | devfn;
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if (hose == NULL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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cfg_dbg("pnv_pci_write_config bus: %x devfn: %x +%x/%x -> %08x\n",
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bus->number, devfn, where, size, val);
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switch (size) {
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case 1:
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opal_pci_config_write_byte(phb->opal_id, bdfn, where, val);
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break;
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case 2:
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opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val);
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break;
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case 4:
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opal_pci_config_write_word(phb->opal_id, bdfn, where, val);
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break;
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default:
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return PCIBIOS_FUNC_NOT_SUPPORTED;
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}
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/* Check if the PHB got frozen due to an error (no response) */
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pnv_pci_config_check_eeh(phb, bus, bdfn);
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops pnv_pci_ops = {
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.read = pnv_pci_read_config,
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.write = pnv_pci_write_config,
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};
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static void pnv_tce_invalidate(struct iommu_table *tbl,
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u64 *startp, u64 *endp)
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{
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u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index;
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unsigned long start, end, inc;
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start = __pa(startp);
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end = __pa(endp);
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/* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
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if (tbl->it_busno) {
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start <<= 12;
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end <<= 12;
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inc = 128 << 12;
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start |= tbl->it_busno;
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end |= tbl->it_busno;
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}
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/* p7ioc-style invalidation, 2 TCEs per write */
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else if (tbl->it_type & TCE_PCI_SWINV_PAIR) {
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start |= (1ull << 63);
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end |= (1ull << 63);
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inc = 16;
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}
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/* Default (older HW) */
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else
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inc = 128;
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end |= inc - 1; /* round up end to be different than start */
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mb(); /* Ensure above stores are visible */
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while (start <= end) {
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__raw_writeq(start, invalidate);
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start += inc;
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}
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/* The iommu layer will do another mb() for us on build() and
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* we don't care on free()
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*/
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}
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static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
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unsigned long uaddr, enum dma_data_direction direction,
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struct dma_attrs *attrs)
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{
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u64 proto_tce;
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u64 *tcep, *tces;
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u64 rpn;
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proto_tce = TCE_PCI_READ; // Read allowed
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if (direction != DMA_TO_DEVICE)
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proto_tce |= TCE_PCI_WRITE;
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tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset;
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rpn = __pa(uaddr) >> TCE_SHIFT;
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while (npages--)
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*(tcep++) = proto_tce | (rpn++ << TCE_RPN_SHIFT);
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/* Some implementations won't cache invalid TCEs and thus may not
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* need that flush. We'll probably turn it_type into a bit mask
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* of flags if that becomes the case
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*/
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if (tbl->it_type & TCE_PCI_SWINV_CREATE)
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pnv_tce_invalidate(tbl, tces, tcep - 1);
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return 0;
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}
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static void pnv_tce_free(struct iommu_table *tbl, long index, long npages)
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{
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u64 *tcep, *tces;
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tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset;
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while (npages--)
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*(tcep++) = 0;
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if (tbl->it_type & TCE_PCI_SWINV_FREE)
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pnv_tce_invalidate(tbl, tces, tcep - 1);
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}
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static unsigned long pnv_tce_get(struct iommu_table *tbl, long index)
|
|
{
|
|
return ((u64 *)tbl->it_base)[index - tbl->it_offset];
|
|
}
|
|
|
|
void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
|
|
void *tce_mem, u64 tce_size,
|
|
u64 dma_offset)
|
|
{
|
|
tbl->it_blocksize = 16;
|
|
tbl->it_base = (unsigned long)tce_mem;
|
|
tbl->it_offset = dma_offset >> IOMMU_PAGE_SHIFT;
|
|
tbl->it_index = 0;
|
|
tbl->it_size = tce_size >> 3;
|
|
tbl->it_busno = 0;
|
|
tbl->it_type = TCE_PCI;
|
|
}
|
|
|
|
static struct iommu_table *pnv_pci_setup_bml_iommu(struct pci_controller *hose)
|
|
{
|
|
struct iommu_table *tbl;
|
|
const __be64 *basep, *swinvp;
|
|
const __be32 *sizep;
|
|
|
|
basep = of_get_property(hose->dn, "linux,tce-base", NULL);
|
|
sizep = of_get_property(hose->dn, "linux,tce-size", NULL);
|
|
if (basep == NULL || sizep == NULL) {
|
|
pr_err("PCI: %s has missing tce entries !\n",
|
|
hose->dn->full_name);
|
|
return NULL;
|
|
}
|
|
tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node);
|
|
if (WARN_ON(!tbl))
|
|
return NULL;
|
|
pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)),
|
|
be32_to_cpup(sizep), 0);
|
|
iommu_init_table(tbl, hose->node);
|
|
|
|
/* Deal with SW invalidated TCEs when needed (BML way) */
|
|
swinvp = of_get_property(hose->dn, "linux,tce-sw-invalidate-info",
|
|
NULL);
|
|
if (swinvp) {
|
|
tbl->it_busno = swinvp[1];
|
|
tbl->it_index = (unsigned long)ioremap(swinvp[0], 8);
|
|
tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
|
|
}
|
|
return tbl;
|
|
}
|
|
|
|
static void pnv_pci_dma_fallback_setup(struct pci_controller *hose,
|
|
struct pci_dev *pdev)
|
|
{
|
|
struct device_node *np = pci_bus_to_OF_node(hose->bus);
|
|
struct pci_dn *pdn;
|
|
|
|
if (np == NULL)
|
|
return;
|
|
pdn = PCI_DN(np);
|
|
if (!pdn->iommu_table)
|
|
pdn->iommu_table = pnv_pci_setup_bml_iommu(hose);
|
|
if (!pdn->iommu_table)
|
|
return;
|
|
set_iommu_table_base(&pdev->dev, pdn->iommu_table);
|
|
}
|
|
|
|
static void pnv_pci_dma_dev_setup(struct pci_dev *pdev)
|
|
{
|
|
struct pci_controller *hose = pci_bus_to_host(pdev->bus);
|
|
struct pnv_phb *phb = hose->private_data;
|
|
|
|
/* If we have no phb structure, try to setup a fallback based on
|
|
* the device-tree (RTAS PCI for example)
|
|
*/
|
|
if (phb && phb->dma_dev_setup)
|
|
phb->dma_dev_setup(phb, pdev);
|
|
else
|
|
pnv_pci_dma_fallback_setup(hose, pdev);
|
|
}
|
|
|
|
/* Fixup wrong class code in p7ioc root complex */
|
|
static void pnv_p7ioc_rc_quirk(struct pci_dev *dev)
|
|
{
|
|
dev->class = PCI_CLASS_BRIDGE_PCI << 8;
|
|
}
|
|
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk);
|
|
|
|
static int pnv_pci_probe_mode(struct pci_bus *bus)
|
|
{
|
|
struct pci_controller *hose = pci_bus_to_host(bus);
|
|
const __be64 *tstamp;
|
|
u64 now, target;
|
|
|
|
|
|
/* We hijack this as a way to ensure we have waited long
|
|
* enough since the reset was lifted on the PCI bus
|
|
*/
|
|
if (bus != hose->bus)
|
|
return PCI_PROBE_NORMAL;
|
|
tstamp = of_get_property(hose->dn, "reset-clear-timestamp", NULL);
|
|
if (!tstamp || !*tstamp)
|
|
return PCI_PROBE_NORMAL;
|
|
|
|
now = mftb() / tb_ticks_per_usec;
|
|
target = (be64_to_cpup(tstamp) / tb_ticks_per_usec)
|
|
+ PCI_RESET_DELAY_US;
|
|
|
|
pr_devel("pci %04d: Reset target: 0x%llx now: 0x%llx\n",
|
|
hose->global_number, target, now);
|
|
|
|
if (now < target)
|
|
msleep((target - now + 999) / 1000);
|
|
|
|
return PCI_PROBE_NORMAL;
|
|
}
|
|
|
|
void __init pnv_pci_init(void)
|
|
{
|
|
struct device_node *np;
|
|
|
|
pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN);
|
|
|
|
/* OPAL absent, try POPAL first then RTAS detection of PHBs */
|
|
if (!firmware_has_feature(FW_FEATURE_OPAL)) {
|
|
#ifdef CONFIG_PPC_POWERNV_RTAS
|
|
init_pci_config_tokens();
|
|
find_and_init_phbs();
|
|
#endif /* CONFIG_PPC_POWERNV_RTAS */
|
|
}
|
|
/* OPAL is here, do our normal stuff */
|
|
else {
|
|
int found_ioda = 0;
|
|
|
|
/* Look for IODA IO-Hubs. We don't support mixing IODA
|
|
* and p5ioc2 due to the need to change some global
|
|
* probing flags
|
|
*/
|
|
for_each_compatible_node(np, NULL, "ibm,ioda-hub") {
|
|
pnv_pci_init_ioda_hub(np);
|
|
found_ioda = 1;
|
|
}
|
|
|
|
/* Look for p5ioc2 IO-Hubs */
|
|
if (!found_ioda)
|
|
for_each_compatible_node(np, NULL, "ibm,p5ioc2")
|
|
pnv_pci_init_p5ioc2_hub(np);
|
|
}
|
|
|
|
/* Setup the linkage between OF nodes and PHBs */
|
|
pci_devs_phb_init();
|
|
|
|
/* Configure IOMMU DMA hooks */
|
|
ppc_md.pci_dma_dev_setup = pnv_pci_dma_dev_setup;
|
|
ppc_md.tce_build = pnv_tce_build;
|
|
ppc_md.tce_free = pnv_tce_free;
|
|
ppc_md.tce_get = pnv_tce_get;
|
|
ppc_md.pci_probe_mode = pnv_pci_probe_mode;
|
|
set_pci_dma_ops(&dma_iommu_ops);
|
|
|
|
/* Configure MSIs */
|
|
#ifdef CONFIG_PCI_MSI
|
|
ppc_md.msi_check_device = pnv_msi_check_device;
|
|
ppc_md.setup_msi_irqs = pnv_setup_msi_irqs;
|
|
ppc_md.teardown_msi_irqs = pnv_teardown_msi_irqs;
|
|
#endif
|
|
}
|