254 строки
6.0 KiB
C
254 строки
6.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* MStar timer driver
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*
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* Copyright (C) 2021 Daniel Palmer
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* Copyright (C) 2021 Romain Perier
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*
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*/
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqreturn.h>
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#include <linux/sched_clock.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#ifdef CONFIG_ARM
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#include <linux/delay.h>
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#endif
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#include "timer-of.h"
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#define TIMER_NAME "msc313e_timer"
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#define MSC313E_REG_CTRL 0x00
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#define MSC313E_REG_CTRL_TIMER_EN BIT(0)
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#define MSC313E_REG_CTRL_TIMER_TRIG BIT(1)
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#define MSC313E_REG_CTRL_TIMER_INT_EN BIT(8)
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#define MSC313E_REG_TIMER_MAX_LOW 0x08
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#define MSC313E_REG_TIMER_MAX_HIGH 0x0c
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#define MSC313E_REG_COUNTER_LOW 0x10
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#define MSC313E_REG_COUNTER_HIGH 0x14
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#define MSC313E_REG_TIMER_DIVIDE 0x18
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#define MSC313E_CLK_DIVIDER 9
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#define TIMER_SYNC_TICKS 3
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#ifdef CONFIG_ARM
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struct msc313e_delay {
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void __iomem *base;
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struct delay_timer delay;
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};
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static struct msc313e_delay msc313e_delay;
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#endif
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static void __iomem *msc313e_clksrc;
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static void msc313e_timer_stop(void __iomem *base)
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{
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writew(0, base + MSC313E_REG_CTRL);
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}
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static void msc313e_timer_start(void __iomem *base, bool periodic)
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{
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u16 reg;
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reg = readw(base + MSC313E_REG_CTRL);
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if (periodic)
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reg |= MSC313E_REG_CTRL_TIMER_EN;
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else
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reg |= MSC313E_REG_CTRL_TIMER_TRIG;
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writew(reg | MSC313E_REG_CTRL_TIMER_INT_EN, base + MSC313E_REG_CTRL);
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}
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static void msc313e_timer_setup(void __iomem *base, unsigned long delay)
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{
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unsigned long flags;
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local_irq_save(flags);
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writew(delay >> 16, base + MSC313E_REG_TIMER_MAX_HIGH);
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writew(delay & 0xffff, base + MSC313E_REG_TIMER_MAX_LOW);
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local_irq_restore(flags);
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}
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static unsigned long msc313e_timer_current_value(void __iomem *base)
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{
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unsigned long flags;
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u16 l, h;
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local_irq_save(flags);
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l = readw(base + MSC313E_REG_COUNTER_LOW);
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h = readw(base + MSC313E_REG_COUNTER_HIGH);
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local_irq_restore(flags);
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return (((u32)h) << 16 | l);
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}
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static int msc313e_timer_clkevt_shutdown(struct clock_event_device *evt)
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{
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struct timer_of *timer = to_timer_of(evt);
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msc313e_timer_stop(timer_of_base(timer));
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return 0;
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}
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static int msc313e_timer_clkevt_set_oneshot(struct clock_event_device *evt)
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{
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struct timer_of *timer = to_timer_of(evt);
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msc313e_timer_stop(timer_of_base(timer));
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msc313e_timer_start(timer_of_base(timer), false);
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return 0;
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}
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static int msc313e_timer_clkevt_set_periodic(struct clock_event_device *evt)
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{
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struct timer_of *timer = to_timer_of(evt);
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msc313e_timer_stop(timer_of_base(timer));
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msc313e_timer_setup(timer_of_base(timer), timer_of_period(timer));
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msc313e_timer_start(timer_of_base(timer), true);
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return 0;
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}
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static int msc313e_timer_clkevt_next_event(unsigned long evt, struct clock_event_device *clkevt)
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{
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struct timer_of *timer = to_timer_of(clkevt);
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msc313e_timer_stop(timer_of_base(timer));
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msc313e_timer_setup(timer_of_base(timer), evt);
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msc313e_timer_start(timer_of_base(timer), false);
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return 0;
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}
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static irqreturn_t msc313e_timer_clkevt_irq(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static u64 msc313e_timer_clksrc_read(struct clocksource *cs)
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{
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return msc313e_timer_current_value(msc313e_clksrc) & cs->mask;
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}
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#ifdef CONFIG_ARM
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static unsigned long msc313e_read_delay_timer_read(void)
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{
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return msc313e_timer_current_value(msc313e_delay.base);
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}
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#endif
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static u64 msc313e_timer_sched_clock_read(void)
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{
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return msc313e_timer_current_value(msc313e_clksrc);
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}
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static struct clock_event_device msc313e_clkevt = {
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.name = TIMER_NAME,
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.rating = 300,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_state_shutdown = msc313e_timer_clkevt_shutdown,
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.set_state_periodic = msc313e_timer_clkevt_set_periodic,
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.set_state_oneshot = msc313e_timer_clkevt_set_oneshot,
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.tick_resume = msc313e_timer_clkevt_shutdown,
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.set_next_event = msc313e_timer_clkevt_next_event,
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};
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static int __init msc313e_clkevt_init(struct device_node *np)
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{
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int ret;
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struct timer_of *to;
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to = kzalloc(sizeof(*to), GFP_KERNEL);
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if (!to)
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return -ENOMEM;
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to->flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE;
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to->of_irq.handler = msc313e_timer_clkevt_irq;
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ret = timer_of_init(np, to);
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if (ret)
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return ret;
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if (of_device_is_compatible(np, "sstar,ssd20xd-timer")) {
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to->of_clk.rate = clk_get_rate(to->of_clk.clk) / MSC313E_CLK_DIVIDER;
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to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ);
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writew(MSC313E_CLK_DIVIDER - 1, timer_of_base(to) + MSC313E_REG_TIMER_DIVIDE);
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}
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msc313e_clkevt.cpumask = cpu_possible_mask;
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msc313e_clkevt.irq = to->of_irq.irq;
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to->clkevt = msc313e_clkevt;
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clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
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TIMER_SYNC_TICKS, 0xffffffff);
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return 0;
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}
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static int __init msc313e_clksrc_init(struct device_node *np)
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{
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struct timer_of to = { 0 };
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int ret;
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u16 reg;
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to.flags = TIMER_OF_BASE | TIMER_OF_CLOCK;
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ret = timer_of_init(np, &to);
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if (ret)
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return ret;
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msc313e_clksrc = timer_of_base(&to);
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reg = readw(msc313e_clksrc + MSC313E_REG_CTRL);
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reg |= MSC313E_REG_CTRL_TIMER_EN;
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writew(reg, msc313e_clksrc + MSC313E_REG_CTRL);
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#ifdef CONFIG_ARM
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msc313e_delay.base = timer_of_base(&to);
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msc313e_delay.delay.read_current_timer = msc313e_read_delay_timer_read;
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msc313e_delay.delay.freq = timer_of_rate(&to);
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register_current_timer_delay(&msc313e_delay.delay);
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#endif
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sched_clock_register(msc313e_timer_sched_clock_read, 32, timer_of_rate(&to));
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return clocksource_mmio_init(timer_of_base(&to), TIMER_NAME, timer_of_rate(&to), 300, 32,
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msc313e_timer_clksrc_read);
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}
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static int __init msc313e_timer_init(struct device_node *np)
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{
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int ret = 0;
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static int num_called;
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switch (num_called) {
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case 0:
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ret = msc313e_clksrc_init(np);
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if (ret)
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return ret;
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break;
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default:
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ret = msc313e_clkevt_init(np);
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if (ret)
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return ret;
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break;
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}
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num_called++;
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return 0;
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}
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TIMER_OF_DECLARE(msc313, "mstar,msc313e-timer", msc313e_timer_init);
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TIMER_OF_DECLARE(ssd20xd, "sstar,ssd20xd-timer", msc313e_timer_init);
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