700 строки
18 KiB
C
700 строки
18 KiB
C
/***********************license start************************************
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* Copyright (c) 2003-2017 Cavium, Inc.
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* All rights reserved.
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*
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* License: one of 'Cavium License' or 'GNU General Public License Version 2'
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*
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* This file is provided under the terms of the Cavium License (see below)
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* or under the terms of GNU General Public License, Version 2, as
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* published by the Free Software Foundation. When using or redistributing
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* this file, you may do so under either license.
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*
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* Cavium License: Redistribution and use in source and binary forms, with
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* or without modification, are permitted provided that the following
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* conditions are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* * Neither the name of Cavium Inc. nor the names of its contributors may be
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* used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* This Software, including technical data, may be subject to U.S. export
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* control laws, including the U.S. Export Administration Act and its
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* associated regulations, and may be subject to export or import
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* regulations in other countries.
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*
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS
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* OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
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* RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
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* REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
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* DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY)
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* WARRANTIES OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A
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* PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET
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* ENJOYMENT, QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE
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* ENTIRE RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES
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* WITH YOU.
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***********************license end**************************************/
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#include "common.h"
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#include "zip_crypto.h"
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#define DRV_NAME "ThunderX-ZIP"
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static struct zip_device *zip_dev[MAX_ZIP_DEVICES];
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static const struct pci_device_id zip_id_table[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDERX_ZIP) },
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{ 0, }
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};
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void zip_reg_write(u64 val, u64 __iomem *addr)
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{
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writeq(val, addr);
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}
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u64 zip_reg_read(u64 __iomem *addr)
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{
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return readq(addr);
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}
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/*
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* Allocates new ZIP device structure
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* Returns zip_device pointer or NULL if cannot allocate memory for zip_device
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*/
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static struct zip_device *zip_alloc_device(struct pci_dev *pdev)
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{
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struct zip_device *zip = NULL;
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int idx;
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for (idx = 0; idx < MAX_ZIP_DEVICES; idx++) {
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if (!zip_dev[idx])
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break;
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}
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/* To ensure that the index is within the limit */
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if (idx < MAX_ZIP_DEVICES)
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zip = devm_kzalloc(&pdev->dev, sizeof(*zip), GFP_KERNEL);
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if (!zip)
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return NULL;
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zip_dev[idx] = zip;
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zip->index = idx;
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return zip;
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}
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/**
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* zip_get_device - Get ZIP device based on node id of cpu
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*
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* @node: Node id of the current cpu
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* Return: Pointer to Zip device structure
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*/
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struct zip_device *zip_get_device(int node)
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{
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if ((node < MAX_ZIP_DEVICES) && (node >= 0))
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return zip_dev[node];
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zip_err("ZIP device not found for node id %d\n", node);
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return NULL;
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}
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/**
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* zip_get_node_id - Get the node id of the current cpu
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*
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* Return: Node id of the current cpu
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*/
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int zip_get_node_id(void)
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{
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return cpu_to_node(raw_smp_processor_id());
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}
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/* Initializes the ZIP h/w sub-system */
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static int zip_init_hw(struct zip_device *zip)
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{
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union zip_cmd_ctl cmd_ctl;
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union zip_constants constants;
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union zip_que_ena que_ena;
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union zip_quex_map que_map;
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union zip_que_pri que_pri;
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union zip_quex_sbuf_addr que_sbuf_addr;
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union zip_quex_sbuf_ctl que_sbuf_ctl;
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int q = 0;
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/* Enable the ZIP Engine(Core) Clock */
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cmd_ctl.u_reg64 = zip_reg_read(zip->reg_base + ZIP_CMD_CTL);
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cmd_ctl.s.forceclk = 1;
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zip_reg_write(cmd_ctl.u_reg64 & 0xFF, (zip->reg_base + ZIP_CMD_CTL));
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zip_msg("ZIP_CMD_CTL : 0x%016llx",
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zip_reg_read(zip->reg_base + ZIP_CMD_CTL));
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constants.u_reg64 = zip_reg_read(zip->reg_base + ZIP_CONSTANTS);
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zip->depth = constants.s.depth;
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zip->onfsize = constants.s.onfsize;
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zip->ctxsize = constants.s.ctxsize;
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zip_msg("depth: 0x%016llx , onfsize : 0x%016llx , ctxsize : 0x%016llx",
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zip->depth, zip->onfsize, zip->ctxsize);
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/*
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* Program ZIP_QUE(0..7)_SBUF_ADDR and ZIP_QUE(0..7)_SBUF_CTL to
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* have the correct buffer pointer and size configured for each
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* instruction queue.
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*/
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for (q = 0; q < ZIP_NUM_QUEUES; q++) {
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que_sbuf_ctl.u_reg64 = 0ull;
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que_sbuf_ctl.s.size = (ZIP_CMD_QBUF_SIZE / sizeof(u64));
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que_sbuf_ctl.s.inst_be = 0;
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que_sbuf_ctl.s.stream_id = 0;
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zip_reg_write(que_sbuf_ctl.u_reg64,
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(zip->reg_base + ZIP_QUEX_SBUF_CTL(q)));
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zip_msg("QUEX_SBUF_CTL[%d]: 0x%016llx", q,
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zip_reg_read(zip->reg_base + ZIP_QUEX_SBUF_CTL(q)));
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}
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for (q = 0; q < ZIP_NUM_QUEUES; q++) {
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memset(&zip->iq[q], 0x0, sizeof(struct zip_iq));
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spin_lock_init(&zip->iq[q].lock);
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if (zip_cmd_qbuf_alloc(zip, q)) {
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while (q != 0) {
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q--;
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zip_cmd_qbuf_free(zip, q);
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}
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return -ENOMEM;
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}
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/* Initialize tail ptr to head */
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zip->iq[q].sw_tail = zip->iq[q].sw_head;
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zip->iq[q].hw_tail = zip->iq[q].sw_head;
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/* Write the physical addr to register */
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que_sbuf_addr.u_reg64 = 0ull;
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que_sbuf_addr.s.ptr = (__pa(zip->iq[q].sw_head) >>
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ZIP_128B_ALIGN);
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zip_msg("QUE[%d]_PTR(PHYS): 0x%016llx", q,
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(u64)que_sbuf_addr.s.ptr);
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zip_reg_write(que_sbuf_addr.u_reg64,
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(zip->reg_base + ZIP_QUEX_SBUF_ADDR(q)));
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zip_msg("QUEX_SBUF_ADDR[%d]: 0x%016llx", q,
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zip_reg_read(zip->reg_base + ZIP_QUEX_SBUF_ADDR(q)));
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zip_dbg("sw_head :0x%lx sw_tail :0x%lx hw_tail :0x%lx",
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zip->iq[q].sw_head, zip->iq[q].sw_tail,
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zip->iq[q].hw_tail);
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zip_dbg("sw_head phy addr : 0x%lx", que_sbuf_addr.s.ptr);
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}
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/*
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* Queue-to-ZIP core mapping
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* If a queue is not mapped to a particular core, it is equivalent to
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* the ZIP core being disabled.
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*/
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que_ena.u_reg64 = 0x0ull;
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/* Enabling queues based on ZIP_NUM_QUEUES */
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for (q = 0; q < ZIP_NUM_QUEUES; q++)
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que_ena.s.ena |= (0x1 << q);
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zip_reg_write(que_ena.u_reg64, (zip->reg_base + ZIP_QUE_ENA));
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zip_msg("QUE_ENA : 0x%016llx",
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zip_reg_read(zip->reg_base + ZIP_QUE_ENA));
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for (q = 0; q < ZIP_NUM_QUEUES; q++) {
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que_map.u_reg64 = 0ull;
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/* Mapping each queue to two ZIP cores */
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que_map.s.zce = 0x3;
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zip_reg_write(que_map.u_reg64,
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(zip->reg_base + ZIP_QUEX_MAP(q)));
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zip_msg("QUE_MAP(%d) : 0x%016llx", q,
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zip_reg_read(zip->reg_base + ZIP_QUEX_MAP(q)));
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}
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que_pri.u_reg64 = 0ull;
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for (q = 0; q < ZIP_NUM_QUEUES; q++)
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que_pri.s.pri |= (0x1 << q); /* Higher Priority RR */
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zip_reg_write(que_pri.u_reg64, (zip->reg_base + ZIP_QUE_PRI));
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zip_msg("QUE_PRI %016llx", zip_reg_read(zip->reg_base + ZIP_QUE_PRI));
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return 0;
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}
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static int zip_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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struct device *dev = &pdev->dev;
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struct zip_device *zip = NULL;
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int err;
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zip = zip_alloc_device(pdev);
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if (!zip)
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return -ENOMEM;
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dev_info(dev, "Found ZIP device %d %x:%x on Node %d\n", zip->index,
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pdev->vendor, pdev->device, dev_to_node(dev));
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pci_set_drvdata(pdev, zip);
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zip->pdev = pdev;
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err = pci_enable_device(pdev);
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if (err) {
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dev_err(dev, "Failed to enable PCI device");
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goto err_free_device;
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}
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err = pci_request_regions(pdev, DRV_NAME);
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if (err) {
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dev_err(dev, "PCI request regions failed 0x%x", err);
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goto err_disable_device;
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}
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err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48));
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if (err) {
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dev_err(dev, "Unable to get usable DMA configuration\n");
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goto err_release_regions;
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}
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err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48));
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if (err) {
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dev_err(dev, "Unable to get 48-bit DMA for allocations\n");
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goto err_release_regions;
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}
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/* MAP configuration registers */
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zip->reg_base = pci_ioremap_bar(pdev, PCI_CFG_ZIP_PF_BAR0);
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if (!zip->reg_base) {
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dev_err(dev, "ZIP: Cannot map BAR0 CSR memory space, aborting");
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err = -ENOMEM;
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goto err_release_regions;
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}
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/* Initialize ZIP Hardware */
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err = zip_init_hw(zip);
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if (err)
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goto err_release_regions;
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return 0;
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err_release_regions:
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if (zip->reg_base)
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iounmap(zip->reg_base);
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pci_release_regions(pdev);
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err_disable_device:
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pci_disable_device(pdev);
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err_free_device:
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pci_set_drvdata(pdev, NULL);
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/* Remove zip_dev from zip_device list, free the zip_device memory */
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zip_dev[zip->index] = NULL;
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devm_kfree(dev, zip);
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return err;
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}
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static void zip_remove(struct pci_dev *pdev)
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{
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struct zip_device *zip = pci_get_drvdata(pdev);
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union zip_cmd_ctl cmd_ctl;
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int q = 0;
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if (!zip)
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return;
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if (zip->reg_base) {
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cmd_ctl.u_reg64 = 0x0ull;
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cmd_ctl.s.reset = 1; /* Forces ZIP cores to do reset */
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zip_reg_write(cmd_ctl.u_reg64, (zip->reg_base + ZIP_CMD_CTL));
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iounmap(zip->reg_base);
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}
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pci_release_regions(pdev);
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pci_disable_device(pdev);
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/*
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* Free Command Queue buffers. This free should be called for all
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* the enabled Queues.
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*/
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for (q = 0; q < ZIP_NUM_QUEUES; q++)
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zip_cmd_qbuf_free(zip, q);
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pci_set_drvdata(pdev, NULL);
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/* remove zip device from zip device list */
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zip_dev[zip->index] = NULL;
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}
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/* PCI Sub-System Interface */
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static struct pci_driver zip_driver = {
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.name = DRV_NAME,
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.id_table = zip_id_table,
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.probe = zip_probe,
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.remove = zip_remove,
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};
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/* Kernel Crypto Subsystem Interface */
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static struct crypto_alg zip_comp_deflate = {
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.cra_name = "deflate",
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.cra_driver_name = "deflate-cavium",
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.cra_flags = CRYPTO_ALG_TYPE_COMPRESS,
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.cra_ctxsize = sizeof(struct zip_kernel_ctx),
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.cra_priority = 300,
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.cra_module = THIS_MODULE,
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.cra_init = zip_alloc_comp_ctx_deflate,
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.cra_exit = zip_free_comp_ctx,
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.cra_u = { .compress = {
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.coa_compress = zip_comp_compress,
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.coa_decompress = zip_comp_decompress
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} }
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};
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static struct crypto_alg zip_comp_lzs = {
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.cra_name = "lzs",
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.cra_driver_name = "lzs-cavium",
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.cra_flags = CRYPTO_ALG_TYPE_COMPRESS,
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.cra_ctxsize = sizeof(struct zip_kernel_ctx),
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.cra_priority = 300,
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.cra_module = THIS_MODULE,
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.cra_init = zip_alloc_comp_ctx_lzs,
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.cra_exit = zip_free_comp_ctx,
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.cra_u = { .compress = {
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.coa_compress = zip_comp_compress,
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.coa_decompress = zip_comp_decompress
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} }
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};
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static struct scomp_alg zip_scomp_deflate = {
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.alloc_ctx = zip_alloc_scomp_ctx_deflate,
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.free_ctx = zip_free_scomp_ctx,
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.compress = zip_scomp_compress,
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.decompress = zip_scomp_decompress,
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.base = {
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.cra_name = "deflate",
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.cra_driver_name = "deflate-scomp-cavium",
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.cra_module = THIS_MODULE,
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.cra_priority = 300,
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}
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};
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static struct scomp_alg zip_scomp_lzs = {
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.alloc_ctx = zip_alloc_scomp_ctx_lzs,
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.free_ctx = zip_free_scomp_ctx,
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.compress = zip_scomp_compress,
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.decompress = zip_scomp_decompress,
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.base = {
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.cra_name = "lzs",
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.cra_driver_name = "lzs-scomp-cavium",
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.cra_module = THIS_MODULE,
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.cra_priority = 300,
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}
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};
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static int zip_register_compression_device(void)
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{
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int ret;
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ret = crypto_register_alg(&zip_comp_deflate);
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if (ret < 0) {
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zip_err("Deflate algorithm registration failed\n");
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return ret;
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}
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ret = crypto_register_alg(&zip_comp_lzs);
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if (ret < 0) {
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zip_err("LZS algorithm registration failed\n");
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goto err_unregister_alg_deflate;
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}
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ret = crypto_register_scomp(&zip_scomp_deflate);
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if (ret < 0) {
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zip_err("Deflate scomp algorithm registration failed\n");
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goto err_unregister_alg_lzs;
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}
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ret = crypto_register_scomp(&zip_scomp_lzs);
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if (ret < 0) {
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zip_err("LZS scomp algorithm registration failed\n");
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goto err_unregister_scomp_deflate;
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}
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return ret;
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err_unregister_scomp_deflate:
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crypto_unregister_scomp(&zip_scomp_deflate);
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err_unregister_alg_lzs:
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crypto_unregister_alg(&zip_comp_lzs);
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err_unregister_alg_deflate:
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crypto_unregister_alg(&zip_comp_deflate);
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return ret;
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}
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static void zip_unregister_compression_device(void)
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{
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crypto_unregister_alg(&zip_comp_deflate);
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crypto_unregister_alg(&zip_comp_lzs);
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crypto_unregister_scomp(&zip_scomp_deflate);
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crypto_unregister_scomp(&zip_scomp_lzs);
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}
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/*
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* debugfs functions
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*/
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#ifdef CONFIG_DEBUG_FS
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#include <linux/debugfs.h>
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/* Displays ZIP device statistics */
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static int zip_show_stats(struct seq_file *s, void *unused)
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{
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u64 val = 0ull;
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u64 avg_chunk = 0ull, avg_cr = 0ull;
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u32 q = 0;
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int index = 0;
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struct zip_device *zip;
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struct zip_stats *st;
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for (index = 0; index < MAX_ZIP_DEVICES; index++) {
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u64 pending = 0;
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if (zip_dev[index]) {
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zip = zip_dev[index];
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st = &zip->stats;
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/* Get all the pending requests */
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for (q = 0; q < ZIP_NUM_QUEUES; q++) {
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val = zip_reg_read((zip->reg_base +
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ZIP_DBG_QUEX_STA(q)));
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pending += val >> 32 & 0xffffff;
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}
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val = atomic64_read(&st->comp_req_complete);
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avg_chunk = (val) ? atomic64_read(&st->comp_in_bytes) / val : 0;
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|
|
val = atomic64_read(&st->comp_out_bytes);
|
|
avg_cr = (val) ? atomic64_read(&st->comp_in_bytes) / val : 0;
|
|
seq_printf(s, " ZIP Device %d Stats\n"
|
|
"-----------------------------------\n"
|
|
"Comp Req Submitted : \t%lld\n"
|
|
"Comp Req Completed : \t%lld\n"
|
|
"Compress In Bytes : \t%lld\n"
|
|
"Compressed Out Bytes : \t%lld\n"
|
|
"Average Chunk size : \t%llu\n"
|
|
"Average Compression ratio : \t%llu\n"
|
|
"Decomp Req Submitted : \t%lld\n"
|
|
"Decomp Req Completed : \t%lld\n"
|
|
"Decompress In Bytes : \t%lld\n"
|
|
"Decompressed Out Bytes : \t%lld\n"
|
|
"Decompress Bad requests : \t%lld\n"
|
|
"Pending Req : \t%lld\n"
|
|
"---------------------------------\n",
|
|
index,
|
|
(u64)atomic64_read(&st->comp_req_submit),
|
|
(u64)atomic64_read(&st->comp_req_complete),
|
|
(u64)atomic64_read(&st->comp_in_bytes),
|
|
(u64)atomic64_read(&st->comp_out_bytes),
|
|
avg_chunk,
|
|
avg_cr,
|
|
(u64)atomic64_read(&st->decomp_req_submit),
|
|
(u64)atomic64_read(&st->decomp_req_complete),
|
|
(u64)atomic64_read(&st->decomp_in_bytes),
|
|
(u64)atomic64_read(&st->decomp_out_bytes),
|
|
(u64)atomic64_read(&st->decomp_bad_reqs),
|
|
pending);
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* Clears stats data */
|
|
static int zip_clear_stats(struct seq_file *s, void *unused)
|
|
{
|
|
int index = 0;
|
|
|
|
for (index = 0; index < MAX_ZIP_DEVICES; index++) {
|
|
if (zip_dev[index]) {
|
|
memset(&zip_dev[index]->stats, 0,
|
|
sizeof(struct zip_stats));
|
|
seq_printf(s, "Cleared stats for zip %d\n", index);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct zip_registers zipregs[64] = {
|
|
{"ZIP_CMD_CTL ", 0x0000ull},
|
|
{"ZIP_THROTTLE ", 0x0010ull},
|
|
{"ZIP_CONSTANTS ", 0x00A0ull},
|
|
{"ZIP_QUE0_MAP ", 0x1400ull},
|
|
{"ZIP_QUE1_MAP ", 0x1408ull},
|
|
{"ZIP_QUE_ENA ", 0x0500ull},
|
|
{"ZIP_QUE_PRI ", 0x0508ull},
|
|
{"ZIP_QUE0_DONE ", 0x2000ull},
|
|
{"ZIP_QUE1_DONE ", 0x2008ull},
|
|
{"ZIP_QUE0_DOORBELL ", 0x4000ull},
|
|
{"ZIP_QUE1_DOORBELL ", 0x4008ull},
|
|
{"ZIP_QUE0_SBUF_ADDR ", 0x1000ull},
|
|
{"ZIP_QUE1_SBUF_ADDR ", 0x1008ull},
|
|
{"ZIP_QUE0_SBUF_CTL ", 0x1200ull},
|
|
{"ZIP_QUE1_SBUF_CTL ", 0x1208ull},
|
|
{ NULL, 0}
|
|
};
|
|
|
|
/* Prints registers' contents */
|
|
static int zip_print_regs(struct seq_file *s, void *unused)
|
|
{
|
|
u64 val = 0;
|
|
int i = 0, index = 0;
|
|
|
|
for (index = 0; index < MAX_ZIP_DEVICES; index++) {
|
|
if (zip_dev[index]) {
|
|
seq_printf(s, "--------------------------------\n"
|
|
" ZIP Device %d Registers\n"
|
|
"--------------------------------\n",
|
|
index);
|
|
|
|
i = 0;
|
|
|
|
while (zipregs[i].reg_name) {
|
|
val = zip_reg_read((zip_dev[index]->reg_base +
|
|
zipregs[i].reg_offset));
|
|
seq_printf(s, "%s: 0x%016llx\n",
|
|
zipregs[i].reg_name, val);
|
|
i++;
|
|
}
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int zip_stats_open(struct inode *inode, struct file *file)
|
|
{
|
|
return single_open(file, zip_show_stats, NULL);
|
|
}
|
|
|
|
static const struct file_operations zip_stats_fops = {
|
|
.owner = THIS_MODULE,
|
|
.open = zip_stats_open,
|
|
.read = seq_read,
|
|
};
|
|
|
|
static int zip_clear_open(struct inode *inode, struct file *file)
|
|
{
|
|
return single_open(file, zip_clear_stats, NULL);
|
|
}
|
|
|
|
static const struct file_operations zip_clear_fops = {
|
|
.owner = THIS_MODULE,
|
|
.open = zip_clear_open,
|
|
.read = seq_read,
|
|
};
|
|
|
|
static int zip_regs_open(struct inode *inode, struct file *file)
|
|
{
|
|
return single_open(file, zip_print_regs, NULL);
|
|
}
|
|
|
|
static const struct file_operations zip_regs_fops = {
|
|
.owner = THIS_MODULE,
|
|
.open = zip_regs_open,
|
|
.read = seq_read,
|
|
};
|
|
|
|
/* Root directory for thunderx_zip debugfs entry */
|
|
static struct dentry *zip_debugfs_root;
|
|
|
|
static void __init zip_debugfs_init(void)
|
|
{
|
|
if (!debugfs_initialized())
|
|
return;
|
|
|
|
zip_debugfs_root = debugfs_create_dir("thunderx_zip", NULL);
|
|
|
|
/* Creating files for entries inside thunderx_zip directory */
|
|
debugfs_create_file("zip_stats", 0444, zip_debugfs_root, NULL,
|
|
&zip_stats_fops);
|
|
|
|
debugfs_create_file("zip_clear", 0444, zip_debugfs_root, NULL,
|
|
&zip_clear_fops);
|
|
|
|
debugfs_create_file("zip_regs", 0444, zip_debugfs_root, NULL,
|
|
&zip_regs_fops);
|
|
|
|
}
|
|
|
|
static void __exit zip_debugfs_exit(void)
|
|
{
|
|
debugfs_remove_recursive(zip_debugfs_root);
|
|
}
|
|
|
|
#else
|
|
static void __init zip_debugfs_init(void) { }
|
|
static void __exit zip_debugfs_exit(void) { }
|
|
#endif
|
|
/* debugfs - end */
|
|
|
|
static int __init zip_init_module(void)
|
|
{
|
|
int ret;
|
|
|
|
zip_msg("%s\n", DRV_NAME);
|
|
|
|
ret = pci_register_driver(&zip_driver);
|
|
if (ret < 0) {
|
|
zip_err("ZIP: pci_register_driver() failed\n");
|
|
return ret;
|
|
}
|
|
|
|
/* Register with the Kernel Crypto Interface */
|
|
ret = zip_register_compression_device();
|
|
if (ret < 0) {
|
|
zip_err("ZIP: Kernel Crypto Registration failed\n");
|
|
goto err_pci_unregister;
|
|
}
|
|
|
|
/* comp-decomp statistics are handled with debugfs interface */
|
|
zip_debugfs_init();
|
|
|
|
return ret;
|
|
|
|
err_pci_unregister:
|
|
pci_unregister_driver(&zip_driver);
|
|
return ret;
|
|
}
|
|
|
|
static void __exit zip_cleanup_module(void)
|
|
{
|
|
zip_debugfs_exit();
|
|
|
|
/* Unregister from the kernel crypto interface */
|
|
zip_unregister_compression_device();
|
|
|
|
/* Unregister this driver for pci zip devices */
|
|
pci_unregister_driver(&zip_driver);
|
|
}
|
|
|
|
module_init(zip_init_module);
|
|
module_exit(zip_cleanup_module);
|
|
|
|
MODULE_AUTHOR("Cavium Inc");
|
|
MODULE_DESCRIPTION("Cavium Inc ThunderX ZIP Driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DEVICE_TABLE(pci, zip_id_table);
|