371 строка
7.6 KiB
C
371 строка
7.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/of_device.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <dt-bindings/memory/tegra20-mc.h>
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#include "mc.h"
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static const struct tegra_mc_client tegra20_mc_clients[] = {
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{
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.id = 0x00,
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.name = "display0a",
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}, {
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.id = 0x01,
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.name = "display0ab",
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}, {
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.id = 0x02,
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.name = "display0b",
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}, {
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.id = 0x03,
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.name = "display0bb",
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}, {
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.id = 0x04,
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.name = "display0c",
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}, {
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.id = 0x05,
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.name = "display0cb",
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}, {
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.id = 0x06,
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.name = "display1b",
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}, {
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.id = 0x07,
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.name = "display1bb",
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}, {
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.id = 0x08,
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.name = "eppup",
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}, {
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.id = 0x09,
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.name = "g2pr",
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}, {
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.id = 0x0a,
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.name = "g2sr",
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}, {
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.id = 0x0b,
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.name = "mpeunifbr",
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}, {
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.id = 0x0c,
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.name = "viruv",
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}, {
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.id = 0x0d,
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.name = "avpcarm7r",
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}, {
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.id = 0x0e,
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.name = "displayhc",
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}, {
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.id = 0x0f,
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.name = "displayhcb",
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}, {
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.id = 0x10,
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.name = "fdcdrd",
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}, {
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.id = 0x11,
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.name = "g2dr",
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}, {
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.id = 0x12,
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.name = "host1xdmar",
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}, {
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.id = 0x13,
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.name = "host1xr",
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}, {
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.id = 0x14,
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.name = "idxsrd",
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}, {
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.id = 0x15,
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.name = "mpcorer",
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}, {
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.id = 0x16,
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.name = "mpe_ipred",
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}, {
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.id = 0x17,
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.name = "mpeamemrd",
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}, {
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.id = 0x18,
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.name = "mpecsrd",
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}, {
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.id = 0x19,
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.name = "ppcsahbdmar",
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}, {
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.id = 0x1a,
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.name = "ppcsahbslvr",
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}, {
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.id = 0x1b,
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.name = "texsrd",
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}, {
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.id = 0x1c,
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.name = "vdebsevr",
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}, {
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.id = 0x1d,
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.name = "vdember",
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}, {
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.id = 0x1e,
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.name = "vdemcer",
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}, {
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.id = 0x1f,
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.name = "vdetper",
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}, {
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.id = 0x20,
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.name = "eppu",
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}, {
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.id = 0x21,
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.name = "eppv",
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}, {
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.id = 0x22,
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.name = "eppy",
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}, {
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.id = 0x23,
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.name = "mpeunifbw",
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}, {
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.id = 0x24,
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.name = "viwsb",
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}, {
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.id = 0x25,
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.name = "viwu",
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}, {
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.id = 0x26,
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.name = "viwv",
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}, {
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.id = 0x27,
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.name = "viwy",
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}, {
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.id = 0x28,
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.name = "g2dw",
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}, {
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.id = 0x29,
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.name = "avpcarm7w",
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}, {
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.id = 0x2a,
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.name = "fdcdwr",
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}, {
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.id = 0x2b,
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.name = "host1xw",
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}, {
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.id = 0x2c,
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.name = "ispw",
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}, {
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.id = 0x2d,
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.name = "mpcorew",
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}, {
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.id = 0x2e,
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.name = "mpecswr",
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}, {
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.id = 0x2f,
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.name = "ppcsahbdmaw",
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}, {
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.id = 0x30,
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.name = "ppcsahbslvw",
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}, {
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.id = 0x31,
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.name = "vdebsevw",
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}, {
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.id = 0x32,
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.name = "vdembew",
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}, {
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.id = 0x33,
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.name = "vdetpmw",
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},
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};
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#define TEGRA20_MC_RESET(_name, _control, _status, _reset, _bit) \
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{ \
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.name = #_name, \
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.id = TEGRA20_MC_RESET_##_name, \
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.control = _control, \
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.status = _status, \
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.reset = _reset, \
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.bit = _bit, \
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}
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static const struct tegra_mc_reset tegra20_mc_resets[] = {
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TEGRA20_MC_RESET(AVPC, 0x100, 0x140, 0x104, 0),
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TEGRA20_MC_RESET(DC, 0x100, 0x144, 0x104, 1),
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TEGRA20_MC_RESET(DCB, 0x100, 0x148, 0x104, 2),
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TEGRA20_MC_RESET(EPP, 0x100, 0x14c, 0x104, 3),
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TEGRA20_MC_RESET(2D, 0x100, 0x150, 0x104, 4),
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TEGRA20_MC_RESET(HC, 0x100, 0x154, 0x104, 5),
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TEGRA20_MC_RESET(ISP, 0x100, 0x158, 0x104, 6),
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TEGRA20_MC_RESET(MPCORE, 0x100, 0x15c, 0x104, 7),
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TEGRA20_MC_RESET(MPEA, 0x100, 0x160, 0x104, 8),
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TEGRA20_MC_RESET(MPEB, 0x100, 0x164, 0x104, 9),
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TEGRA20_MC_RESET(MPEC, 0x100, 0x168, 0x104, 10),
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TEGRA20_MC_RESET(3D, 0x100, 0x16c, 0x104, 11),
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TEGRA20_MC_RESET(PPCS, 0x100, 0x170, 0x104, 12),
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TEGRA20_MC_RESET(VDE, 0x100, 0x174, 0x104, 13),
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TEGRA20_MC_RESET(VI, 0x100, 0x178, 0x104, 14),
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};
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static int tegra20_mc_hotreset_assert(struct tegra_mc *mc,
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const struct tegra_mc_reset *rst)
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{
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unsigned long flags;
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u32 value;
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spin_lock_irqsave(&mc->lock, flags);
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value = mc_readl(mc, rst->reset);
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mc_writel(mc, value & ~BIT(rst->bit), rst->reset);
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spin_unlock_irqrestore(&mc->lock, flags);
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return 0;
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}
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static int tegra20_mc_hotreset_deassert(struct tegra_mc *mc,
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const struct tegra_mc_reset *rst)
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{
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unsigned long flags;
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u32 value;
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spin_lock_irqsave(&mc->lock, flags);
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value = mc_readl(mc, rst->reset);
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mc_writel(mc, value | BIT(rst->bit), rst->reset);
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spin_unlock_irqrestore(&mc->lock, flags);
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return 0;
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}
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static int tegra20_mc_block_dma(struct tegra_mc *mc,
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const struct tegra_mc_reset *rst)
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{
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unsigned long flags;
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u32 value;
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spin_lock_irqsave(&mc->lock, flags);
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value = mc_readl(mc, rst->control) & ~BIT(rst->bit);
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mc_writel(mc, value, rst->control);
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spin_unlock_irqrestore(&mc->lock, flags);
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return 0;
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}
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static bool tegra20_mc_dma_idling(struct tegra_mc *mc,
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const struct tegra_mc_reset *rst)
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{
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return mc_readl(mc, rst->status) == 0;
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}
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static int tegra20_mc_reset_status(struct tegra_mc *mc,
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const struct tegra_mc_reset *rst)
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{
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return (mc_readl(mc, rst->reset) & BIT(rst->bit)) == 0;
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}
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static int tegra20_mc_unblock_dma(struct tegra_mc *mc,
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const struct tegra_mc_reset *rst)
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{
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unsigned long flags;
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u32 value;
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spin_lock_irqsave(&mc->lock, flags);
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value = mc_readl(mc, rst->control) | BIT(rst->bit);
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mc_writel(mc, value, rst->control);
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spin_unlock_irqrestore(&mc->lock, flags);
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return 0;
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}
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static const struct tegra_mc_reset_ops tegra20_mc_reset_ops = {
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.hotreset_assert = tegra20_mc_hotreset_assert,
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.hotreset_deassert = tegra20_mc_hotreset_deassert,
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.block_dma = tegra20_mc_block_dma,
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.dma_idling = tegra20_mc_dma_idling,
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.unblock_dma = tegra20_mc_unblock_dma,
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.reset_status = tegra20_mc_reset_status,
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};
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static int tegra20_mc_icc_set(struct icc_node *src, struct icc_node *dst)
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{
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/*
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* It should be possible to tune arbitration knobs here, but the
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* default values are known to work well on all devices. Hence
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* nothing to do here so far.
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*/
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return 0;
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}
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static int tegra20_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw,
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u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
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{
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/*
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* ISO clients need to reserve extra bandwidth up-front because
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* there could be high bandwidth pressure during initial filling
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* of the client's FIFO buffers. Secondly, we need to take into
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* account impurities of the memory subsystem.
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*/
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if (tag & TEGRA_MC_ICC_TAG_ISO)
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peak_bw = tegra_mc_scale_percents(peak_bw, 300);
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*agg_avg += avg_bw;
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*agg_peak = max(*agg_peak, peak_bw);
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return 0;
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}
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static struct icc_node_data *
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tegra20_mc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
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{
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struct tegra_mc *mc = icc_provider_to_tegra_mc(data);
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unsigned int i, idx = spec->args[0];
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struct icc_node_data *ndata;
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struct icc_node *node;
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list_for_each_entry(node, &mc->provider.nodes, node_list) {
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if (node->id != idx)
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continue;
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ndata = kzalloc(sizeof(*ndata), GFP_KERNEL);
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if (!ndata)
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return ERR_PTR(-ENOMEM);
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ndata->node = node;
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/* these clients are isochronous by default */
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if (strstarts(node->name, "display") ||
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strstarts(node->name, "vi"))
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ndata->tag = TEGRA_MC_ICC_TAG_ISO;
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else
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ndata->tag = TEGRA_MC_ICC_TAG_DEFAULT;
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return ndata;
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}
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for (i = 0; i < mc->soc->num_clients; i++) {
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if (mc->soc->clients[i].id == idx)
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return ERR_PTR(-EPROBE_DEFER);
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}
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dev_err(mc->dev, "invalid ICC client ID %u\n", idx);
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return ERR_PTR(-EINVAL);
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}
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static const struct tegra_mc_icc_ops tegra20_mc_icc_ops = {
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.xlate_extended = tegra20_mc_of_icc_xlate_extended,
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.aggregate = tegra20_mc_icc_aggreate,
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.set = tegra20_mc_icc_set,
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};
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const struct tegra_mc_soc tegra20_mc_soc = {
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.clients = tegra20_mc_clients,
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.num_clients = ARRAY_SIZE(tegra20_mc_clients),
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.num_address_bits = 32,
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.client_id_mask = 0x3f,
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.intmask = MC_INT_SECURITY_VIOLATION | MC_INT_INVALID_GART_PAGE |
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MC_INT_DECERR_EMEM,
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.reset_ops = &tegra20_mc_reset_ops,
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.resets = tegra20_mc_resets,
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.num_resets = ARRAY_SIZE(tegra20_mc_resets),
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.icc_ops = &tegra20_mc_icc_ops,
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};
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