Andrew Bresticker a47eb351d2 CLK: Pistachio: Register external clock gates ... Register the clock gates for the external audio and ethernet reference clocks provided by the top-level general control block. Signed-off-by: Damien Horsley <Damien.Horsley@imgtec.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Cc: James Hartley <james.hartley@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Patchwork: https://patchwork.linux-mips.org/patch/9321/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2015-03-31 11:59:31 +02:00
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Makefile	CLK: Pistachio: Register core clocks	2015-03-31 11:59:10 +02:00
clk-pistachio.c	CLK: Pistachio: Register external clock gates	2015-03-31 11:59:31 +02:00
clk-pll.c	CLK: Pistachio: Add PLL driver	2015-03-31 11:59:04 +02:00
clk.c	…
clk.h	CLK: Pistachio: Add PLL driver	2015-03-31 11:59:04 +02:00