164 строки
3.7 KiB
C
164 строки
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device access for Basin Cove PMIC
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*
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* Copyright (c) 2019, Intel Corporation.
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* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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*/
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#include <linux/acpi.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/intel_soc_pmic.h>
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#include <linux/mfd/intel_soc_pmic_mrfld.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <asm/intel_scu_ipc.h>
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/*
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* Level 2 IRQs
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*
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* Firmware on the systems with Basin Cove PMIC services Level 1 IRQs
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* without an assistance. Thus, each of the Level 1 IRQ is represented
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* as a separate RTE in IOAPIC.
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*/
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static struct resource irq_level2_resources[] = {
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DEFINE_RES_IRQ(0), /* power button */
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DEFINE_RES_IRQ(0), /* TMU */
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DEFINE_RES_IRQ(0), /* thermal */
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DEFINE_RES_IRQ(0), /* BCU */
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DEFINE_RES_IRQ(0), /* ADC */
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DEFINE_RES_IRQ(0), /* charger */
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DEFINE_RES_IRQ(0), /* GPIO */
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};
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static const struct mfd_cell bcove_dev[] = {
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{
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.name = "mrfld_bcove_pwrbtn",
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.num_resources = 1,
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.resources = &irq_level2_resources[0],
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}, {
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.name = "mrfld_bcove_tmu",
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.num_resources = 1,
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.resources = &irq_level2_resources[1],
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}, {
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.name = "mrfld_bcove_thermal",
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.num_resources = 1,
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.resources = &irq_level2_resources[2],
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}, {
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.name = "mrfld_bcove_bcu",
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.num_resources = 1,
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.resources = &irq_level2_resources[3],
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}, {
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.name = "mrfld_bcove_adc",
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.num_resources = 1,
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.resources = &irq_level2_resources[4],
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}, {
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.name = "mrfld_bcove_charger",
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.num_resources = 1,
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.resources = &irq_level2_resources[5],
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}, {
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.name = "mrfld_bcove_pwrsrc",
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.num_resources = 1,
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.resources = &irq_level2_resources[5],
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}, {
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.name = "mrfld_bcove_gpio",
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.num_resources = 1,
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.resources = &irq_level2_resources[6],
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},
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{ .name = "mrfld_bcove_region", },
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};
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static int bcove_ipc_byte_reg_read(void *context, unsigned int reg,
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unsigned int *val)
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{
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struct intel_soc_pmic *pmic = context;
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u8 ipc_out;
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int ret;
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ret = intel_scu_ipc_dev_ioread8(pmic->scu, reg, &ipc_out);
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if (ret)
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return ret;
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*val = ipc_out;
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return 0;
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}
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static int bcove_ipc_byte_reg_write(void *context, unsigned int reg,
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unsigned int val)
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{
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struct intel_soc_pmic *pmic = context;
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u8 ipc_in = val;
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int ret;
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ret = intel_scu_ipc_dev_iowrite8(pmic->scu, reg, ipc_in);
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if (ret)
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return ret;
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return 0;
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}
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static const struct regmap_config bcove_regmap_config = {
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.reg_bits = 16,
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.val_bits = 8,
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.max_register = 0xff,
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.reg_write = bcove_ipc_byte_reg_write,
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.reg_read = bcove_ipc_byte_reg_read,
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};
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static int bcove_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct intel_soc_pmic *pmic;
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unsigned int i;
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int ret;
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pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
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if (!pmic)
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return -ENOMEM;
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pmic->scu = devm_intel_scu_ipc_dev_get(dev);
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if (!pmic->scu)
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return -ENOMEM;
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platform_set_drvdata(pdev, pmic);
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pmic->dev = &pdev->dev;
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pmic->regmap = devm_regmap_init(dev, NULL, pmic, &bcove_regmap_config);
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if (IS_ERR(pmic->regmap))
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return PTR_ERR(pmic->regmap);
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for (i = 0; i < ARRAY_SIZE(irq_level2_resources); i++) {
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ret = platform_get_irq(pdev, i);
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if (ret < 0)
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return ret;
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irq_level2_resources[i].start = ret;
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irq_level2_resources[i].end = ret;
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}
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return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
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bcove_dev, ARRAY_SIZE(bcove_dev),
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NULL, 0, NULL);
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}
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static const struct acpi_device_id bcove_acpi_ids[] = {
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{ "INTC100E" },
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{}
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};
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MODULE_DEVICE_TABLE(acpi, bcove_acpi_ids);
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static struct platform_driver bcove_driver = {
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.driver = {
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.name = "intel_soc_pmic_mrfld",
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.acpi_match_table = bcove_acpi_ids,
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},
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.probe = bcove_probe,
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};
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module_platform_driver(bcove_driver);
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MODULE_DESCRIPTION("IPC driver for Intel SoC Basin Cove PMIC");
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MODULE_LICENSE("GPL v2");
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