460 строки
12 KiB
C
460 строки
12 KiB
C
/*
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* linux/arch/alpha/kernel/time.c
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*
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* Copyright (C) 1991, 1992, 1995, 1999, 2000 Linus Torvalds
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*
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* This file contains the clocksource time handling.
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* 1997-09-10 Updated NTP code according to technical memorandum Jan '96
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* "A Kernel Model for Precision Timekeeping" by Dave Mills
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* 1997-01-09 Adrian Sun
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* use interval timer if CONFIG_RTC=y
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* 1997-10-29 John Bowman (bowman@math.ualberta.ca)
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* fixed tick loss calculation in timer_interrupt
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* (round system clock to nearest tick instead of truncating)
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* fixed algorithm in time_init for getting time from CMOS clock
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* 1999-04-16 Thorsten Kranzkowski (dl8bcu@gmx.net)
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* fixed algorithm in do_gettimeofday() for calculating the precise time
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* from processor cycle counter (now taking lost_ticks into account)
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* 2003-06-03 R. Scott Bailey <scott.bailey@eds.com>
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* Tighten sanity in time_init from 1% (10,000 PPM) to 250 PPM
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*/
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <linux/mm.h>
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#include <linux/delay.h>
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/bcd.h>
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#include <linux/profile.h>
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#include <linux/irq_work.h>
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#include <linux/uaccess.h>
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#include <asm/io.h>
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#include <asm/hwrpb.h>
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#include <linux/mc146818rtc.h>
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#include <linux/time.h>
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#include <linux/timex.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include "proto.h"
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#include "irq_impl.h"
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DEFINE_SPINLOCK(rtc_lock);
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EXPORT_SYMBOL(rtc_lock);
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unsigned long est_cycle_freq;
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#ifdef CONFIG_IRQ_WORK
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DEFINE_PER_CPU(u8, irq_work_pending);
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#define set_irq_work_pending_flag() __this_cpu_write(irq_work_pending, 1)
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#define test_irq_work_pending() __this_cpu_read(irq_work_pending)
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#define clear_irq_work_pending() __this_cpu_write(irq_work_pending, 0)
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void arch_irq_work_raise(void)
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{
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set_irq_work_pending_flag();
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}
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#else /* CONFIG_IRQ_WORK */
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#define test_irq_work_pending() 0
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#define clear_irq_work_pending()
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#endif /* CONFIG_IRQ_WORK */
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static inline __u32 rpcc(void)
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{
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return __builtin_alpha_rpcc();
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}
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/*
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* The RTC as a clock_event_device primitive.
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*/
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static DEFINE_PER_CPU(struct clock_event_device, cpu_ce);
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irqreturn_t
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rtc_timer_interrupt(int irq, void *dev)
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{
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int cpu = smp_processor_id();
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struct clock_event_device *ce = &per_cpu(cpu_ce, cpu);
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/* Don't run the hook for UNUSED or SHUTDOWN. */
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if (likely(clockevent_state_periodic(ce)))
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ce->event_handler(ce);
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if (test_irq_work_pending()) {
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clear_irq_work_pending();
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irq_work_run();
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}
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return IRQ_HANDLED;
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}
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static int
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rtc_ce_set_next_event(unsigned long evt, struct clock_event_device *ce)
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{
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/* This hook is for oneshot mode, which we don't support. */
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return -EINVAL;
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}
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static void __init
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init_rtc_clockevent(void)
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{
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int cpu = smp_processor_id();
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struct clock_event_device *ce = &per_cpu(cpu_ce, cpu);
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*ce = (struct clock_event_device){
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.name = "rtc",
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.features = CLOCK_EVT_FEAT_PERIODIC,
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.rating = 100,
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.cpumask = cpumask_of(cpu),
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.set_next_event = rtc_ce_set_next_event,
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};
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clockevents_config_and_register(ce, CONFIG_HZ, 0, 0);
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}
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/*
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* The QEMU clock as a clocksource primitive.
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*/
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static u64
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qemu_cs_read(struct clocksource *cs)
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{
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return qemu_get_vmtime();
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}
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static struct clocksource qemu_cs = {
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.name = "qemu",
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.rating = 400,
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.read = qemu_cs_read,
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.mask = CLOCKSOURCE_MASK(64),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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.max_idle_ns = LONG_MAX
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};
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/*
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* The QEMU alarm as a clock_event_device primitive.
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*/
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static int qemu_ce_shutdown(struct clock_event_device *ce)
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{
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/* The mode member of CE is updated for us in generic code.
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Just make sure that the event is disabled. */
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qemu_set_alarm_abs(0);
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return 0;
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}
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static int
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qemu_ce_set_next_event(unsigned long evt, struct clock_event_device *ce)
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{
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qemu_set_alarm_rel(evt);
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return 0;
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}
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static irqreturn_t
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qemu_timer_interrupt(int irq, void *dev)
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{
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int cpu = smp_processor_id();
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struct clock_event_device *ce = &per_cpu(cpu_ce, cpu);
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ce->event_handler(ce);
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return IRQ_HANDLED;
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}
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static void __init
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init_qemu_clockevent(void)
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{
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int cpu = smp_processor_id();
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struct clock_event_device *ce = &per_cpu(cpu_ce, cpu);
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*ce = (struct clock_event_device){
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.name = "qemu",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.rating = 400,
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.cpumask = cpumask_of(cpu),
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.set_state_shutdown = qemu_ce_shutdown,
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.set_state_oneshot = qemu_ce_shutdown,
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.tick_resume = qemu_ce_shutdown,
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.set_next_event = qemu_ce_set_next_event,
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};
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clockevents_config_and_register(ce, NSEC_PER_SEC, 1000, LONG_MAX);
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}
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void __init
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common_init_rtc(void)
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{
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unsigned char x, sel = 0;
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/* Reset periodic interrupt frequency. */
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#if CONFIG_HZ == 1024 || CONFIG_HZ == 1200
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x = CMOS_READ(RTC_FREQ_SELECT) & 0x3f;
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/* Test includes known working values on various platforms
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where 0x26 is wrong; we refuse to change those. */
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if (x != 0x26 && x != 0x25 && x != 0x19 && x != 0x06) {
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sel = RTC_REF_CLCK_32KHZ + 6;
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}
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#elif CONFIG_HZ == 256 || CONFIG_HZ == 128 || CONFIG_HZ == 64 || CONFIG_HZ == 32
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sel = RTC_REF_CLCK_32KHZ + __builtin_ffs(32768 / CONFIG_HZ);
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#else
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# error "Unknown HZ from arch/alpha/Kconfig"
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#endif
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if (sel) {
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printk(KERN_INFO "Setting RTC_FREQ to %d Hz (%x)\n",
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CONFIG_HZ, sel);
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CMOS_WRITE(sel, RTC_FREQ_SELECT);
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}
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/* Turn on periodic interrupts. */
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x = CMOS_READ(RTC_CONTROL);
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if (!(x & RTC_PIE)) {
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printk("Turning on RTC interrupts.\n");
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x |= RTC_PIE;
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x &= ~(RTC_AIE | RTC_UIE);
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CMOS_WRITE(x, RTC_CONTROL);
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}
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(void) CMOS_READ(RTC_INTR_FLAGS);
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outb(0x36, 0x43); /* pit counter 0: system timer */
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outb(0x00, 0x40);
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outb(0x00, 0x40);
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outb(0xb6, 0x43); /* pit counter 2: speaker */
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outb(0x31, 0x42);
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outb(0x13, 0x42);
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init_rtc_irq();
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}
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#ifndef CONFIG_ALPHA_WTINT
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/*
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* The RPCC as a clocksource primitive.
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*
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* While we have free-running timecounters running on all CPUs, and we make
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* a half-hearted attempt in init_rtc_rpcc_info to sync the timecounter
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* with the wall clock, that initialization isn't kept up-to-date across
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* different time counters in SMP mode. Therefore we can only use this
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* method when there's only one CPU enabled.
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*
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* When using the WTINT PALcall, the RPCC may shift to a lower frequency,
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* or stop altogether, while waiting for the interrupt. Therefore we cannot
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* use this method when WTINT is in use.
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*/
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static u64 read_rpcc(struct clocksource *cs)
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{
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return rpcc();
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}
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static struct clocksource clocksource_rpcc = {
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.name = "rpcc",
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.rating = 300,
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.read = read_rpcc,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS
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};
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#endif /* ALPHA_WTINT */
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/* Validate a computed cycle counter result against the known bounds for
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the given processor core. There's too much brokenness in the way of
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timing hardware for any one method to work everywhere. :-(
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Return 0 if the result cannot be trusted, otherwise return the argument. */
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static unsigned long __init
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validate_cc_value(unsigned long cc)
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{
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static struct bounds {
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unsigned int min, max;
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} cpu_hz[] __initdata = {
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[EV3_CPU] = { 50000000, 200000000 }, /* guess */
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[EV4_CPU] = { 100000000, 300000000 },
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[LCA4_CPU] = { 100000000, 300000000 }, /* guess */
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[EV45_CPU] = { 200000000, 300000000 },
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[EV5_CPU] = { 250000000, 433000000 },
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[EV56_CPU] = { 333000000, 667000000 },
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[PCA56_CPU] = { 400000000, 600000000 }, /* guess */
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[PCA57_CPU] = { 500000000, 600000000 }, /* guess */
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[EV6_CPU] = { 466000000, 600000000 },
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[EV67_CPU] = { 600000000, 750000000 },
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[EV68AL_CPU] = { 750000000, 940000000 },
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[EV68CB_CPU] = { 1000000000, 1333333333 },
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/* None of the following are shipping as of 2001-11-01. */
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[EV68CX_CPU] = { 1000000000, 1700000000 }, /* guess */
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[EV69_CPU] = { 1000000000, 1700000000 }, /* guess */
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[EV7_CPU] = { 800000000, 1400000000 }, /* guess */
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[EV79_CPU] = { 1000000000, 2000000000 }, /* guess */
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};
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/* Allow for some drift in the crystal. 10MHz is more than enough. */
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const unsigned int deviation = 10000000;
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struct percpu_struct *cpu;
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unsigned int index;
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cpu = (struct percpu_struct *)((char*)hwrpb + hwrpb->processor_offset);
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index = cpu->type & 0xffffffff;
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/* If index out of bounds, no way to validate. */
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if (index >= ARRAY_SIZE(cpu_hz))
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return cc;
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/* If index contains no data, no way to validate. */
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if (cpu_hz[index].max == 0)
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return cc;
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if (cc < cpu_hz[index].min - deviation
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|| cc > cpu_hz[index].max + deviation)
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return 0;
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return cc;
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}
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/*
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* Calibrate CPU clock using legacy 8254 timer/counter. Stolen from
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* arch/i386/time.c.
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*/
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#define CALIBRATE_LATCH 0xffff
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#define TIMEOUT_COUNT 0x100000
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static unsigned long __init
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calibrate_cc_with_pit(void)
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{
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int cc, count = 0;
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/* Set the Gate high, disable speaker */
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outb((inb(0x61) & ~0x02) | 0x01, 0x61);
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/*
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* Now let's take care of CTC channel 2
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*
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* Set the Gate high, program CTC channel 2 for mode 0,
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* (interrupt on terminal count mode), binary count,
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* load 5 * LATCH count, (LSB and MSB) to begin countdown.
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*/
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outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */
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outb(CALIBRATE_LATCH & 0xff, 0x42); /* LSB of count */
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outb(CALIBRATE_LATCH >> 8, 0x42); /* MSB of count */
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cc = rpcc();
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do {
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count++;
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} while ((inb(0x61) & 0x20) == 0 && count < TIMEOUT_COUNT);
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cc = rpcc() - cc;
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/* Error: ECTCNEVERSET or ECPUTOOFAST. */
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if (count <= 1 || count == TIMEOUT_COUNT)
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return 0;
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return ((long)cc * PIT_TICK_RATE) / (CALIBRATE_LATCH + 1);
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}
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/* The Linux interpretation of the CMOS clock register contents:
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When the Update-In-Progress (UIP) flag goes from 1 to 0, the
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RTC registers show the second which has precisely just started.
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Let's hope other operating systems interpret the RTC the same way. */
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static unsigned long __init
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rpcc_after_update_in_progress(void)
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{
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do { } while (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP));
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do { } while (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP);
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return rpcc();
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}
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void __init
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time_init(void)
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{
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unsigned int cc1, cc2;
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unsigned long cycle_freq, tolerance;
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long diff;
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if (alpha_using_qemu) {
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clocksource_register_hz(&qemu_cs, NSEC_PER_SEC);
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init_qemu_clockevent();
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timer_irqaction.handler = qemu_timer_interrupt;
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init_rtc_irq();
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return;
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}
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/* Calibrate CPU clock -- attempt #1. */
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if (!est_cycle_freq)
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est_cycle_freq = validate_cc_value(calibrate_cc_with_pit());
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cc1 = rpcc();
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/* Calibrate CPU clock -- attempt #2. */
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if (!est_cycle_freq) {
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cc1 = rpcc_after_update_in_progress();
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cc2 = rpcc_after_update_in_progress();
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est_cycle_freq = validate_cc_value(cc2 - cc1);
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cc1 = cc2;
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}
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cycle_freq = hwrpb->cycle_freq;
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if (est_cycle_freq) {
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/* If the given value is within 250 PPM of what we calculated,
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accept it. Otherwise, use what we found. */
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tolerance = cycle_freq / 4000;
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diff = cycle_freq - est_cycle_freq;
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if (diff < 0)
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diff = -diff;
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if ((unsigned long)diff > tolerance) {
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cycle_freq = est_cycle_freq;
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printk("HWRPB cycle frequency bogus. "
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"Estimated %lu Hz\n", cycle_freq);
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} else {
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est_cycle_freq = 0;
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}
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} else if (! validate_cc_value (cycle_freq)) {
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printk("HWRPB cycle frequency bogus, "
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"and unable to estimate a proper value!\n");
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}
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/* See above for restrictions on using clocksource_rpcc. */
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#ifndef CONFIG_ALPHA_WTINT
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if (hwrpb->nr_processors == 1)
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clocksource_register_hz(&clocksource_rpcc, cycle_freq);
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#endif
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/* Startup the timer source. */
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alpha_mv.init_rtc();
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init_rtc_clockevent();
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}
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/* Initialize the clock_event_device for secondary cpus. */
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#ifdef CONFIG_SMP
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void __init
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init_clockevent(void)
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{
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if (alpha_using_qemu)
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init_qemu_clockevent();
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else
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init_rtc_clockevent();
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}
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#endif
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