412 строки
10 KiB
C
412 строки
10 KiB
C
/*
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* SH7206 Setup
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*
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* Copyright (C) 2006 Yoshinori Sato
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* Copyright (C) 2009 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_timer.h>
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#include <linux/io.h>
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
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PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
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ADC_ADI0, ADC_ADI1,
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DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
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MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
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MTU3_ABCD, MTU4_ABCD, MTU5, POE2_12, MTU3S_ABCD, MTU4S_ABCD, MTU5S,
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IIC3,
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CMT0, CMT1, BSC, WDT,
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MTU2_TCI3V, MTU2_TCI4V, MTU2S_TCI3V, MTU2S_TCI4V,
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POE2_OEI3,
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SCIF0, SCIF1, SCIF2, SCIF3,
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/* interrupt groups */
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PINT,
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};
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static struct intc_vect vectors[] __initdata = {
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INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
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INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
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INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
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INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
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INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
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INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
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INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
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INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
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INTC_IRQ(ADC_ADI0, 92), INTC_IRQ(ADC_ADI1, 96),
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INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
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INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
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INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
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INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
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INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
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INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
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INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
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INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
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INTC_IRQ(CMT0, 140), INTC_IRQ(CMT1, 144),
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INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152),
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INTC_IRQ(MTU0_ABCD, 156), INTC_IRQ(MTU0_ABCD, 157),
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INTC_IRQ(MTU0_ABCD, 158), INTC_IRQ(MTU0_ABCD, 159),
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INTC_IRQ(MTU0_VEF, 160), INTC_IRQ(MTU0_VEF, 161),
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INTC_IRQ(MTU0_VEF, 162),
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INTC_IRQ(MTU1_AB, 164), INTC_IRQ(MTU1_AB, 165),
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INTC_IRQ(MTU1_VU, 168), INTC_IRQ(MTU1_VU, 169),
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INTC_IRQ(MTU2_AB, 172), INTC_IRQ(MTU2_AB, 173),
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INTC_IRQ(MTU2_VU, 176), INTC_IRQ(MTU2_VU, 177),
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INTC_IRQ(MTU3_ABCD, 180), INTC_IRQ(MTU3_ABCD, 181),
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INTC_IRQ(MTU3_ABCD, 182), INTC_IRQ(MTU3_ABCD, 183),
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INTC_IRQ(MTU2_TCI3V, 184),
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INTC_IRQ(MTU4_ABCD, 188), INTC_IRQ(MTU4_ABCD, 189),
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INTC_IRQ(MTU4_ABCD, 190), INTC_IRQ(MTU4_ABCD, 191),
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INTC_IRQ(MTU2_TCI4V, 192),
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INTC_IRQ(MTU5, 196), INTC_IRQ(MTU5, 197),
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INTC_IRQ(MTU5, 198),
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INTC_IRQ(POE2_12, 200), INTC_IRQ(POE2_12, 201),
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INTC_IRQ(MTU3S_ABCD, 204), INTC_IRQ(MTU3S_ABCD, 205),
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INTC_IRQ(MTU3S_ABCD, 206), INTC_IRQ(MTU3S_ABCD, 207),
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INTC_IRQ(MTU2S_TCI3V, 208),
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INTC_IRQ(MTU4S_ABCD, 212), INTC_IRQ(MTU4S_ABCD, 213),
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INTC_IRQ(MTU4S_ABCD, 214), INTC_IRQ(MTU4S_ABCD, 215),
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INTC_IRQ(MTU2S_TCI4V, 216),
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INTC_IRQ(MTU5S, 220), INTC_IRQ(MTU5S, 221),
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INTC_IRQ(MTU5S, 222),
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INTC_IRQ(POE2_OEI3, 224),
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INTC_IRQ(IIC3, 228), INTC_IRQ(IIC3, 229),
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INTC_IRQ(IIC3, 230), INTC_IRQ(IIC3, 231),
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INTC_IRQ(IIC3, 232),
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INTC_IRQ(SCIF0, 240), INTC_IRQ(SCIF0, 241),
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INTC_IRQ(SCIF0, 242), INTC_IRQ(SCIF0, 243),
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INTC_IRQ(SCIF1, 244), INTC_IRQ(SCIF1, 245),
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INTC_IRQ(SCIF1, 246), INTC_IRQ(SCIF1, 247),
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INTC_IRQ(SCIF2, 248), INTC_IRQ(SCIF2, 249),
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INTC_IRQ(SCIF2, 250), INTC_IRQ(SCIF2, 251),
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INTC_IRQ(SCIF3, 252), INTC_IRQ(SCIF3, 253),
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INTC_IRQ(SCIF3, 254), INTC_IRQ(SCIF3, 255),
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};
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
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PINT4, PINT5, PINT6, PINT7),
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};
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static struct intc_prio_reg prio_registers[] __initdata = {
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{ 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
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{ 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
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{ 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI0, ADC_ADI1 } },
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{ 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
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{ 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
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{ 0xfffe0c04, 0, 16, 4, /* IPR08 */ { CMT0, CMT1, BSC, WDT } },
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{ 0xfffe0c06, 0, 16, 4, /* IPR09 */ { MTU0_ABCD, MTU0_VEF,
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MTU1_AB, MTU1_VU } },
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{ 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU2_AB, MTU2_VU,
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MTU3_ABCD, MTU2_TCI3V } },
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{ 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU4_ABCD, MTU2_TCI4V,
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MTU5, POE2_12 } },
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{ 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU3S_ABCD, MTU2S_TCI3V,
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MTU4S_ABCD, MTU2S_TCI4V } },
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{ 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU5S, POE2_OEI3, IIC3, 0 } },
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{ 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
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};
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static struct intc_mask_reg mask_registers[] __initdata = {
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{ 0xfffe0808, 0, 16, /* PINTER */
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{ 0, 0, 0, 0, 0, 0, 0, 0,
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PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
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};
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static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups,
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mask_registers, prio_registers, NULL);
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static struct plat_sci_port scif0_platform_data = {
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
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.type = PORT_SCIF,
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};
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static struct resource scif0_resources[] = {
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DEFINE_RES_MEM(0xfffe8000, 0x100),
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DEFINE_RES_IRQ(240),
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};
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static struct platform_device scif0_device = {
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.name = "sh-sci",
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.id = 0,
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.resource = scif0_resources,
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.num_resources = ARRAY_SIZE(scif0_resources),
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.dev = {
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.platform_data = &scif0_platform_data,
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},
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};
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static struct plat_sci_port scif1_platform_data = {
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
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.type = PORT_SCIF,
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};
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static struct resource scif1_resources[] = {
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DEFINE_RES_MEM(0xfffe8800, 0x100),
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DEFINE_RES_IRQ(244),
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};
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static struct platform_device scif1_device = {
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.name = "sh-sci",
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.id = 1,
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.resource = scif1_resources,
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.num_resources = ARRAY_SIZE(scif1_resources),
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.dev = {
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.platform_data = &scif1_platform_data,
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},
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};
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static struct plat_sci_port scif2_platform_data = {
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
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.type = PORT_SCIF,
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};
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static struct resource scif2_resources[] = {
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DEFINE_RES_MEM(0xfffe9000, 0x100),
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DEFINE_RES_IRQ(248),
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};
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static struct platform_device scif2_device = {
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.name = "sh-sci",
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.id = 2,
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.resource = scif2_resources,
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.num_resources = ARRAY_SIZE(scif2_resources),
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.dev = {
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.platform_data = &scif2_platform_data,
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},
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};
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static struct plat_sci_port scif3_platform_data = {
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
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.type = PORT_SCIF,
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};
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static struct resource scif3_resources[] = {
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DEFINE_RES_MEM(0xfffe9800, 0x100),
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DEFINE_RES_IRQ(252),
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};
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static struct platform_device scif3_device = {
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.name = "sh-sci",
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.id = 3,
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.resource = scif3_resources,
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.num_resources = ARRAY_SIZE(scif3_resources),
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.dev = {
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.platform_data = &scif3_platform_data,
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},
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};
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static struct sh_timer_config cmt0_platform_data = {
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.channel_offset = 0x02,
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.timer_bit = 0,
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.clockevent_rating = 125,
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.clocksource_rating = 0, /* disabled due to code generation issues */
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};
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static struct resource cmt0_resources[] = {
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[0] = {
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.start = 0xfffec002,
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.end = 0xfffec007,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 140,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device cmt0_device = {
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.name = "sh_cmt",
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.id = 0,
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.dev = {
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.platform_data = &cmt0_platform_data,
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},
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.resource = cmt0_resources,
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.num_resources = ARRAY_SIZE(cmt0_resources),
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};
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static struct sh_timer_config cmt1_platform_data = {
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.channel_offset = 0x08,
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.timer_bit = 1,
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.clockevent_rating = 125,
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.clocksource_rating = 0, /* disabled due to code generation issues */
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};
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static struct resource cmt1_resources[] = {
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[0] = {
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.start = 0xfffec008,
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.end = 0xfffec00d,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 144,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device cmt1_device = {
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.name = "sh_cmt",
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.id = 1,
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.dev = {
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.platform_data = &cmt1_platform_data,
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},
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.resource = cmt1_resources,
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.num_resources = ARRAY_SIZE(cmt1_resources),
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};
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static struct sh_timer_config mtu2_0_platform_data = {
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.channel_offset = -0x80,
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.timer_bit = 0,
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.clockevent_rating = 200,
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};
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static struct resource mtu2_0_resources[] = {
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[0] = {
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.start = 0xfffe4300,
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.end = 0xfffe4326,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 156,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mtu2_0_device = {
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.name = "sh_mtu2",
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.id = 0,
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.dev = {
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.platform_data = &mtu2_0_platform_data,
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},
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.resource = mtu2_0_resources,
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.num_resources = ARRAY_SIZE(mtu2_0_resources),
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};
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static struct sh_timer_config mtu2_1_platform_data = {
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.channel_offset = -0x100,
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.timer_bit = 1,
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.clockevent_rating = 200,
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};
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static struct resource mtu2_1_resources[] = {
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[0] = {
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.start = 0xfffe4380,
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.end = 0xfffe4390,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 164,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mtu2_1_device = {
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.name = "sh_mtu2",
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.id = 1,
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.dev = {
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.platform_data = &mtu2_1_platform_data,
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},
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.resource = mtu2_1_resources,
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.num_resources = ARRAY_SIZE(mtu2_1_resources),
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};
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static struct sh_timer_config mtu2_2_platform_data = {
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.channel_offset = 0x80,
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.timer_bit = 2,
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.clockevent_rating = 200,
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};
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static struct resource mtu2_2_resources[] = {
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[0] = {
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.start = 0xfffe4000,
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.end = 0xfffe400a,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 180,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mtu2_2_device = {
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.name = "sh_mtu2",
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.id = 2,
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.dev = {
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.platform_data = &mtu2_2_platform_data,
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},
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.resource = mtu2_2_resources,
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.num_resources = ARRAY_SIZE(mtu2_2_resources),
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};
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static struct platform_device *sh7206_devices[] __initdata = {
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&scif0_device,
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&scif1_device,
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&scif2_device,
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&scif3_device,
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&cmt0_device,
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&cmt1_device,
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&mtu2_0_device,
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&mtu2_1_device,
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&mtu2_2_device,
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};
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static int __init sh7206_devices_setup(void)
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{
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return platform_add_devices(sh7206_devices,
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ARRAY_SIZE(sh7206_devices));
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}
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arch_initcall(sh7206_devices_setup);
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void __init plat_irq_setup(void)
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{
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register_intc_controller(&intc_desc);
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}
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static struct platform_device *sh7206_early_devices[] __initdata = {
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&scif0_device,
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&scif1_device,
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&scif2_device,
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&scif3_device,
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&cmt0_device,
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&cmt1_device,
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&mtu2_0_device,
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&mtu2_1_device,
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&mtu2_2_device,
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};
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#define STBCR3 0xfffe0408
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#define STBCR4 0xfffe040c
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void __init plat_early_device_setup(void)
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{
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/* enable CMT clock */
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__raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);
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/* enable MTU2 clock */
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__raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
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early_platform_add_devices(sh7206_early_devices,
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ARRAY_SIZE(sh7206_early_devices));
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}
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