224 строки
5.3 KiB
C
224 строки
5.3 KiB
C
/*
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* Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
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* Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include <linux/export.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <video/imx-ipu-v3.h>
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#include "ipu-prv.h"
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#define DMFC_RD_CHAN 0x0000
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#define DMFC_WR_CHAN 0x0004
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#define DMFC_WR_CHAN_DEF 0x0008
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#define DMFC_DP_CHAN 0x000c
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#define DMFC_DP_CHAN_DEF 0x0010
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#define DMFC_GENERAL1 0x0014
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#define DMFC_GENERAL2 0x0018
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#define DMFC_IC_CTRL 0x001c
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#define DMFC_WR_CHAN_ALT 0x0020
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#define DMFC_WR_CHAN_DEF_ALT 0x0024
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#define DMFC_DP_CHAN_ALT 0x0028
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#define DMFC_DP_CHAN_DEF_ALT 0x002c
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#define DMFC_GENERAL1_ALT 0x0030
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#define DMFC_STAT 0x0034
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#define DMFC_WR_CHAN_1_28 0
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#define DMFC_WR_CHAN_2_41 8
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#define DMFC_WR_CHAN_1C_42 16
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#define DMFC_WR_CHAN_2C_43 24
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#define DMFC_DP_CHAN_5B_23 0
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#define DMFC_DP_CHAN_5F_27 8
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#define DMFC_DP_CHAN_6B_24 16
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#define DMFC_DP_CHAN_6F_29 24
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struct dmfc_channel_data {
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int ipu_channel;
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unsigned long channel_reg;
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unsigned long shift;
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unsigned eot_shift;
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unsigned max_fifo_lines;
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};
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static const struct dmfc_channel_data dmfcdata[] = {
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{
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.ipu_channel = IPUV3_CHANNEL_MEM_BG_SYNC,
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.channel_reg = DMFC_DP_CHAN,
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.shift = DMFC_DP_CHAN_5B_23,
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.eot_shift = 20,
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.max_fifo_lines = 3,
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}, {
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.ipu_channel = 24,
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.channel_reg = DMFC_DP_CHAN,
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.shift = DMFC_DP_CHAN_6B_24,
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.eot_shift = 22,
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.max_fifo_lines = 1,
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}, {
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.ipu_channel = IPUV3_CHANNEL_MEM_FG_SYNC,
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.channel_reg = DMFC_DP_CHAN,
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.shift = DMFC_DP_CHAN_5F_27,
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.eot_shift = 21,
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.max_fifo_lines = 2,
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}, {
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.ipu_channel = IPUV3_CHANNEL_MEM_DC_SYNC,
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.channel_reg = DMFC_WR_CHAN,
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.shift = DMFC_WR_CHAN_1_28,
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.eot_shift = 16,
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.max_fifo_lines = 2,
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}, {
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.ipu_channel = 29,
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.channel_reg = DMFC_DP_CHAN,
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.shift = DMFC_DP_CHAN_6F_29,
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.eot_shift = 23,
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.max_fifo_lines = 1,
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},
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};
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#define DMFC_NUM_CHANNELS ARRAY_SIZE(dmfcdata)
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struct ipu_dmfc_priv;
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struct dmfc_channel {
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unsigned slots;
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struct ipu_soc *ipu;
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struct ipu_dmfc_priv *priv;
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const struct dmfc_channel_data *data;
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};
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struct ipu_dmfc_priv {
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struct ipu_soc *ipu;
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struct device *dev;
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struct dmfc_channel channels[DMFC_NUM_CHANNELS];
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struct mutex mutex;
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void __iomem *base;
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int use_count;
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};
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int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc)
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{
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struct ipu_dmfc_priv *priv = dmfc->priv;
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mutex_lock(&priv->mutex);
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if (!priv->use_count)
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ipu_module_enable(priv->ipu, IPU_CONF_DMFC_EN);
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priv->use_count++;
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mutex_unlock(&priv->mutex);
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return 0;
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}
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EXPORT_SYMBOL_GPL(ipu_dmfc_enable_channel);
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void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc)
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{
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struct ipu_dmfc_priv *priv = dmfc->priv;
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mutex_lock(&priv->mutex);
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priv->use_count--;
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if (!priv->use_count)
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ipu_module_disable(priv->ipu, IPU_CONF_DMFC_EN);
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if (priv->use_count < 0)
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priv->use_count = 0;
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mutex_unlock(&priv->mutex);
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}
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EXPORT_SYMBOL_GPL(ipu_dmfc_disable_channel);
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void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width)
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{
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struct ipu_dmfc_priv *priv = dmfc->priv;
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u32 dmfc_gen1;
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mutex_lock(&priv->mutex);
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dmfc_gen1 = readl(priv->base + DMFC_GENERAL1);
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if ((dmfc->slots * 64 * 4) / width > dmfc->data->max_fifo_lines)
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dmfc_gen1 |= 1 << dmfc->data->eot_shift;
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else
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dmfc_gen1 &= ~(1 << dmfc->data->eot_shift);
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writel(dmfc_gen1, priv->base + DMFC_GENERAL1);
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mutex_unlock(&priv->mutex);
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}
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EXPORT_SYMBOL_GPL(ipu_dmfc_config_wait4eot);
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struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipu_channel)
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{
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struct ipu_dmfc_priv *priv = ipu->dmfc_priv;
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int i;
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for (i = 0; i < DMFC_NUM_CHANNELS; i++)
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if (dmfcdata[i].ipu_channel == ipu_channel)
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return &priv->channels[i];
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return ERR_PTR(-ENODEV);
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}
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EXPORT_SYMBOL_GPL(ipu_dmfc_get);
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void ipu_dmfc_put(struct dmfc_channel *dmfc)
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{
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}
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EXPORT_SYMBOL_GPL(ipu_dmfc_put);
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int ipu_dmfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
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struct clk *ipu_clk)
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{
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struct ipu_dmfc_priv *priv;
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int i;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->base = devm_ioremap(dev, base, PAGE_SIZE);
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if (!priv->base)
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return -ENOMEM;
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priv->dev = dev;
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priv->ipu = ipu;
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mutex_init(&priv->mutex);
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ipu->dmfc_priv = priv;
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for (i = 0; i < DMFC_NUM_CHANNELS; i++) {
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priv->channels[i].priv = priv;
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priv->channels[i].ipu = ipu;
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priv->channels[i].data = &dmfcdata[i];
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if (dmfcdata[i].ipu_channel == IPUV3_CHANNEL_MEM_BG_SYNC ||
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dmfcdata[i].ipu_channel == IPUV3_CHANNEL_MEM_FG_SYNC ||
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dmfcdata[i].ipu_channel == IPUV3_CHANNEL_MEM_DC_SYNC)
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priv->channels[i].slots = 2;
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}
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writel(0x00000050, priv->base + DMFC_WR_CHAN);
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writel(0x00005654, priv->base + DMFC_DP_CHAN);
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writel(0x202020f6, priv->base + DMFC_WR_CHAN_DEF);
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writel(0x2020f6f6, priv->base + DMFC_DP_CHAN_DEF);
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writel(0x00000003, priv->base + DMFC_GENERAL1);
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return 0;
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}
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void ipu_dmfc_exit(struct ipu_soc *ipu)
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{
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}
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