microsoft
/
WSL2-Linux-Kernel
зеркало из https://github.com/microsoft/WSL2-Linux-Kernel.git
1
0
Форкнуть 0
Код Задачи Пакеты Проекты Релизы Вики Активность
WSL2-Linux-Kernel/drivers/fpga
История
Kang Luwei 29de76240e fpga: dfl: fme: add partial reconfiguration sub feature support 
Partial Reconfiguration (PR) is the most important function for FME. It
allows reconfiguration for given Port/Accelerated Function Unit (AFU).

It creates platform devices for fpga-mgr, fpga-regions and fpga-bridges,
and invokes fpga-region's interface (fpga_region_program_fpga) for PR
operation once PR request received via ioctl. Below user space interface
is exposed by this sub feature.

Ioctl interface:
* DFL_FPGA_FME_PORT_PR
  Do partial reconfiguration per information from userspace, including
  target port(AFU), buffer size and address info. It returns error code
  to userspace if failed. For detailed PR error information, user needs
  to read fpga-mgr's status sysfs interface.

Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
Signed-off-by: Shiva Rao <shiva.rao@intel.com>
Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
Signed-off-by: Kang Luwei <luwei.kang@intel.com>
Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Wu Hao <hao.wu@intel.com>
Acked-by: Alan Tull <atull@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 		2018-07-15 13:55:46 +02:00
..
Kconfig fpga: dfl: add FPGA Management Engine driver basic framework 2018-07-15 13:55:45 +02:00
Makefile fpga: dfl: fme: add partial reconfiguration sub feature support 2018-07-15 13:55:46 +02:00
altera-cvp.c fpga: manager: change api, don't use drvdata 2018-05-25 18:23:55 +02:00
altera-fpga2sdram.c fpga: use SPDX 2018-05-25 18:23:56 +02:00
altera-freeze-bridge.c fpga: use SPDX 2018-05-25 18:23:56 +02:00
altera-hps2fpga.c fpga: use SPDX 2018-05-25 18:23:56 +02:00
altera-pr-ip-core-plat.c fpga: use SPDX 2018-05-25 18:23:56 +02:00
altera-pr-ip-core.c fpga: use SPDX 2018-05-25 18:23:56 +02:00
altera-ps-spi.c fpga: manager: change api, don't use drvdata 2018-05-25 18:23:55 +02:00
dfl-fme-main.c fpga: dfl: fme: add partial reconfiguration sub feature support 2018-07-15 13:55:46 +02:00
dfl-fme-pr.c fpga: dfl: fme: add partial reconfiguration sub feature support 2018-07-15 13:55:46 +02:00
dfl-fme-pr.h fpga: dfl: fme: add partial reconfiguration sub feature support 2018-07-15 13:55:46 +02:00
dfl-fme.h fpga: dfl: fme: add partial reconfiguration sub feature support 2018-07-15 13:55:46 +02:00
dfl-pci.c fpga: dfl-pci: add enumeration for feature devices 2018-07-15 13:55:45 +02:00
dfl.c fpga: dfl: add dfl_fpga_check_port_id function. 2018-07-15 13:55:45 +02:00
dfl.h fpga: dfl: add dfl_fpga_check_port_id function. 2018-07-15 13:55:45 +02:00
fpga-bridge.c fpga: clarify that unregister functions also free 2018-05-25 18:23:56 +02:00
fpga-mgr.c fpga: mgr: add status for fpga-manager 2018-07-15 13:55:44 +02:00
fpga-region.c fpga: region: add compat_id support 2018-07-15 13:55:44 +02:00
ice40-spi.c fpga: manager: change api, don't use drvdata 2018-05-25 18:23:55 +02:00
machxo2-spi.c fpga: manager: change api, don't use drvdata 2018-05-25 18:23:55 +02:00
of-fpga-region.c fpga: use SPDX 2018-05-25 18:23:56 +02:00
socfpga-a10.c fpga: use SPDX 2018-05-25 18:23:56 +02:00
socfpga.c fpga: use SPDX 2018-05-25 18:23:56 +02:00
ts73xx-fpga.c fpga: manager: change api, don't use drvdata 2018-05-25 18:23:55 +02:00
xilinx-pr-decoupler.c fpga: bridge: change api, don't use drvdata 2018-05-25 18:23:55 +02:00
xilinx-spi.c fpga: manager: change api, don't use drvdata 2018-05-25 18:23:55 +02:00
zynq-fpga.c fpga: manager: change api, don't use drvdata 2018-05-25 18:23:55 +02:00