892 строки
32 KiB
Plaintext
892 строки
32 KiB
Plaintext
Intel Processor Trace
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=====================
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Overview
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========
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Intel Processor Trace (Intel PT) is an extension of Intel Architecture that
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collects information about software execution such as control flow, execution
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modes and timings and formats it into highly compressed binary packets.
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Technical details are documented in the Intel 64 and IA-32 Architectures
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Software Developer Manuals, Chapter 36 Intel Processor Trace.
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Intel PT is first supported in Intel Core M and 5th generation Intel Core
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processors that are based on the Intel micro-architecture code name Broadwell.
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Trace data is collected by 'perf record' and stored within the perf.data file.
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See below for options to 'perf record'.
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Trace data must be 'decoded' which involves walking the object code and matching
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the trace data packets. For example a TNT packet only tells whether a
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conditional branch was taken or not taken, so to make use of that packet the
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decoder must know precisely which instruction was being executed.
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Decoding is done on-the-fly. The decoder outputs samples in the same format as
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samples output by perf hardware events, for example as though the "instructions"
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or "branches" events had been recorded. Presently 3 tools support this:
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'perf script', 'perf report' and 'perf inject'. See below for more information
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on using those tools.
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The main distinguishing feature of Intel PT is that the decoder can determine
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the exact flow of software execution. Intel PT can be used to understand why
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and how did software get to a certain point, or behave a certain way. The
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software does not have to be recompiled, so Intel PT works with debug or release
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builds, however the executed images are needed - which makes use in JIT-compiled
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environments, or with self-modified code, a challenge. Also symbols need to be
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provided to make sense of addresses.
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A limitation of Intel PT is that it produces huge amounts of trace data
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(hundreds of megabytes per second per core) which takes a long time to decode,
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for example two or three orders of magnitude longer than it took to collect.
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Another limitation is the performance impact of tracing, something that will
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vary depending on the use-case and architecture.
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Quickstart
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==========
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It is important to start small. That is because it is easy to capture vastly
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more data than can possibly be processed.
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The simplest thing to do with Intel PT is userspace profiling of small programs.
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Data is captured with 'perf record' e.g. to trace 'ls' userspace-only:
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perf record -e intel_pt//u ls
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And profiled with 'perf report' e.g.
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perf report
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To also trace kernel space presents a problem, namely kernel self-modifying
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code. A fairly good kernel image is available in /proc/kcore but to get an
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accurate image a copy of /proc/kcore needs to be made under the same conditions
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as the data capture. A script perf-with-kcore can do that, but beware that the
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script makes use of 'sudo' to copy /proc/kcore. If you have perf installed
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locally from the source tree you can do:
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~/libexec/perf-core/perf-with-kcore record pt_ls -e intel_pt// -- ls
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which will create a directory named 'pt_ls' and put the perf.data file and
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copies of /proc/kcore, /proc/kallsyms and /proc/modules into it. Then to use
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'perf report' becomes:
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~/libexec/perf-core/perf-with-kcore report pt_ls
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Because samples are synthesized after-the-fact, the sampling period can be
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selected for reporting. e.g. sample every microsecond
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~/libexec/perf-core/perf-with-kcore report pt_ls --itrace=i1usge
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See the sections below for more information about the --itrace option.
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Beware the smaller the period, the more samples that are produced, and the
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longer it takes to process them.
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Also note that the coarseness of Intel PT timing information will start to
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distort the statistical value of the sampling as the sampling period becomes
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smaller.
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To represent software control flow, "branches" samples are produced. By default
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a branch sample is synthesized for every single branch. To get an idea what
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data is available you can use the 'perf script' tool with no parameters, which
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will list all the samples.
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perf record -e intel_pt//u ls
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perf script
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An interesting field that is not printed by default is 'flags' which can be
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displayed as follows:
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perf script -Fcomm,tid,pid,time,cpu,event,trace,ip,sym,dso,addr,symoff,flags
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The flags are "bcrosyiABEx" which stand for branch, call, return, conditional,
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system, asynchronous, interrupt, transaction abort, trace begin, trace end, and
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in transaction, respectively.
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While it is possible to create scripts to analyze the data, an alternative
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approach is available to export the data to a sqlite or postgresql database.
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Refer to script export-to-sqlite.py or export-to-postgresql.py for more details,
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and to script call-graph-from-sql.py for an example of using the database.
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There is also script intel-pt-events.py which provides an example of how to
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unpack the raw data for power events and PTWRITE.
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As mentioned above, it is easy to capture too much data. One way to limit the
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data captured is to use 'snapshot' mode which is explained further below.
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Refer to 'new snapshot option' and 'Intel PT modes of operation' further below.
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Another problem that will be experienced is decoder errors. They can be caused
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by inability to access the executed image, self-modified or JIT-ed code, or the
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inability to match side-band information (such as context switches and mmaps)
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which results in the decoder not knowing what code was executed.
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There is also the problem of perf not being able to copy the data fast enough,
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resulting in data lost because the buffer was full. See 'Buffer handling' below
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for more details.
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perf record
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===========
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new event
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---------
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The Intel PT kernel driver creates a new PMU for Intel PT. PMU events are
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selected by providing the PMU name followed by the "config" separated by slashes.
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An enhancement has been made to allow default "config" e.g. the option
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-e intel_pt//
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will use a default config value. Currently that is the same as
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-e intel_pt/tsc,noretcomp=0/
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which is the same as
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-e intel_pt/tsc=1,noretcomp=0/
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Note there are now new config terms - see section 'config terms' further below.
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The config terms are listed in /sys/devices/intel_pt/format. They are bit
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fields within the config member of the struct perf_event_attr which is
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passed to the kernel by the perf_event_open system call. They correspond to bit
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fields in the IA32_RTIT_CTL MSR. Here is a list of them and their definitions:
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$ grep -H . /sys/bus/event_source/devices/intel_pt/format/*
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/sys/bus/event_source/devices/intel_pt/format/cyc:config:1
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/sys/bus/event_source/devices/intel_pt/format/cyc_thresh:config:19-22
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/sys/bus/event_source/devices/intel_pt/format/mtc:config:9
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/sys/bus/event_source/devices/intel_pt/format/mtc_period:config:14-17
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/sys/bus/event_source/devices/intel_pt/format/noretcomp:config:11
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/sys/bus/event_source/devices/intel_pt/format/psb_period:config:24-27
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/sys/bus/event_source/devices/intel_pt/format/tsc:config:10
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Note that the default config must be overridden for each term i.e.
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-e intel_pt/noretcomp=0/
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is the same as:
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-e intel_pt/tsc=1,noretcomp=0/
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So, to disable TSC packets use:
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-e intel_pt/tsc=0/
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It is also possible to specify the config value explicitly:
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-e intel_pt/config=0x400/
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Note that, as with all events, the event is suffixed with event modifiers:
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u userspace
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k kernel
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h hypervisor
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G guest
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H host
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p precise ip
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'h', 'G' and 'H' are for virtualization which is not supported by Intel PT.
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'p' is also not relevant to Intel PT. So only options 'u' and 'k' are
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meaningful for Intel PT.
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perf_event_attr is displayed if the -vv option is used e.g.
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------------------------------------------------------------
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perf_event_attr:
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type 6
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size 112
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config 0x400
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{ sample_period, sample_freq } 1
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sample_type IP|TID|TIME|CPU|IDENTIFIER
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read_format ID
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disabled 1
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inherit 1
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exclude_kernel 1
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exclude_hv 1
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enable_on_exec 1
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sample_id_all 1
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------------------------------------------------------------
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sys_perf_event_open: pid 31104 cpu 0 group_fd -1 flags 0x8
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sys_perf_event_open: pid 31104 cpu 1 group_fd -1 flags 0x8
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sys_perf_event_open: pid 31104 cpu 2 group_fd -1 flags 0x8
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sys_perf_event_open: pid 31104 cpu 3 group_fd -1 flags 0x8
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------------------------------------------------------------
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config terms
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------------
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The June 2015 version of Intel 64 and IA-32 Architectures Software Developer
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Manuals, Chapter 36 Intel Processor Trace, defined new Intel PT features.
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Some of the features are reflect in new config terms. All the config terms are
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described below.
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tsc Always supported. Produces TSC timestamp packets to provide
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timing information. In some cases it is possible to decode
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without timing information, for example a per-thread context
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that does not overlap executable memory maps.
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The default config selects tsc (i.e. tsc=1).
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noretcomp Always supported. Disables "return compression" so a TIP packet
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is produced when a function returns. Causes more packets to be
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produced but might make decoding more reliable.
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The default config does not select noretcomp (i.e. noretcomp=0).
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psb_period Allows the frequency of PSB packets to be specified.
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The PSB packet is a synchronization packet that provides a
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starting point for decoding or recovery from errors.
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Support for psb_period is indicated by:
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/sys/bus/event_source/devices/intel_pt/caps/psb_cyc
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which contains "1" if the feature is supported and "0"
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otherwise.
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Valid values are given by:
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/sys/bus/event_source/devices/intel_pt/caps/psb_periods
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which contains a hexadecimal value, the bits of which represent
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valid values e.g. bit 2 set means value 2 is valid.
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The psb_period value is converted to the approximate number of
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trace bytes between PSB packets as:
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2 ^ (value + 11)
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e.g. value 3 means 16KiB bytes between PSBs
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If an invalid value is entered, the error message
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will give a list of valid values e.g.
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$ perf record -e intel_pt/psb_period=15/u uname
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Invalid psb_period for intel_pt. Valid values are: 0-5
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If MTC packets are selected, the default config selects a value
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of 3 (i.e. psb_period=3) or the nearest lower value that is
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supported (0 is always supported). Otherwise the default is 0.
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If decoding is expected to be reliable and the buffer is large
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then a large PSB period can be used.
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Because a TSC packet is produced with PSB, the PSB period can
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also affect the granularity to timing information in the absence
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of MTC or CYC.
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mtc Produces MTC timing packets.
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MTC packets provide finer grain timestamp information than TSC
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packets. MTC packets record time using the hardware crystal
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clock (CTC) which is related to TSC packets using a TMA packet.
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Support for this feature is indicated by:
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/sys/bus/event_source/devices/intel_pt/caps/mtc
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which contains "1" if the feature is supported and
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"0" otherwise.
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The frequency of MTC packets can also be specified - see
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mtc_period below.
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mtc_period Specifies how frequently MTC packets are produced - see mtc
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above for how to determine if MTC packets are supported.
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Valid values are given by:
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/sys/bus/event_source/devices/intel_pt/caps/mtc_periods
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which contains a hexadecimal value, the bits of which represent
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valid values e.g. bit 2 set means value 2 is valid.
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The mtc_period value is converted to the MTC frequency as:
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CTC-frequency / (2 ^ value)
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e.g. value 3 means one eighth of CTC-frequency
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Where CTC is the hardware crystal clock, the frequency of which
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can be related to TSC via values provided in cpuid leaf 0x15.
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If an invalid value is entered, the error message
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will give a list of valid values e.g.
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$ perf record -e intel_pt/mtc_period=15/u uname
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Invalid mtc_period for intel_pt. Valid values are: 0,3,6,9
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The default value is 3 or the nearest lower value
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that is supported (0 is always supported).
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cyc Produces CYC timing packets.
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CYC packets provide even finer grain timestamp information than
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MTC and TSC packets. A CYC packet contains the number of CPU
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cycles since the last CYC packet. Unlike MTC and TSC packets,
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CYC packets are only sent when another packet is also sent.
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Support for this feature is indicated by:
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/sys/bus/event_source/devices/intel_pt/caps/psb_cyc
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which contains "1" if the feature is supported and
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"0" otherwise.
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The number of CYC packets produced can be reduced by specifying
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a threshold - see cyc_thresh below.
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cyc_thresh Specifies how frequently CYC packets are produced - see cyc
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above for how to determine if CYC packets are supported.
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Valid cyc_thresh values are given by:
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/sys/bus/event_source/devices/intel_pt/caps/cycle_thresholds
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which contains a hexadecimal value, the bits of which represent
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valid values e.g. bit 2 set means value 2 is valid.
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The cyc_thresh value represents the minimum number of CPU cycles
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that must have passed before a CYC packet can be sent. The
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number of CPU cycles is:
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2 ^ (value - 1)
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e.g. value 4 means 8 CPU cycles must pass before a CYC packet
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can be sent. Note a CYC packet is still only sent when another
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packet is sent, not at, e.g. every 8 CPU cycles.
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If an invalid value is entered, the error message
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will give a list of valid values e.g.
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$ perf record -e intel_pt/cyc,cyc_thresh=15/u uname
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Invalid cyc_thresh for intel_pt. Valid values are: 0-12
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CYC packets are not requested by default.
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pt Specifies pass-through which enables the 'branch' config term.
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The default config selects 'pt' if it is available, so a user will
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never need to specify this term.
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branch Enable branch tracing. Branch tracing is enabled by default so to
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disable branch tracing use 'branch=0'.
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The default config selects 'branch' if it is available.
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ptw Enable PTWRITE packets which are produced when a ptwrite instruction
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is executed.
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Support for this feature is indicated by:
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/sys/bus/event_source/devices/intel_pt/caps/ptwrite
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which contains "1" if the feature is supported and
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"0" otherwise.
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fup_on_ptw Enable a FUP packet to follow the PTWRITE packet. The FUP packet
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provides the address of the ptwrite instruction. In the absence of
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fup_on_ptw, the decoder will use the address of the previous branch
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if branch tracing is enabled, otherwise the address will be zero.
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Note that fup_on_ptw will work even when branch tracing is disabled.
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pwr_evt Enable power events. The power events provide information about
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changes to the CPU C-state.
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Support for this feature is indicated by:
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/sys/bus/event_source/devices/intel_pt/caps/power_event_trace
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which contains "1" if the feature is supported and
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"0" otherwise.
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new snapshot option
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-------------------
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The difference between full trace and snapshot from the kernel's perspective is
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that in full trace we don't overwrite trace data that the user hasn't collected
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yet (and indicated that by advancing aux_tail), whereas in snapshot mode we let
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the trace run and overwrite older data in the buffer so that whenever something
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interesting happens, we can stop it and grab a snapshot of what was going on
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around that interesting moment.
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To select snapshot mode a new option has been added:
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-S
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Optionally it can be followed by the snapshot size e.g.
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-S0x100000
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The default snapshot size is the auxtrace mmap size. If neither auxtrace mmap size
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nor snapshot size is specified, then the default is 4MiB for privileged users
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(or if /proc/sys/kernel/perf_event_paranoid < 0), 128KiB for unprivileged users.
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If an unprivileged user does not specify mmap pages, the mmap pages will be
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reduced as described in the 'new auxtrace mmap size option' section below.
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The snapshot size is displayed if the option -vv is used e.g.
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Intel PT snapshot size: %zu
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new auxtrace mmap size option
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---------------------------
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Intel PT buffer size is specified by an addition to the -m option e.g.
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-m,16
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selects a buffer size of 16 pages i.e. 64KiB.
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Note that the existing functionality of -m is unchanged. The auxtrace mmap size
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is specified by the optional addition of a comma and the value.
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The default auxtrace mmap size for Intel PT is 4MiB/page_size for privileged users
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(or if /proc/sys/kernel/perf_event_paranoid < 0), 128KiB for unprivileged users.
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If an unprivileged user does not specify mmap pages, the mmap pages will be
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reduced from the default 512KiB/page_size to 256KiB/page_size, otherwise the
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user is likely to get an error as they exceed their mlock limit (Max locked
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memory as shown in /proc/self/limits). Note that perf does not count the first
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512KiB (actually /proc/sys/kernel/perf_event_mlock_kb minus 1 page) per cpu
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against the mlock limit so an unprivileged user is allowed 512KiB per cpu plus
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their mlock limit (which defaults to 64KiB but is not multiplied by the number
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of cpus).
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In full-trace mode, powers of two are allowed for buffer size, with a minimum
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size of 2 pages. In snapshot mode, it is the same but the minimum size is
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1 page.
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The mmap size and auxtrace mmap size are displayed if the -vv option is used e.g.
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mmap length 528384
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auxtrace mmap length 4198400
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Intel PT modes of operation
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---------------------------
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Intel PT can be used in 2 modes:
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full-trace mode
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snapshot mode
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Full-trace mode traces continuously e.g.
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perf record -e intel_pt//u uname
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Snapshot mode captures the available data when a signal is sent e.g.
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perf record -v -e intel_pt//u -S ./loopy 1000000000 &
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[1] 11435
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kill -USR2 11435
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Recording AUX area tracing snapshot
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Note that the signal sent is SIGUSR2.
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Note that "Recording AUX area tracing snapshot" is displayed because the -v
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option is used.
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The 2 modes cannot be used together.
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Buffer handling
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---------------
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There may be buffer limitations (i.e. single ToPa entry) which means that actual
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buffer sizes are limited to powers of 2 up to 4MiB (MAX_ORDER). In order to
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provide other sizes, and in particular an arbitrarily large size, multiple
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buffers are logically concatenated. However an interrupt must be used to switch
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between buffers. That has two potential problems:
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a) the interrupt may not be handled in time so that the current buffer
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becomes full and some trace data is lost.
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b) the interrupts may slow the system and affect the performance
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results.
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If trace data is lost, the driver sets 'truncated' in the PERF_RECORD_AUX event
|
|
which the tools report as an error.
|
|
|
|
In full-trace mode, the driver waits for data to be copied out before allowing
|
|
the (logical) buffer to wrap-around. If data is not copied out quickly enough,
|
|
again 'truncated' is set in the PERF_RECORD_AUX event. If the driver has to
|
|
wait, the intel_pt event gets disabled. Because it is difficult to know when
|
|
that happens, perf tools always re-enable the intel_pt event after copying out
|
|
data.
|
|
|
|
|
|
Intel PT and build ids
|
|
----------------------
|
|
|
|
By default "perf record" post-processes the event stream to find all build ids
|
|
for executables for all addresses sampled. Deliberately, Intel PT is not
|
|
decoded for that purpose (it would take too long). Instead the build ids for
|
|
all executables encountered (due to mmap, comm or task events) are included
|
|
in the perf.data file.
|
|
|
|
To see buildids included in the perf.data file use the command:
|
|
|
|
perf buildid-list
|
|
|
|
If the perf.data file contains Intel PT data, that is the same as:
|
|
|
|
perf buildid-list --with-hits
|
|
|
|
|
|
Snapshot mode and event disabling
|
|
---------------------------------
|
|
|
|
In order to make a snapshot, the intel_pt event is disabled using an IOCTL,
|
|
namely PERF_EVENT_IOC_DISABLE. However doing that can also disable the
|
|
collection of side-band information. In order to prevent that, a dummy
|
|
software event has been introduced that permits tracking events (like mmaps) to
|
|
continue to be recorded while intel_pt is disabled. That is important to ensure
|
|
there is complete side-band information to allow the decoding of subsequent
|
|
snapshots.
|
|
|
|
A test has been created for that. To find the test:
|
|
|
|
perf test list
|
|
...
|
|
23: Test using a dummy software event to keep tracking
|
|
|
|
To run the test:
|
|
|
|
perf test 23
|
|
23: Test using a dummy software event to keep tracking : Ok
|
|
|
|
|
|
perf record modes (nothing new here)
|
|
------------------------------------
|
|
|
|
perf record essentially operates in one of three modes:
|
|
per thread
|
|
per cpu
|
|
workload only
|
|
|
|
"per thread" mode is selected by -t or by --per-thread (with -p or -u or just a
|
|
workload).
|
|
"per cpu" is selected by -C or -a.
|
|
"workload only" mode is selected by not using the other options but providing a
|
|
command to run (i.e. the workload).
|
|
|
|
In per-thread mode an exact list of threads is traced. There is no inheritance.
|
|
Each thread has its own event buffer.
|
|
|
|
In per-cpu mode all processes (or processes from the selected cgroup i.e. -G
|
|
option, or processes selected with -p or -u) are traced. Each cpu has its own
|
|
buffer. Inheritance is allowed.
|
|
|
|
In workload-only mode, the workload is traced but with per-cpu buffers.
|
|
Inheritance is allowed. Note that you can now trace a workload in per-thread
|
|
mode by using the --per-thread option.
|
|
|
|
|
|
Privileged vs non-privileged users
|
|
----------------------------------
|
|
|
|
Unless /proc/sys/kernel/perf_event_paranoid is set to -1, unprivileged users
|
|
have memory limits imposed upon them. That affects what buffer sizes they can
|
|
have as outlined above.
|
|
|
|
The v4.2 kernel introduced support for a context switch metadata event,
|
|
PERF_RECORD_SWITCH, which allows unprivileged users to see when their processes
|
|
are scheduled out and in, just not by whom, which is left for the
|
|
PERF_RECORD_SWITCH_CPU_WIDE, that is only accessible in system wide context,
|
|
which in turn requires CAP_SYS_ADMIN.
|
|
|
|
Please see the 45ac1403f564 ("perf: Add PERF_RECORD_SWITCH to indicate context
|
|
switches") commit, that introduces these metadata events for further info.
|
|
|
|
When working with kernels < v4.2, the following considerations must be taken,
|
|
as the sched:sched_switch tracepoints will be used to receive such information:
|
|
|
|
Unless /proc/sys/kernel/perf_event_paranoid is set to -1, unprivileged users are
|
|
not permitted to use tracepoints which means there is insufficient side-band
|
|
information to decode Intel PT in per-cpu mode, and potentially workload-only
|
|
mode too if the workload creates new processes.
|
|
|
|
Note also, that to use tracepoints, read-access to debugfs is required. So if
|
|
debugfs is not mounted or the user does not have read-access, it will again not
|
|
be possible to decode Intel PT in per-cpu mode.
|
|
|
|
|
|
sched_switch tracepoint
|
|
-----------------------
|
|
|
|
The sched_switch tracepoint is used to provide side-band data for Intel PT
|
|
decoding in kernels where the PERF_RECORD_SWITCH metadata event isn't
|
|
available.
|
|
|
|
The sched_switch events are automatically added. e.g. the second event shown
|
|
below:
|
|
|
|
$ perf record -vv -e intel_pt//u uname
|
|
------------------------------------------------------------
|
|
perf_event_attr:
|
|
type 6
|
|
size 112
|
|
config 0x400
|
|
{ sample_period, sample_freq } 1
|
|
sample_type IP|TID|TIME|CPU|IDENTIFIER
|
|
read_format ID
|
|
disabled 1
|
|
inherit 1
|
|
exclude_kernel 1
|
|
exclude_hv 1
|
|
enable_on_exec 1
|
|
sample_id_all 1
|
|
------------------------------------------------------------
|
|
sys_perf_event_open: pid 31104 cpu 0 group_fd -1 flags 0x8
|
|
sys_perf_event_open: pid 31104 cpu 1 group_fd -1 flags 0x8
|
|
sys_perf_event_open: pid 31104 cpu 2 group_fd -1 flags 0x8
|
|
sys_perf_event_open: pid 31104 cpu 3 group_fd -1 flags 0x8
|
|
------------------------------------------------------------
|
|
perf_event_attr:
|
|
type 2
|
|
size 112
|
|
config 0x108
|
|
{ sample_period, sample_freq } 1
|
|
sample_type IP|TID|TIME|CPU|PERIOD|RAW|IDENTIFIER
|
|
read_format ID
|
|
inherit 1
|
|
sample_id_all 1
|
|
exclude_guest 1
|
|
------------------------------------------------------------
|
|
sys_perf_event_open: pid -1 cpu 0 group_fd -1 flags 0x8
|
|
sys_perf_event_open: pid -1 cpu 1 group_fd -1 flags 0x8
|
|
sys_perf_event_open: pid -1 cpu 2 group_fd -1 flags 0x8
|
|
sys_perf_event_open: pid -1 cpu 3 group_fd -1 flags 0x8
|
|
------------------------------------------------------------
|
|
perf_event_attr:
|
|
type 1
|
|
size 112
|
|
config 0x9
|
|
{ sample_period, sample_freq } 1
|
|
sample_type IP|TID|TIME|IDENTIFIER
|
|
read_format ID
|
|
disabled 1
|
|
inherit 1
|
|
exclude_kernel 1
|
|
exclude_hv 1
|
|
mmap 1
|
|
comm 1
|
|
enable_on_exec 1
|
|
task 1
|
|
sample_id_all 1
|
|
mmap2 1
|
|
comm_exec 1
|
|
------------------------------------------------------------
|
|
sys_perf_event_open: pid 31104 cpu 0 group_fd -1 flags 0x8
|
|
sys_perf_event_open: pid 31104 cpu 1 group_fd -1 flags 0x8
|
|
sys_perf_event_open: pid 31104 cpu 2 group_fd -1 flags 0x8
|
|
sys_perf_event_open: pid 31104 cpu 3 group_fd -1 flags 0x8
|
|
mmap size 528384B
|
|
AUX area mmap length 4194304
|
|
perf event ring buffer mmapped per cpu
|
|
Synthesizing auxtrace information
|
|
Linux
|
|
[ perf record: Woken up 1 times to write data ]
|
|
[ perf record: Captured and wrote 0.042 MB perf.data ]
|
|
|
|
Note, the sched_switch event is only added if the user is permitted to use it
|
|
and only in per-cpu mode.
|
|
|
|
Note also, the sched_switch event is only added if TSC packets are requested.
|
|
That is because, in the absence of timing information, the sched_switch events
|
|
cannot be matched against the Intel PT trace.
|
|
|
|
|
|
perf script
|
|
===========
|
|
|
|
By default, perf script will decode trace data found in the perf.data file.
|
|
This can be further controlled by new option --itrace.
|
|
|
|
|
|
New --itrace option
|
|
-------------------
|
|
|
|
Having no option is the same as
|
|
|
|
--itrace
|
|
|
|
which, in turn, is the same as
|
|
|
|
--itrace=ibxwpe
|
|
|
|
The letters are:
|
|
|
|
i synthesize "instructions" events
|
|
b synthesize "branches" events
|
|
x synthesize "transactions" events
|
|
w synthesize "ptwrite" events
|
|
p synthesize "power" events
|
|
c synthesize branches events (calls only)
|
|
r synthesize branches events (returns only)
|
|
e synthesize tracing error events
|
|
d create a debug log
|
|
g synthesize a call chain (use with i or x)
|
|
l synthesize last branch entries (use with i or x)
|
|
s skip initial number of events
|
|
|
|
"Instructions" events look like they were recorded by "perf record -e
|
|
instructions".
|
|
|
|
"Branches" events look like they were recorded by "perf record -e branches". "c"
|
|
and "r" can be combined to get calls and returns.
|
|
|
|
"Transactions" events correspond to the start or end of transactions. The
|
|
'flags' field can be used in perf script to determine whether the event is a
|
|
tranasaction start, commit or abort.
|
|
|
|
Note that "instructions", "branches" and "transactions" events depend on code
|
|
flow packets which can be disabled by using the config term "branch=0". Refer
|
|
to the config terms section above.
|
|
|
|
"ptwrite" events record the payload of the ptwrite instruction and whether
|
|
"fup_on_ptw" was used. "ptwrite" events depend on PTWRITE packets which are
|
|
recorded only if the "ptw" config term was used. Refer to the config terms
|
|
section above. perf script "synth" field displays "ptwrite" information like
|
|
this: "ip: 0 payload: 0x123456789abcdef0" where "ip" is 1 if "fup_on_ptw" was
|
|
used.
|
|
|
|
"Power" events correspond to power event packets and CBR (core-to-bus ratio)
|
|
packets. While CBR packets are always recorded when tracing is enabled, power
|
|
event packets are recorded only if the "pwr_evt" config term was used. Refer to
|
|
the config terms section above. The power events record information about
|
|
C-state changes, whereas CBR is indicative of CPU frequency. perf script
|
|
"event,synth" fields display information like this:
|
|
cbr: cbr: 22 freq: 2189 MHz (200%)
|
|
mwait: hints: 0x60 extensions: 0x1
|
|
pwre: hw: 0 cstate: 2 sub-cstate: 0
|
|
exstop: ip: 1
|
|
pwrx: deepest cstate: 2 last cstate: 2 wake reason: 0x4
|
|
Where:
|
|
"cbr" includes the frequency and the percentage of maximum non-turbo
|
|
"mwait" shows mwait hints and extensions
|
|
"pwre" shows C-state transitions (to a C-state deeper than C0) and
|
|
whether initiated by hardware
|
|
"exstop" indicates execution stopped and whether the IP was recorded
|
|
exactly,
|
|
"pwrx" indicates return to C0
|
|
For more details refer to the Intel 64 and IA-32 Architectures Software
|
|
Developer Manuals.
|
|
|
|
Error events show where the decoder lost the trace. Error events
|
|
are quite important. Users must know if what they are seeing is a complete
|
|
picture or not.
|
|
|
|
The "d" option will cause the creation of a file "intel_pt.log" containing all
|
|
decoded packets and instructions. Note that this option slows down the decoder
|
|
and that the resulting file may be very large.
|
|
|
|
In addition, the period of the "instructions" event can be specified. e.g.
|
|
|
|
--itrace=i10us
|
|
|
|
sets the period to 10us i.e. one instruction sample is synthesized for each 10
|
|
microseconds of trace. Alternatives to "us" are "ms" (milliseconds),
|
|
"ns" (nanoseconds), "t" (TSC ticks) or "i" (instructions).
|
|
|
|
"ms", "us" and "ns" are converted to TSC ticks.
|
|
|
|
The timing information included with Intel PT does not give the time of every
|
|
instruction. Consequently, for the purpose of sampling, the decoder estimates
|
|
the time since the last timing packet based on 1 tick per instruction. The time
|
|
on the sample is *not* adjusted and reflects the last known value of TSC.
|
|
|
|
For Intel PT, the default period is 100us.
|
|
|
|
Setting it to a zero period means "as often as possible".
|
|
|
|
In the case of Intel PT that is the same as a period of 1 and a unit of
|
|
'instructions' (i.e. --itrace=i1i).
|
|
|
|
Also the call chain size (default 16, max. 1024) for instructions or
|
|
transactions events can be specified. e.g.
|
|
|
|
--itrace=ig32
|
|
--itrace=xg32
|
|
|
|
Also the number of last branch entries (default 64, max. 1024) for instructions or
|
|
transactions events can be specified. e.g.
|
|
|
|
--itrace=il10
|
|
--itrace=xl10
|
|
|
|
Note that last branch entries are cleared for each sample, so there is no overlap
|
|
from one sample to the next.
|
|
|
|
To disable trace decoding entirely, use the option --no-itrace.
|
|
|
|
It is also possible to skip events generated (instructions, branches, transactions)
|
|
at the beginning. This is useful to ignore initialization code.
|
|
|
|
--itrace=i0nss1000000
|
|
|
|
skips the first million instructions.
|
|
|
|
dump option
|
|
-----------
|
|
|
|
perf script has an option (-D) to "dump" the events i.e. display the binary
|
|
data.
|
|
|
|
When -D is used, Intel PT packets are displayed. The packet decoder does not
|
|
pay attention to PSB packets, but just decodes the bytes - so the packets seen
|
|
by the actual decoder may not be identical in places where the data is corrupt.
|
|
One example of that would be when the buffer-switching interrupt has been too
|
|
slow, and the buffer has been filled completely. In that case, the last packet
|
|
in the buffer might be truncated and immediately followed by a PSB as the trace
|
|
continues in the next buffer.
|
|
|
|
To disable the display of Intel PT packets, combine the -D option with
|
|
--no-itrace.
|
|
|
|
|
|
perf report
|
|
===========
|
|
|
|
By default, perf report will decode trace data found in the perf.data file.
|
|
This can be further controlled by new option --itrace exactly the same as
|
|
perf script, with the exception that the default is --itrace=igxe.
|
|
|
|
|
|
perf inject
|
|
===========
|
|
|
|
perf inject also accepts the --itrace option in which case tracing data is
|
|
removed and replaced with the synthesized events. e.g.
|
|
|
|
perf inject --itrace -i perf.data -o perf.data.new
|
|
|
|
Below is an example of using Intel PT with autofdo. It requires autofdo
|
|
(https://github.com/google/autofdo) and gcc version 5. The bubble
|
|
sort example is from the AutoFDO tutorial (https://gcc.gnu.org/wiki/AutoFDO/Tutorial)
|
|
amended to take the number of elements as a parameter.
|
|
|
|
$ gcc-5 -O3 sort.c -o sort_optimized
|
|
$ ./sort_optimized 30000
|
|
Bubble sorting array of 30000 elements
|
|
2254 ms
|
|
|
|
$ cat ~/.perfconfig
|
|
[intel-pt]
|
|
mispred-all = on
|
|
|
|
$ perf record -e intel_pt//u ./sort 3000
|
|
Bubble sorting array of 3000 elements
|
|
58 ms
|
|
[ perf record: Woken up 2 times to write data ]
|
|
[ perf record: Captured and wrote 3.939 MB perf.data ]
|
|
$ perf inject -i perf.data -o inj --itrace=i100usle --strip
|
|
$ ./create_gcov --binary=./sort --profile=inj --gcov=sort.gcov -gcov_version=1
|
|
$ gcc-5 -O3 -fauto-profile=sort.gcov sort.c -o sort_autofdo
|
|
$ ./sort_autofdo 30000
|
|
Bubble sorting array of 30000 elements
|
|
2155 ms
|
|
|
|
Note there is currently no advantage to using Intel PT instead of LBR, but
|
|
that may change in the future if greater use is made of the data.
|