692 строки
19 KiB
C
692 строки
19 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003, 04, 05 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2007 Maciej W. Rozycki
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* Copyright (C) 2008 Thiemo Seufer
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/proc_fs.h>
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#include <asm/bugs.h>
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#include <asm/cacheops.h>
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#include <asm/inst.h>
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#include <asm/io.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/prefetch.h>
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#include <asm/system.h>
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#include <asm/bootinfo.h>
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#include <asm/mipsregs.h>
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#include <asm/mmu_context.h>
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#include <asm/cpu.h>
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#include <asm/war.h>
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#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
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#include <asm/sibyte/sb1250.h>
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#include <asm/sibyte/sb1250_regs.h>
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#include <asm/sibyte/sb1250_dma.h>
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#endif
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#include <asm/uasm.h>
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/* Registers used in the assembled routines. */
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#define ZERO 0
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#define AT 2
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#define A0 4
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#define A1 5
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#define A2 6
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#define T0 8
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#define T1 9
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#define T2 10
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#define T3 11
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#define T9 25
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#define RA 31
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/* Handle labels (which must be positive integers). */
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enum label_id {
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label_clear_nopref = 1,
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label_clear_pref,
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label_copy_nopref,
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label_copy_pref_both,
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label_copy_pref_store,
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};
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UASM_L_LA(_clear_nopref)
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UASM_L_LA(_clear_pref)
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UASM_L_LA(_copy_nopref)
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UASM_L_LA(_copy_pref_both)
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UASM_L_LA(_copy_pref_store)
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/* We need one branch and therefore one relocation per target label. */
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static struct uasm_label __cpuinitdata labels[5];
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static struct uasm_reloc __cpuinitdata relocs[5];
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#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
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#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
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/*
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* Maximum sizes:
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*
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* R4000 128 bytes S-cache: 0x058 bytes
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* R4600 v1.7: 0x05c bytes
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* R4600 v2.0: 0x060 bytes
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* With prefetching, 16 word strides 0x120 bytes
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*/
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static u32 clear_page_array[0x120 / 4];
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#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
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void clear_page_cpu(void *page) __attribute__((alias("clear_page_array")));
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#else
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void clear_page(void *page) __attribute__((alias("clear_page_array")));
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#endif
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EXPORT_SYMBOL(clear_page);
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/*
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* Maximum sizes:
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*
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* R4000 128 bytes S-cache: 0x11c bytes
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* R4600 v1.7: 0x080 bytes
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* R4600 v2.0: 0x07c bytes
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* With prefetching, 16 word strides 0x540 bytes
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*/
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static u32 copy_page_array[0x540 / 4];
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#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
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void
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copy_page_cpu(void *to, void *from) __attribute__((alias("copy_page_array")));
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#else
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void copy_page(void *to, void *from) __attribute__((alias("copy_page_array")));
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#endif
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EXPORT_SYMBOL(copy_page);
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static int pref_bias_clear_store __cpuinitdata;
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static int pref_bias_copy_load __cpuinitdata;
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static int pref_bias_copy_store __cpuinitdata;
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static u32 pref_src_mode __cpuinitdata;
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static u32 pref_dst_mode __cpuinitdata;
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static int clear_word_size __cpuinitdata;
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static int copy_word_size __cpuinitdata;
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static int half_clear_loop_size __cpuinitdata;
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static int half_copy_loop_size __cpuinitdata;
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static int cache_line_size __cpuinitdata;
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#define cache_line_mask() (cache_line_size - 1)
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static inline void __cpuinit
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pg_addiu(u32 **buf, unsigned int reg1, unsigned int reg2, unsigned int off)
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{
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if (cpu_has_64bit_gp_regs && DADDI_WAR && r4k_daddiu_bug()) {
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if (off > 0x7fff) {
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uasm_i_lui(buf, T9, uasm_rel_hi(off));
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uasm_i_addiu(buf, T9, T9, uasm_rel_lo(off));
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} else
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uasm_i_addiu(buf, T9, ZERO, off);
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uasm_i_daddu(buf, reg1, reg2, T9);
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} else {
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if (off > 0x7fff) {
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uasm_i_lui(buf, T9, uasm_rel_hi(off));
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uasm_i_addiu(buf, T9, T9, uasm_rel_lo(off));
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UASM_i_ADDU(buf, reg1, reg2, T9);
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} else
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UASM_i_ADDIU(buf, reg1, reg2, off);
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}
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}
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static void __cpuinit set_prefetch_parameters(void)
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{
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if (cpu_has_64bit_gp_regs || cpu_has_64bit_zero_reg)
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clear_word_size = 8;
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else
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clear_word_size = 4;
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if (cpu_has_64bit_gp_regs)
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copy_word_size = 8;
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else
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copy_word_size = 4;
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/*
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* The pref's used here are using "streaming" hints, which cause the
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* copied data to be kicked out of the cache sooner. A page copy often
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* ends up copying a lot more data than is commonly used, so this seems
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* to make sense in terms of reducing cache pollution, but I've no real
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* performance data to back this up.
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*/
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if (cpu_has_prefetch) {
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/*
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* XXX: Most prefetch bias values in here are based on
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* guesswork.
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*/
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cache_line_size = cpu_dcache_line_size();
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switch (current_cpu_type()) {
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case CPU_R5500:
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case CPU_TX49XX:
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/* These processors only support the Pref_Load. */
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pref_bias_copy_load = 256;
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break;
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case CPU_RM9000:
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/*
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* As a workaround for erratum G105 which make the
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* PrepareForStore hint unusable we fall back to
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* StoreRetained on the RM9000. Once it is known which
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* versions of the RM9000 we'll be able to condition-
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* alize this.
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*/
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case CPU_R10000:
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case CPU_R12000:
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case CPU_R14000:
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/*
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* Those values have been experimentally tuned for an
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* Origin 200.
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*/
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pref_bias_clear_store = 512;
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pref_bias_copy_load = 256;
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pref_bias_copy_store = 256;
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pref_src_mode = Pref_LoadStreamed;
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pref_dst_mode = Pref_StoreStreamed;
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break;
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case CPU_SB1:
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case CPU_SB1A:
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pref_bias_clear_store = 128;
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pref_bias_copy_load = 128;
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pref_bias_copy_store = 128;
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/*
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* SB1 pass1 Pref_LoadStreamed/Pref_StoreStreamed
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* hints are broken.
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*/
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if (current_cpu_type() == CPU_SB1 &&
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(current_cpu_data.processor_id & 0xff) < 0x02) {
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pref_src_mode = Pref_Load;
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pref_dst_mode = Pref_Store;
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} else {
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pref_src_mode = Pref_LoadStreamed;
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pref_dst_mode = Pref_StoreStreamed;
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}
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break;
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default:
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pref_bias_clear_store = 128;
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pref_bias_copy_load = 256;
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pref_bias_copy_store = 128;
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pref_src_mode = Pref_LoadStreamed;
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pref_dst_mode = Pref_PrepareForStore;
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break;
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}
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} else {
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if (cpu_has_cache_cdex_s)
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cache_line_size = cpu_scache_line_size();
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else if (cpu_has_cache_cdex_p)
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cache_line_size = cpu_dcache_line_size();
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}
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/*
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* Too much unrolling will overflow the available space in
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* clear_space_array / copy_page_array.
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*/
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half_clear_loop_size = min(16 * clear_word_size,
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max(cache_line_size >> 1,
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4 * clear_word_size));
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half_copy_loop_size = min(16 * copy_word_size,
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max(cache_line_size >> 1,
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4 * copy_word_size));
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}
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static void __cpuinit build_clear_store(u32 **buf, int off)
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{
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if (cpu_has_64bit_gp_regs || cpu_has_64bit_zero_reg) {
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uasm_i_sd(buf, ZERO, off, A0);
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} else {
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uasm_i_sw(buf, ZERO, off, A0);
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}
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}
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static inline void __cpuinit build_clear_pref(u32 **buf, int off)
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{
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if (off & cache_line_mask())
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return;
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if (pref_bias_clear_store) {
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uasm_i_pref(buf, pref_dst_mode, pref_bias_clear_store + off,
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A0);
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} else if (cache_line_size == (half_clear_loop_size << 1)) {
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if (cpu_has_cache_cdex_s) {
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uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
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} else if (cpu_has_cache_cdex_p) {
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if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
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uasm_i_nop(buf);
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uasm_i_nop(buf);
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uasm_i_nop(buf);
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uasm_i_nop(buf);
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}
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if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
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uasm_i_lw(buf, ZERO, ZERO, AT);
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uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
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}
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}
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}
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void __cpuinit build_clear_page(void)
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{
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int off;
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u32 *buf = (u32 *)&clear_page_array;
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struct uasm_label *l = labels;
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struct uasm_reloc *r = relocs;
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int i;
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memset(labels, 0, sizeof(labels));
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memset(relocs, 0, sizeof(relocs));
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set_prefetch_parameters();
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/*
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* This algorithm makes the following assumptions:
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* - The prefetch bias is a multiple of 2 words.
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* - The prefetch bias is less than one page.
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*/
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BUG_ON(pref_bias_clear_store % (2 * clear_word_size));
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BUG_ON(PAGE_SIZE < pref_bias_clear_store);
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off = PAGE_SIZE - pref_bias_clear_store;
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if (off > 0xffff || !pref_bias_clear_store)
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pg_addiu(&buf, A2, A0, off);
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else
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uasm_i_ori(&buf, A2, A0, off);
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if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
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uasm_i_lui(&buf, AT, 0xa000);
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off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size)
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* cache_line_size : 0;
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while (off) {
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build_clear_pref(&buf, -off);
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off -= cache_line_size;
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}
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uasm_l_clear_pref(&l, buf);
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do {
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build_clear_pref(&buf, off);
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build_clear_store(&buf, off);
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off += clear_word_size;
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} while (off < half_clear_loop_size);
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pg_addiu(&buf, A0, A0, 2 * off);
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off = -off;
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do {
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build_clear_pref(&buf, off);
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if (off == -clear_word_size)
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uasm_il_bne(&buf, &r, A0, A2, label_clear_pref);
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build_clear_store(&buf, off);
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off += clear_word_size;
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} while (off < 0);
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if (pref_bias_clear_store) {
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pg_addiu(&buf, A2, A0, pref_bias_clear_store);
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uasm_l_clear_nopref(&l, buf);
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off = 0;
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do {
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build_clear_store(&buf, off);
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off += clear_word_size;
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} while (off < half_clear_loop_size);
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pg_addiu(&buf, A0, A0, 2 * off);
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off = -off;
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do {
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if (off == -clear_word_size)
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uasm_il_bne(&buf, &r, A0, A2,
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label_clear_nopref);
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build_clear_store(&buf, off);
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off += clear_word_size;
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} while (off < 0);
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}
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uasm_i_jr(&buf, RA);
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uasm_i_nop(&buf);
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BUG_ON(buf > clear_page_array + ARRAY_SIZE(clear_page_array));
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uasm_resolve_relocs(relocs, labels);
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pr_debug("Synthesized clear page handler (%u instructions).\n",
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(u32)(buf - clear_page_array));
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pr_debug("\t.set push\n");
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pr_debug("\t.set noreorder\n");
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for (i = 0; i < (buf - clear_page_array); i++)
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pr_debug("\t.word 0x%08x\n", clear_page_array[i]);
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pr_debug("\t.set pop\n");
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}
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static void __cpuinit build_copy_load(u32 **buf, int reg, int off)
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{
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if (cpu_has_64bit_gp_regs) {
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uasm_i_ld(buf, reg, off, A1);
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} else {
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uasm_i_lw(buf, reg, off, A1);
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}
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}
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static void __cpuinit build_copy_store(u32 **buf, int reg, int off)
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{
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if (cpu_has_64bit_gp_regs) {
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uasm_i_sd(buf, reg, off, A0);
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} else {
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uasm_i_sw(buf, reg, off, A0);
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}
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}
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static inline void build_copy_load_pref(u32 **buf, int off)
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{
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if (off & cache_line_mask())
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return;
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if (pref_bias_copy_load)
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uasm_i_pref(buf, pref_src_mode, pref_bias_copy_load + off, A1);
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}
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static inline void build_copy_store_pref(u32 **buf, int off)
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{
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if (off & cache_line_mask())
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return;
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if (pref_bias_copy_store) {
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uasm_i_pref(buf, pref_dst_mode, pref_bias_copy_store + off,
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A0);
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} else if (cache_line_size == (half_copy_loop_size << 1)) {
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if (cpu_has_cache_cdex_s) {
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uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
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} else if (cpu_has_cache_cdex_p) {
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if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
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uasm_i_nop(buf);
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uasm_i_nop(buf);
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uasm_i_nop(buf);
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uasm_i_nop(buf);
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}
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if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
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uasm_i_lw(buf, ZERO, ZERO, AT);
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uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
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}
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}
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}
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void __cpuinit build_copy_page(void)
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{
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int off;
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u32 *buf = (u32 *)©_page_array;
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struct uasm_label *l = labels;
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struct uasm_reloc *r = relocs;
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int i;
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memset(labels, 0, sizeof(labels));
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memset(relocs, 0, sizeof(relocs));
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set_prefetch_parameters();
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/*
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* This algorithm makes the following assumptions:
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* - All prefetch biases are multiples of 8 words.
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* - The prefetch biases are less than one page.
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* - The store prefetch bias isn't greater than the load
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* prefetch bias.
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*/
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BUG_ON(pref_bias_copy_load % (8 * copy_word_size));
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BUG_ON(pref_bias_copy_store % (8 * copy_word_size));
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BUG_ON(PAGE_SIZE < pref_bias_copy_load);
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BUG_ON(pref_bias_copy_store > pref_bias_copy_load);
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off = PAGE_SIZE - pref_bias_copy_load;
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if (off > 0xffff || !pref_bias_copy_load)
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pg_addiu(&buf, A2, A0, off);
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else
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uasm_i_ori(&buf, A2, A0, off);
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if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
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uasm_i_lui(&buf, AT, 0xa000);
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off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) *
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cache_line_size : 0;
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while (off) {
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build_copy_load_pref(&buf, -off);
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off -= cache_line_size;
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}
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off = cache_line_size ? min(8, pref_bias_copy_store / cache_line_size) *
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cache_line_size : 0;
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while (off) {
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build_copy_store_pref(&buf, -off);
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off -= cache_line_size;
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}
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uasm_l_copy_pref_both(&l, buf);
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do {
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build_copy_load_pref(&buf, off);
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build_copy_load(&buf, T0, off);
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build_copy_load_pref(&buf, off + copy_word_size);
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build_copy_load(&buf, T1, off + copy_word_size);
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build_copy_load_pref(&buf, off + 2 * copy_word_size);
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|
build_copy_load(&buf, T2, off + 2 * copy_word_size);
|
|
build_copy_load_pref(&buf, off + 3 * copy_word_size);
|
|
build_copy_load(&buf, T3, off + 3 * copy_word_size);
|
|
build_copy_store_pref(&buf, off);
|
|
build_copy_store(&buf, T0, off);
|
|
build_copy_store_pref(&buf, off + copy_word_size);
|
|
build_copy_store(&buf, T1, off + copy_word_size);
|
|
build_copy_store_pref(&buf, off + 2 * copy_word_size);
|
|
build_copy_store(&buf, T2, off + 2 * copy_word_size);
|
|
build_copy_store_pref(&buf, off + 3 * copy_word_size);
|
|
build_copy_store(&buf, T3, off + 3 * copy_word_size);
|
|
off += 4 * copy_word_size;
|
|
} while (off < half_copy_loop_size);
|
|
pg_addiu(&buf, A1, A1, 2 * off);
|
|
pg_addiu(&buf, A0, A0, 2 * off);
|
|
off = -off;
|
|
do {
|
|
build_copy_load_pref(&buf, off);
|
|
build_copy_load(&buf, T0, off);
|
|
build_copy_load_pref(&buf, off + copy_word_size);
|
|
build_copy_load(&buf, T1, off + copy_word_size);
|
|
build_copy_load_pref(&buf, off + 2 * copy_word_size);
|
|
build_copy_load(&buf, T2, off + 2 * copy_word_size);
|
|
build_copy_load_pref(&buf, off + 3 * copy_word_size);
|
|
build_copy_load(&buf, T3, off + 3 * copy_word_size);
|
|
build_copy_store_pref(&buf, off);
|
|
build_copy_store(&buf, T0, off);
|
|
build_copy_store_pref(&buf, off + copy_word_size);
|
|
build_copy_store(&buf, T1, off + copy_word_size);
|
|
build_copy_store_pref(&buf, off + 2 * copy_word_size);
|
|
build_copy_store(&buf, T2, off + 2 * copy_word_size);
|
|
build_copy_store_pref(&buf, off + 3 * copy_word_size);
|
|
if (off == -(4 * copy_word_size))
|
|
uasm_il_bne(&buf, &r, A2, A0, label_copy_pref_both);
|
|
build_copy_store(&buf, T3, off + 3 * copy_word_size);
|
|
off += 4 * copy_word_size;
|
|
} while (off < 0);
|
|
|
|
if (pref_bias_copy_load - pref_bias_copy_store) {
|
|
pg_addiu(&buf, A2, A0,
|
|
pref_bias_copy_load - pref_bias_copy_store);
|
|
uasm_l_copy_pref_store(&l, buf);
|
|
off = 0;
|
|
do {
|
|
build_copy_load(&buf, T0, off);
|
|
build_copy_load(&buf, T1, off + copy_word_size);
|
|
build_copy_load(&buf, T2, off + 2 * copy_word_size);
|
|
build_copy_load(&buf, T3, off + 3 * copy_word_size);
|
|
build_copy_store_pref(&buf, off);
|
|
build_copy_store(&buf, T0, off);
|
|
build_copy_store_pref(&buf, off + copy_word_size);
|
|
build_copy_store(&buf, T1, off + copy_word_size);
|
|
build_copy_store_pref(&buf, off + 2 * copy_word_size);
|
|
build_copy_store(&buf, T2, off + 2 * copy_word_size);
|
|
build_copy_store_pref(&buf, off + 3 * copy_word_size);
|
|
build_copy_store(&buf, T3, off + 3 * copy_word_size);
|
|
off += 4 * copy_word_size;
|
|
} while (off < half_copy_loop_size);
|
|
pg_addiu(&buf, A1, A1, 2 * off);
|
|
pg_addiu(&buf, A0, A0, 2 * off);
|
|
off = -off;
|
|
do {
|
|
build_copy_load(&buf, T0, off);
|
|
build_copy_load(&buf, T1, off + copy_word_size);
|
|
build_copy_load(&buf, T2, off + 2 * copy_word_size);
|
|
build_copy_load(&buf, T3, off + 3 * copy_word_size);
|
|
build_copy_store_pref(&buf, off);
|
|
build_copy_store(&buf, T0, off);
|
|
build_copy_store_pref(&buf, off + copy_word_size);
|
|
build_copy_store(&buf, T1, off + copy_word_size);
|
|
build_copy_store_pref(&buf, off + 2 * copy_word_size);
|
|
build_copy_store(&buf, T2, off + 2 * copy_word_size);
|
|
build_copy_store_pref(&buf, off + 3 * copy_word_size);
|
|
if (off == -(4 * copy_word_size))
|
|
uasm_il_bne(&buf, &r, A2, A0,
|
|
label_copy_pref_store);
|
|
build_copy_store(&buf, T3, off + 3 * copy_word_size);
|
|
off += 4 * copy_word_size;
|
|
} while (off < 0);
|
|
}
|
|
|
|
if (pref_bias_copy_store) {
|
|
pg_addiu(&buf, A2, A0, pref_bias_copy_store);
|
|
uasm_l_copy_nopref(&l, buf);
|
|
off = 0;
|
|
do {
|
|
build_copy_load(&buf, T0, off);
|
|
build_copy_load(&buf, T1, off + copy_word_size);
|
|
build_copy_load(&buf, T2, off + 2 * copy_word_size);
|
|
build_copy_load(&buf, T3, off + 3 * copy_word_size);
|
|
build_copy_store(&buf, T0, off);
|
|
build_copy_store(&buf, T1, off + copy_word_size);
|
|
build_copy_store(&buf, T2, off + 2 * copy_word_size);
|
|
build_copy_store(&buf, T3, off + 3 * copy_word_size);
|
|
off += 4 * copy_word_size;
|
|
} while (off < half_copy_loop_size);
|
|
pg_addiu(&buf, A1, A1, 2 * off);
|
|
pg_addiu(&buf, A0, A0, 2 * off);
|
|
off = -off;
|
|
do {
|
|
build_copy_load(&buf, T0, off);
|
|
build_copy_load(&buf, T1, off + copy_word_size);
|
|
build_copy_load(&buf, T2, off + 2 * copy_word_size);
|
|
build_copy_load(&buf, T3, off + 3 * copy_word_size);
|
|
build_copy_store(&buf, T0, off);
|
|
build_copy_store(&buf, T1, off + copy_word_size);
|
|
build_copy_store(&buf, T2, off + 2 * copy_word_size);
|
|
if (off == -(4 * copy_word_size))
|
|
uasm_il_bne(&buf, &r, A2, A0,
|
|
label_copy_nopref);
|
|
build_copy_store(&buf, T3, off + 3 * copy_word_size);
|
|
off += 4 * copy_word_size;
|
|
} while (off < 0);
|
|
}
|
|
|
|
uasm_i_jr(&buf, RA);
|
|
uasm_i_nop(&buf);
|
|
|
|
BUG_ON(buf > copy_page_array + ARRAY_SIZE(copy_page_array));
|
|
|
|
uasm_resolve_relocs(relocs, labels);
|
|
|
|
pr_debug("Synthesized copy page handler (%u instructions).\n",
|
|
(u32)(buf - copy_page_array));
|
|
|
|
pr_debug("\t.set push\n");
|
|
pr_debug("\t.set noreorder\n");
|
|
for (i = 0; i < (buf - copy_page_array); i++)
|
|
pr_debug("\t.word 0x%08x\n", copy_page_array[i]);
|
|
pr_debug("\t.set pop\n");
|
|
}
|
|
|
|
#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
|
|
|
|
/*
|
|
* Pad descriptors to cacheline, since each is exclusively owned by a
|
|
* particular CPU.
|
|
*/
|
|
struct dmadscr {
|
|
u64 dscr_a;
|
|
u64 dscr_b;
|
|
u64 pad_a;
|
|
u64 pad_b;
|
|
} ____cacheline_aligned_in_smp page_descr[DM_NUM_CHANNELS];
|
|
|
|
void sb1_dma_init(void)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < DM_NUM_CHANNELS; i++) {
|
|
const u64 base_val = CPHYSADDR((unsigned long)&page_descr[i]) |
|
|
V_DM_DSCR_BASE_RINGSZ(1);
|
|
void *base_reg = IOADDR(A_DM_REGISTER(i, R_DM_DSCR_BASE));
|
|
|
|
__raw_writeq(base_val, base_reg);
|
|
__raw_writeq(base_val | M_DM_DSCR_BASE_RESET, base_reg);
|
|
__raw_writeq(base_val | M_DM_DSCR_BASE_ENABL, base_reg);
|
|
}
|
|
}
|
|
|
|
void clear_page(void *page)
|
|
{
|
|
u64 to_phys = CPHYSADDR((unsigned long)page);
|
|
unsigned int cpu = smp_processor_id();
|
|
|
|
/* if the page is not in KSEG0, use old way */
|
|
if ((long)KSEGX((unsigned long)page) != (long)CKSEG0)
|
|
return clear_page_cpu(page);
|
|
|
|
page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_ZERO_MEM |
|
|
M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT;
|
|
page_descr[cpu].dscr_b = V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE);
|
|
__raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));
|
|
|
|
/*
|
|
* Don't really want to do it this way, but there's no
|
|
* reliable way to delay completion detection.
|
|
*/
|
|
while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)))
|
|
& M_DM_DSCR_BASE_INTERRUPT))
|
|
;
|
|
__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
|
|
}
|
|
|
|
void copy_page(void *to, void *from)
|
|
{
|
|
u64 from_phys = CPHYSADDR((unsigned long)from);
|
|
u64 to_phys = CPHYSADDR((unsigned long)to);
|
|
unsigned int cpu = smp_processor_id();
|
|
|
|
/* if any page is not in KSEG0, use old way */
|
|
if ((long)KSEGX((unsigned long)to) != (long)CKSEG0
|
|
|| (long)KSEGX((unsigned long)from) != (long)CKSEG0)
|
|
return copy_page_cpu(to, from);
|
|
|
|
page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_L2C_DEST |
|
|
M_DM_DSCRA_INTERRUPT;
|
|
page_descr[cpu].dscr_b = from_phys | V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE);
|
|
__raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));
|
|
|
|
/*
|
|
* Don't really want to do it this way, but there's no
|
|
* reliable way to delay completion detection.
|
|
*/
|
|
while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)))
|
|
& M_DM_DSCR_BASE_INTERRUPT))
|
|
;
|
|
__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
|
|
}
|
|
|
|
#endif /* CONFIG_SIBYTE_DMA_PAGEOPS */
|