287 строки
11 KiB
Plaintext
287 строки
11 KiB
Plaintext
MFP Configuration for PXA2xx/PXA3xx Processors
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Eric Miao <eric.miao@marvell.com>
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MFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and
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later PXA series processors. This document describes the existing MFP API,
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and how board/platform driver authors could make use of it.
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Basic Concept
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===============
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Unlike the GPIO alternate function settings on PXA25x and PXA27x, a new MFP
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mechanism is introduced from PXA3xx to completely move the pin-mux functions
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out of the GPIO controller. In addition to pin-mux configurations, the MFP
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also controls the low power state, driving strength, pull-up/down and event
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detection of each pin. Below is a diagram of internal connections between
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the MFP logic and the remaining SoC peripherals:
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+--------+
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| |--(GPIO19)--+
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| GPIO | |
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| |--(GPIO...) |
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+--------+ |
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| +---------+
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+--------+ +------>| |
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| PWM2 |--(PWM_OUT)-------->| MFP |
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+--------+ +------>| |-------> to external PAD
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| +---->| |
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+--------+ | | +-->| |
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| SSP2 |---(TXD)----+ | | +---------+
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+--------+ | |
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+--------+ | |
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| Keypad |--(MKOUT4)----+ |
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+--------+ |
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+--------+ |
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| UART2 |---(TXD)--------+
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+--------+
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NOTE: the external pad is named as MFP_PIN_GPIO19, it doesn't necessarily
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mean it's dedicated for GPIO19, only as a hint that internally this pin
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can be routed from GPIO19 of the GPIO controller.
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To better understand the change from PXA25x/PXA27x GPIO alternate function
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to this new MFP mechanism, here are several key points:
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1. GPIO controller on PXA3xx is now a dedicated controller, same as other
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internal controllers like PWM, SSP and UART, with 128 internal signals
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which can be routed to external through one or more MFPs (e.g. GPIO<0>
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can be routed through either MFP_PIN_GPIO0 as well as MFP_PIN_GPIO0_2,
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see arch/arm/mach-pxa/mfp-pxa300.h)
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2. Alternate function configuration is removed from this GPIO controller,
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the remaining functions are pure GPIO-specific, i.e.
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- GPIO signal level control
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- GPIO direction control
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- GPIO level change detection
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3. Low power state for each pin is now controlled by MFP, this means the
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PGSRx registers on PXA2xx are now useless on PXA3xx
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4. Wakeup detection is now controlled by MFP, PWER does not control the
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wakeup from GPIO(s) any more, depending on the sleeping state, ADxER
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(as defined in pxa3xx-regs.h) controls the wakeup from MFP
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NOTE: with such a clear separation of MFP and GPIO, by GPIO<xx> we normally
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mean it is a GPIO signal, and by MFP<xxx> or pin xxx, we mean a physical
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pad (or ball).
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MFP API Usage
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===============
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For board code writers, here are some guidelines:
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1. include ONE of the following header files in your <board>.c:
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- #include "mfp-pxa25x.h"
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- #include "mfp-pxa27x.h"
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- #include "mfp-pxa300.h"
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- #include "mfp-pxa320.h"
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- #include "mfp-pxa930.h"
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NOTE: only one file in your <board>.c, depending on the processors used,
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because pin configuration definitions may conflict in these file (i.e.
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same name, different meaning and settings on different processors). E.g.
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for zylonite platform, which support both PXA300/PXA310 and PXA320, two
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separate files are introduced: zylonite_pxa300.c and zylonite_pxa320.c
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(in addition to handle MFP configuration differences, they also handle
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the other differences between the two combinations).
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NOTE: PXA300 and PXA310 are almost identical in pin configurations (with
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PXA310 supporting some additional ones), thus the difference is actually
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covered in a single mfp-pxa300.h.
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2. prepare an array for the initial pin configurations, e.g.:
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static unsigned long mainstone_pin_config[] __initdata = {
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/* Chip Select */
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GPIO15_nCS_1,
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/* LCD - 16bpp Active TFT */
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GPIOxx_TFT_LCD_16BPP,
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GPIO16_PWM0_OUT, /* Backlight */
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/* MMC */
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GPIO32_MMC_CLK,
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GPIO112_MMC_CMD,
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GPIO92_MMC_DAT_0,
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GPIO109_MMC_DAT_1,
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GPIO110_MMC_DAT_2,
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GPIO111_MMC_DAT_3,
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...
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/* GPIO */
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GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
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};
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a) once the pin configurations are passed to pxa{2xx,3xx}_mfp_config(),
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and written to the actual registers, they are useless and may discard,
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adding '__initdata' will help save some additional bytes here.
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b) when there is only one possible pin configurations for a component,
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some simplified definitions can be used, e.g. GPIOxx_TFT_LCD_16BPP on
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PXA25x and PXA27x processors
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c) if by board design, a pin can be configured to wake up the system
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from low power state, it can be 'OR'ed with any of:
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WAKEUP_ON_EDGE_BOTH
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WAKEUP_ON_EDGE_RISE
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WAKEUP_ON_EDGE_FALL
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WAKEUP_ON_LEVEL_HIGH - specifically for enabling of keypad GPIOs,
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to indicate that this pin has the capability of wake-up the system,
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and on which edge(s). This, however, doesn't necessarily mean the
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pin _will_ wakeup the system, it will only when set_irq_wake() is
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invoked with the corresponding GPIO IRQ (GPIO_IRQ(xx) or gpio_to_irq())
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and eventually calls gpio_set_wake() for the actual register setting.
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d) although PXA3xx MFP supports edge detection on each pin, the
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internal logic will only wakeup the system when those specific bits
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in ADxER registers are set, which can be well mapped to the
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corresponding peripheral, thus set_irq_wake() can be called with
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the peripheral IRQ to enable the wakeup.
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MFP on PXA3xx
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===============
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Every external I/O pad on PXA3xx (excluding those for special purpose) has
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one MFP logic associated, and is controlled by one MFP register (MFPR).
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The MFPR has the following bit definitions (for PXA300/PXA310/PXA320):
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31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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+-------------------------+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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| RESERVED |PS|PU|PD| DRIVE |SS|SD|SO|EC|EF|ER|--| AF_SEL |
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+-------------------------+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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Bit 3: RESERVED
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Bit 4: EDGE_RISE_EN - enable detection of rising edge on this pin
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Bit 5: EDGE_FALL_EN - enable detection of falling edge on this pin
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Bit 6: EDGE_CLEAR - disable edge detection on this pin
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Bit 7: SLEEP_OE_N - enable outputs during low power modes
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Bit 8: SLEEP_DATA - output data on the pin during low power modes
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Bit 9: SLEEP_SEL - selection control for low power modes signals
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Bit 13: PULLDOWN_EN - enable the internal pull-down resistor on this pin
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Bit 14: PULLUP_EN - enable the internal pull-up resistor on this pin
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Bit 15: PULL_SEL - pull state controlled by selected alternate function
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(0) or by PULL{UP,DOWN}_EN bits (1)
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Bit 0 - 2: AF_SEL - alternate function selection, 8 possibilities, from 0-7
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Bit 10-12: DRIVE - drive strength and slew rate
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0b000 - fast 1mA
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0b001 - fast 2mA
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0b002 - fast 3mA
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0b003 - fast 4mA
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0b004 - slow 6mA
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0b005 - fast 6mA
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0b006 - slow 10mA
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0b007 - fast 10mA
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MFP Design for PXA2xx/PXA3xx
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==============================
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Due to the difference of pin-mux handling between PXA2xx and PXA3xx, a unified
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MFP API is introduced to cover both series of processors.
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The basic idea of this design is to introduce definitions for all possible pin
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configurations, these definitions are processor and platform independent, and
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the actual API invoked to convert these definitions into register settings and
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make them effective there-after.
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Files Involved
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--------------
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- arch/arm/mach-pxa/include/mach/mfp.h
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for
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1. Unified pin definitions - enum constants for all configurable pins
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2. processor-neutral bit definitions for a possible MFP configuration
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- arch/arm/mach-pxa/mfp-pxa3xx.h
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for PXA3xx specific MFPR register bit definitions and PXA3xx common pin
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configurations
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- arch/arm/mach-pxa/mfp-pxa2xx.h
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for PXA2xx specific definitions and PXA25x/PXA27x common pin configurations
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- arch/arm/mach-pxa/mfp-pxa25x.h
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arch/arm/mach-pxa/mfp-pxa27x.h
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arch/arm/mach-pxa/mfp-pxa300.h
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arch/arm/mach-pxa/mfp-pxa320.h
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arch/arm/mach-pxa/mfp-pxa930.h
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for processor specific definitions
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- arch/arm/mach-pxa/mfp-pxa3xx.c
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- arch/arm/mach-pxa/mfp-pxa2xx.c
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for implementation of the pin configuration to take effect for the actual
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processor.
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Pin Configuration
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-----------------
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The following comments are copied from mfp.h (see the actual source code
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for most updated info)
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/*
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* a possible MFP configuration is represented by a 32-bit integer
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*
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* bit 0.. 9 - MFP Pin Number (1024 Pins Maximum)
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* bit 10..12 - Alternate Function Selection
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* bit 13..15 - Drive Strength
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* bit 16..18 - Low Power Mode State
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* bit 19..20 - Low Power Mode Edge Detection
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* bit 21..22 - Run Mode Pull State
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*
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* to facilitate the definition, the following macros are provided
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*
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* MFP_CFG_DEFAULT - default MFP configuration value, with
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* alternate function = 0,
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* drive strength = fast 3mA (MFP_DS03X)
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* low power mode = default
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* edge detection = none
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*
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* MFP_CFG - default MFPR value with alternate function
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* MFP_CFG_DRV - default MFPR value with alternate function and
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* pin drive strength
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* MFP_CFG_LPM - default MFPR value with alternate function and
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* low power mode
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* MFP_CFG_X - default MFPR value with alternate function,
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* pin drive strength and low power mode
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*/
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Examples of pin configurations are:
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#define GPIO94_SSP3_RXD MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT)
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which reads GPIO94 can be configured as SSP3_RXD, with alternate function
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selection of 1, driving strength of 0b101, and a float state in low power
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modes.
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NOTE: this is the default setting of this pin being configured as SSP3_RXD
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which can be modified a bit in board code, though it is not recommended to
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do so, simply because this default setting is usually carefully encoded,
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and is supposed to work in most cases.
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Register Settings
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-----------------
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Register settings on PXA3xx for a pin configuration is actually very
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straight-forward, most bits can be converted directly into MFPR value
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in a easier way. Two sets of MFPR values are calculated: the run-time
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ones and the low power mode ones, to allow different settings.
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The conversion from a generic pin configuration to the actual register
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settings on PXA2xx is a bit complicated: many registers are involved,
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including GAFRx, GPDRx, PGSRx, PWER, PKWR, PFER and PRER. Please see
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mfp-pxa2xx.c for how the conversion is made.
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