157 строки
4.2 KiB
C
157 строки
4.2 KiB
C
/*
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* Broadcom specific AMBA
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* ChipCommon core driver
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*
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* Copyright 2005, Broadcom Corporation
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* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include "bcma_private.h"
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#include <linux/bcma/bcma.h>
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static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
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u32 mask, u32 value)
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{
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value &= mask;
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value |= bcma_cc_read32(cc, offset) & ~mask;
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bcma_cc_write32(cc, offset, value);
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return value;
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}
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void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
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{
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u32 leddc_on = 10;
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u32 leddc_off = 90;
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if (cc->setup_done)
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return;
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if (cc->core->id.rev >= 11)
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cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
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cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
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if (cc->core->id.rev >= 35)
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cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
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if (cc->core->id.rev >= 20) {
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bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
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bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
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}
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if (cc->capabilities & BCMA_CC_CAP_PMU)
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bcma_pmu_init(cc);
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if (cc->capabilities & BCMA_CC_CAP_PCTL)
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pr_err("Power control not implemented!\n");
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if (cc->core->id.rev >= 16) {
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if (cc->core->bus->sprom.leddc_on_time &&
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cc->core->bus->sprom.leddc_off_time) {
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leddc_on = cc->core->bus->sprom.leddc_on_time;
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leddc_off = cc->core->bus->sprom.leddc_off_time;
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}
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bcma_cc_write32(cc, BCMA_CC_GPIOTIMER,
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((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
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(leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
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}
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cc->setup_done = true;
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}
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/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
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void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
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{
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/* instant NMI */
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bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
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}
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void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
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{
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bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value);
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}
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u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask)
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{
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return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask;
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}
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u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask)
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{
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return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask;
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}
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u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
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{
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return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
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}
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u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
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{
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return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
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}
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u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
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{
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return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
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}
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EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
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u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
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{
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return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
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}
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u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
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{
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return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
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}
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#ifdef CONFIG_BCMA_DRIVER_MIPS
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void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
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{
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unsigned int irq;
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u32 baud_base;
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u32 i;
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unsigned int ccrev = cc->core->id.rev;
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struct bcma_serial_port *ports = cc->serial_ports;
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if (ccrev >= 11 && ccrev != 15) {
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/* Fixed ALP clock */
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baud_base = bcma_pmu_alp_clock(cc);
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if (ccrev >= 21) {
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/* Turn off UART clock before switching clocksource. */
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bcma_cc_write32(cc, BCMA_CC_CORECTL,
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bcma_cc_read32(cc, BCMA_CC_CORECTL)
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& ~BCMA_CC_CORECTL_UARTCLKEN);
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}
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/* Set the override bit so we don't divide it */
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bcma_cc_write32(cc, BCMA_CC_CORECTL,
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bcma_cc_read32(cc, BCMA_CC_CORECTL)
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| BCMA_CC_CORECTL_UARTCLK0);
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if (ccrev >= 21) {
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/* Re-enable the UART clock. */
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bcma_cc_write32(cc, BCMA_CC_CORECTL,
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bcma_cc_read32(cc, BCMA_CC_CORECTL)
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| BCMA_CC_CORECTL_UARTCLKEN);
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}
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} else {
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pr_err("serial not supported on this device ccrev: 0x%x\n",
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ccrev);
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return;
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}
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irq = bcma_core_mips_irq(cc->core);
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/* Determine the registers of the UARTs */
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cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
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for (i = 0; i < cc->nr_serial_ports; i++) {
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ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA +
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(i * 256);
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ports[i].irq = irq;
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ports[i].baud_base = baud_base;
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ports[i].reg_shift = 0;
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}
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}
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#endif /* CONFIG_BCMA_DRIVER_MIPS */
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