1037 строки
25 KiB
C
1037 строки
25 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* CAN bus driver for Holt HI3110 CAN Controller with SPI Interface
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*
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* Copyright(C) Timesys Corporation 2016
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*
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* Based on Microchip 251x CAN Controller (mcp251x) Linux kernel driver
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* Copyright 2009 Christian Pellegrin EVOL S.r.l.
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* Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
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* Copyright 2006 Arcom Control Systems Ltd.
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*
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* Based on CAN bus driver for the CCAN controller written by
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* - Sascha Hauer, Marc Kleine-Budde, Pengutronix
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* - Simon Kallweit, intefo AG
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* Copyright 2007
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*/
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#include <linux/can/core.h>
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#include <linux/can/dev.h>
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#include <linux/can/led.h>
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/freezer.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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#include <linux/spi/spi.h>
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#include <linux/uaccess.h>
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#define HI3110_MASTER_RESET 0x56
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#define HI3110_READ_CTRL0 0xD2
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#define HI3110_READ_CTRL1 0xD4
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#define HI3110_READ_STATF 0xE2
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#define HI3110_WRITE_CTRL0 0x14
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#define HI3110_WRITE_CTRL1 0x16
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#define HI3110_WRITE_INTE 0x1C
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#define HI3110_WRITE_BTR0 0x18
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#define HI3110_WRITE_BTR1 0x1A
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#define HI3110_READ_BTR0 0xD6
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#define HI3110_READ_BTR1 0xD8
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#define HI3110_READ_INTF 0xDE
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#define HI3110_READ_ERR 0xDC
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#define HI3110_READ_FIFO_WOTIME 0x48
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#define HI3110_WRITE_FIFO 0x12
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#define HI3110_READ_MESSTAT 0xDA
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#define HI3110_READ_REC 0xEA
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#define HI3110_READ_TEC 0xEC
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#define HI3110_CTRL0_MODE_MASK (7 << 5)
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#define HI3110_CTRL0_NORMAL_MODE (0 << 5)
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#define HI3110_CTRL0_LOOPBACK_MODE (1 << 5)
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#define HI3110_CTRL0_MONITOR_MODE (2 << 5)
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#define HI3110_CTRL0_SLEEP_MODE (3 << 5)
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#define HI3110_CTRL0_INIT_MODE (4 << 5)
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#define HI3110_CTRL1_TXEN BIT(7)
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#define HI3110_INT_RXTMP BIT(7)
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#define HI3110_INT_RXFIFO BIT(6)
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#define HI3110_INT_TXCPLT BIT(5)
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#define HI3110_INT_BUSERR BIT(4)
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#define HI3110_INT_MCHG BIT(3)
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#define HI3110_INT_WAKEUP BIT(2)
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#define HI3110_INT_F1MESS BIT(1)
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#define HI3110_INT_F0MESS BIT(0)
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#define HI3110_ERR_BUSOFF BIT(7)
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#define HI3110_ERR_TXERRP BIT(6)
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#define HI3110_ERR_RXERRP BIT(5)
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#define HI3110_ERR_BITERR BIT(4)
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#define HI3110_ERR_FRMERR BIT(3)
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#define HI3110_ERR_CRCERR BIT(2)
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#define HI3110_ERR_ACKERR BIT(1)
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#define HI3110_ERR_STUFERR BIT(0)
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#define HI3110_ERR_PROTOCOL_MASK (0x1F)
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#define HI3110_ERR_PASSIVE_MASK (0x60)
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#define HI3110_STAT_RXFMTY BIT(1)
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#define HI3110_STAT_BUSOFF BIT(2)
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#define HI3110_STAT_ERRP BIT(3)
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#define HI3110_STAT_ERRW BIT(4)
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#define HI3110_STAT_TXMTY BIT(7)
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#define HI3110_BTR0_SJW_SHIFT 6
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#define HI3110_BTR0_BRP_SHIFT 0
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#define HI3110_BTR1_SAMP_3PERBIT (1 << 7)
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#define HI3110_BTR1_SAMP_1PERBIT (0 << 7)
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#define HI3110_BTR1_TSEG2_SHIFT 4
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#define HI3110_BTR1_TSEG1_SHIFT 0
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#define HI3110_FIFO_WOTIME_TAG_OFF 0
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#define HI3110_FIFO_WOTIME_ID_OFF 1
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#define HI3110_FIFO_WOTIME_DLC_OFF 5
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#define HI3110_FIFO_WOTIME_DAT_OFF 6
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#define HI3110_FIFO_WOTIME_TAG_IDE BIT(7)
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#define HI3110_FIFO_WOTIME_ID_RTR BIT(0)
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#define HI3110_FIFO_TAG_OFF 0
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#define HI3110_FIFO_ID_OFF 1
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#define HI3110_FIFO_STD_DLC_OFF 3
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#define HI3110_FIFO_STD_DATA_OFF 4
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#define HI3110_FIFO_EXT_DLC_OFF 5
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#define HI3110_FIFO_EXT_DATA_OFF 6
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#define HI3110_CAN_MAX_DATA_LEN 8
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#define HI3110_RX_BUF_LEN 15
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#define HI3110_TX_STD_BUF_LEN 12
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#define HI3110_TX_EXT_BUF_LEN 14
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#define HI3110_CAN_FRAME_MAX_BITS 128
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#define HI3110_EFF_FLAGS 0x18 /* IDE + SRR */
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#define HI3110_TX_ECHO_SKB_MAX 1
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#define HI3110_OST_DELAY_MS (10)
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#define DEVICE_NAME "hi3110"
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static const struct can_bittiming_const hi3110_bittiming_const = {
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.name = DEVICE_NAME,
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.tseg1_min = 2,
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.tseg1_max = 16,
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.tseg2_min = 2,
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.tseg2_max = 8,
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.sjw_max = 4,
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.brp_min = 1,
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.brp_max = 64,
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.brp_inc = 1,
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};
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enum hi3110_model {
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CAN_HI3110_HI3110 = 0x3110,
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};
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struct hi3110_priv {
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struct can_priv can;
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struct net_device *net;
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struct spi_device *spi;
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enum hi3110_model model;
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struct mutex hi3110_lock; /* SPI device lock */
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u8 *spi_tx_buf;
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u8 *spi_rx_buf;
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struct sk_buff *tx_skb;
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int tx_len;
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struct workqueue_struct *wq;
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struct work_struct tx_work;
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struct work_struct restart_work;
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int force_quit;
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int after_suspend;
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#define HI3110_AFTER_SUSPEND_UP 1
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#define HI3110_AFTER_SUSPEND_DOWN 2
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#define HI3110_AFTER_SUSPEND_POWER 4
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#define HI3110_AFTER_SUSPEND_RESTART 8
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int restart_tx;
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struct regulator *power;
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struct regulator *transceiver;
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struct clk *clk;
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};
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static void hi3110_clean(struct net_device *net)
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{
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struct hi3110_priv *priv = netdev_priv(net);
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if (priv->tx_skb || priv->tx_len)
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net->stats.tx_errors++;
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dev_kfree_skb(priv->tx_skb);
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if (priv->tx_len)
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can_free_echo_skb(priv->net, 0);
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priv->tx_skb = NULL;
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priv->tx_len = 0;
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}
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/* Note about handling of error return of hi3110_spi_trans: accessing
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* registers via SPI is not really different conceptually than using
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* normal I/O assembler instructions, although it's much more
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* complicated from a practical POV. So it's not advisable to always
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* check the return value of this function. Imagine that every
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* read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
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* error();", it would be a great mess (well there are some situation
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* when exception handling C++ like could be useful after all). So we
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* just check that transfers are OK at the beginning of our
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* conversation with the chip and to avoid doing really nasty things
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* (like injecting bogus packets in the network stack).
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*/
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static int hi3110_spi_trans(struct spi_device *spi, int len)
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{
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struct hi3110_priv *priv = spi_get_drvdata(spi);
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struct spi_transfer t = {
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.tx_buf = priv->spi_tx_buf,
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.rx_buf = priv->spi_rx_buf,
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.len = len,
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.cs_change = 0,
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};
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struct spi_message m;
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int ret;
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spi_message_init(&m);
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spi_message_add_tail(&t, &m);
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ret = spi_sync(spi, &m);
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if (ret)
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dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
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return ret;
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}
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static u8 hi3110_cmd(struct spi_device *spi, u8 command)
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{
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struct hi3110_priv *priv = spi_get_drvdata(spi);
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priv->spi_tx_buf[0] = command;
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dev_dbg(&spi->dev, "hi3110_cmd: %02X\n", command);
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return hi3110_spi_trans(spi, 1);
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}
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static u8 hi3110_read(struct spi_device *spi, u8 command)
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{
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struct hi3110_priv *priv = spi_get_drvdata(spi);
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u8 val = 0;
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priv->spi_tx_buf[0] = command;
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hi3110_spi_trans(spi, 2);
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val = priv->spi_rx_buf[1];
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return val;
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}
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static void hi3110_write(struct spi_device *spi, u8 reg, u8 val)
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{
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struct hi3110_priv *priv = spi_get_drvdata(spi);
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priv->spi_tx_buf[0] = reg;
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priv->spi_tx_buf[1] = val;
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hi3110_spi_trans(spi, 2);
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}
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static void hi3110_hw_tx_frame(struct spi_device *spi, u8 *buf, int len)
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{
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struct hi3110_priv *priv = spi_get_drvdata(spi);
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priv->spi_tx_buf[0] = HI3110_WRITE_FIFO;
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memcpy(priv->spi_tx_buf + 1, buf, len);
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hi3110_spi_trans(spi, len + 1);
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}
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static void hi3110_hw_tx(struct spi_device *spi, struct can_frame *frame)
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{
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u8 buf[HI3110_TX_EXT_BUF_LEN];
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buf[HI3110_FIFO_TAG_OFF] = 0;
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if (frame->can_id & CAN_EFF_FLAG) {
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/* Extended frame */
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buf[HI3110_FIFO_ID_OFF] = (frame->can_id & CAN_EFF_MASK) >> 21;
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buf[HI3110_FIFO_ID_OFF + 1] =
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(((frame->can_id & CAN_EFF_MASK) >> 13) & 0xe0) |
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HI3110_EFF_FLAGS |
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(((frame->can_id & CAN_EFF_MASK) >> 15) & 0x07);
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buf[HI3110_FIFO_ID_OFF + 2] =
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(frame->can_id & CAN_EFF_MASK) >> 7;
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buf[HI3110_FIFO_ID_OFF + 3] =
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((frame->can_id & CAN_EFF_MASK) << 1) |
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((frame->can_id & CAN_RTR_FLAG) ? 1 : 0);
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buf[HI3110_FIFO_EXT_DLC_OFF] = frame->can_dlc;
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memcpy(buf + HI3110_FIFO_EXT_DATA_OFF,
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frame->data, frame->can_dlc);
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hi3110_hw_tx_frame(spi, buf, HI3110_TX_EXT_BUF_LEN -
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(HI3110_CAN_MAX_DATA_LEN - frame->can_dlc));
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} else {
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/* Standard frame */
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buf[HI3110_FIFO_ID_OFF] = (frame->can_id & CAN_SFF_MASK) >> 3;
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buf[HI3110_FIFO_ID_OFF + 1] =
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((frame->can_id & CAN_SFF_MASK) << 5) |
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((frame->can_id & CAN_RTR_FLAG) ? (1 << 4) : 0);
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buf[HI3110_FIFO_STD_DLC_OFF] = frame->can_dlc;
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memcpy(buf + HI3110_FIFO_STD_DATA_OFF,
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frame->data, frame->can_dlc);
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hi3110_hw_tx_frame(spi, buf, HI3110_TX_STD_BUF_LEN -
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(HI3110_CAN_MAX_DATA_LEN - frame->can_dlc));
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}
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}
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static void hi3110_hw_rx_frame(struct spi_device *spi, u8 *buf)
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{
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struct hi3110_priv *priv = spi_get_drvdata(spi);
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priv->spi_tx_buf[0] = HI3110_READ_FIFO_WOTIME;
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hi3110_spi_trans(spi, HI3110_RX_BUF_LEN);
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memcpy(buf, priv->spi_rx_buf + 1, HI3110_RX_BUF_LEN - 1);
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}
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static void hi3110_hw_rx(struct spi_device *spi)
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{
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struct hi3110_priv *priv = spi_get_drvdata(spi);
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struct sk_buff *skb;
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struct can_frame *frame;
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u8 buf[HI3110_RX_BUF_LEN - 1];
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skb = alloc_can_skb(priv->net, &frame);
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if (!skb) {
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priv->net->stats.rx_dropped++;
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return;
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}
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hi3110_hw_rx_frame(spi, buf);
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if (buf[HI3110_FIFO_WOTIME_TAG_OFF] & HI3110_FIFO_WOTIME_TAG_IDE) {
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/* IDE is recessive (1), indicating extended 29-bit frame */
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frame->can_id = CAN_EFF_FLAG;
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frame->can_id |=
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(buf[HI3110_FIFO_WOTIME_ID_OFF] << 21) |
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(((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0xE0) >> 5) << 18) |
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((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0x07) << 15) |
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(buf[HI3110_FIFO_WOTIME_ID_OFF + 2] << 7) |
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(buf[HI3110_FIFO_WOTIME_ID_OFF + 3] >> 1);
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} else {
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/* IDE is dominant (0), frame indicating standard 11-bit */
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frame->can_id =
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(buf[HI3110_FIFO_WOTIME_ID_OFF] << 3) |
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((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0xE0) >> 5);
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}
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/* Data length */
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frame->can_dlc = get_can_dlc(buf[HI3110_FIFO_WOTIME_DLC_OFF] & 0x0F);
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if (buf[HI3110_FIFO_WOTIME_ID_OFF + 3] & HI3110_FIFO_WOTIME_ID_RTR)
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frame->can_id |= CAN_RTR_FLAG;
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else
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memcpy(frame->data, buf + HI3110_FIFO_WOTIME_DAT_OFF,
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frame->can_dlc);
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priv->net->stats.rx_packets++;
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priv->net->stats.rx_bytes += frame->can_dlc;
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can_led_event(priv->net, CAN_LED_EVENT_RX);
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netif_rx_ni(skb);
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}
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static void hi3110_hw_sleep(struct spi_device *spi)
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{
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hi3110_write(spi, HI3110_WRITE_CTRL0, HI3110_CTRL0_SLEEP_MODE);
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}
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static netdev_tx_t hi3110_hard_start_xmit(struct sk_buff *skb,
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struct net_device *net)
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{
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struct hi3110_priv *priv = netdev_priv(net);
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struct spi_device *spi = priv->spi;
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if (priv->tx_skb || priv->tx_len) {
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dev_err(&spi->dev, "hard_xmit called while tx busy\n");
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return NETDEV_TX_BUSY;
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}
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if (can_dropped_invalid_skb(net, skb))
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return NETDEV_TX_OK;
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netif_stop_queue(net);
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priv->tx_skb = skb;
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queue_work(priv->wq, &priv->tx_work);
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return NETDEV_TX_OK;
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}
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static int hi3110_do_set_mode(struct net_device *net, enum can_mode mode)
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{
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struct hi3110_priv *priv = netdev_priv(net);
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switch (mode) {
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case CAN_MODE_START:
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hi3110_clean(net);
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/* We have to delay work since SPI I/O may sleep */
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priv->can.state = CAN_STATE_ERROR_ACTIVE;
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priv->restart_tx = 1;
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if (priv->can.restart_ms == 0)
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priv->after_suspend = HI3110_AFTER_SUSPEND_RESTART;
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queue_work(priv->wq, &priv->restart_work);
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break;
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default:
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return -EOPNOTSUPP;
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}
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return 0;
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}
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static int hi3110_get_berr_counter(const struct net_device *net,
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struct can_berr_counter *bec)
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{
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struct hi3110_priv *priv = netdev_priv(net);
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struct spi_device *spi = priv->spi;
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mutex_lock(&priv->hi3110_lock);
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bec->txerr = hi3110_read(spi, HI3110_READ_TEC);
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bec->rxerr = hi3110_read(spi, HI3110_READ_REC);
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mutex_unlock(&priv->hi3110_lock);
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return 0;
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}
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static int hi3110_set_normal_mode(struct spi_device *spi)
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{
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struct hi3110_priv *priv = spi_get_drvdata(spi);
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u8 reg = 0;
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hi3110_write(spi, HI3110_WRITE_INTE, HI3110_INT_BUSERR |
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HI3110_INT_RXFIFO | HI3110_INT_TXCPLT);
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/* Enable TX */
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hi3110_write(spi, HI3110_WRITE_CTRL1, HI3110_CTRL1_TXEN);
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if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
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reg = HI3110_CTRL0_LOOPBACK_MODE;
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else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
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reg = HI3110_CTRL0_MONITOR_MODE;
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else
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reg = HI3110_CTRL0_NORMAL_MODE;
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hi3110_write(spi, HI3110_WRITE_CTRL0, reg);
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/* Wait for the device to enter the mode */
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mdelay(HI3110_OST_DELAY_MS);
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reg = hi3110_read(spi, HI3110_READ_CTRL0);
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if ((reg & HI3110_CTRL0_MODE_MASK) != reg)
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return -EBUSY;
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priv->can.state = CAN_STATE_ERROR_ACTIVE;
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return 0;
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}
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static int hi3110_do_set_bittiming(struct net_device *net)
|
|
{
|
|
struct hi3110_priv *priv = netdev_priv(net);
|
|
struct can_bittiming *bt = &priv->can.bittiming;
|
|
struct spi_device *spi = priv->spi;
|
|
|
|
hi3110_write(spi, HI3110_WRITE_BTR0,
|
|
((bt->sjw - 1) << HI3110_BTR0_SJW_SHIFT) |
|
|
((bt->brp - 1) << HI3110_BTR0_BRP_SHIFT));
|
|
|
|
hi3110_write(spi, HI3110_WRITE_BTR1,
|
|
(priv->can.ctrlmode &
|
|
CAN_CTRLMODE_3_SAMPLES ?
|
|
HI3110_BTR1_SAMP_3PERBIT : HI3110_BTR1_SAMP_1PERBIT) |
|
|
((bt->phase_seg1 + bt->prop_seg - 1)
|
|
<< HI3110_BTR1_TSEG1_SHIFT) |
|
|
((bt->phase_seg2 - 1) << HI3110_BTR1_TSEG2_SHIFT));
|
|
|
|
dev_dbg(&spi->dev, "BT: 0x%02x 0x%02x\n",
|
|
hi3110_read(spi, HI3110_READ_BTR0),
|
|
hi3110_read(spi, HI3110_READ_BTR1));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int hi3110_setup(struct net_device *net)
|
|
{
|
|
hi3110_do_set_bittiming(net);
|
|
return 0;
|
|
}
|
|
|
|
static int hi3110_hw_reset(struct spi_device *spi)
|
|
{
|
|
u8 reg;
|
|
int ret;
|
|
|
|
/* Wait for oscillator startup timer after power up */
|
|
mdelay(HI3110_OST_DELAY_MS);
|
|
|
|
ret = hi3110_cmd(spi, HI3110_MASTER_RESET);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Wait for oscillator startup timer after reset */
|
|
mdelay(HI3110_OST_DELAY_MS);
|
|
|
|
reg = hi3110_read(spi, HI3110_READ_CTRL0);
|
|
if ((reg & HI3110_CTRL0_MODE_MASK) != HI3110_CTRL0_INIT_MODE)
|
|
return -ENODEV;
|
|
|
|
/* As per the datasheet it appears the error flags are
|
|
* not cleared on reset. Explicitly clear them by performing a read
|
|
*/
|
|
hi3110_read(spi, HI3110_READ_ERR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int hi3110_hw_probe(struct spi_device *spi)
|
|
{
|
|
u8 statf;
|
|
|
|
hi3110_hw_reset(spi);
|
|
|
|
/* Confirm correct operation by checking against reset values
|
|
* in datasheet
|
|
*/
|
|
statf = hi3110_read(spi, HI3110_READ_STATF);
|
|
|
|
dev_dbg(&spi->dev, "statf: %02X\n", statf);
|
|
|
|
if (statf != 0x82)
|
|
return -ENODEV;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int hi3110_power_enable(struct regulator *reg, int enable)
|
|
{
|
|
if (IS_ERR_OR_NULL(reg))
|
|
return 0;
|
|
|
|
if (enable)
|
|
return regulator_enable(reg);
|
|
else
|
|
return regulator_disable(reg);
|
|
}
|
|
|
|
static int hi3110_stop(struct net_device *net)
|
|
{
|
|
struct hi3110_priv *priv = netdev_priv(net);
|
|
struct spi_device *spi = priv->spi;
|
|
|
|
close_candev(net);
|
|
|
|
priv->force_quit = 1;
|
|
free_irq(spi->irq, priv);
|
|
destroy_workqueue(priv->wq);
|
|
priv->wq = NULL;
|
|
|
|
mutex_lock(&priv->hi3110_lock);
|
|
|
|
/* Disable transmit, interrupts and clear flags */
|
|
hi3110_write(spi, HI3110_WRITE_CTRL1, 0x0);
|
|
hi3110_write(spi, HI3110_WRITE_INTE, 0x0);
|
|
hi3110_read(spi, HI3110_READ_INTF);
|
|
|
|
hi3110_clean(net);
|
|
|
|
hi3110_hw_sleep(spi);
|
|
|
|
hi3110_power_enable(priv->transceiver, 0);
|
|
|
|
priv->can.state = CAN_STATE_STOPPED;
|
|
|
|
mutex_unlock(&priv->hi3110_lock);
|
|
|
|
can_led_event(net, CAN_LED_EVENT_STOP);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void hi3110_tx_work_handler(struct work_struct *ws)
|
|
{
|
|
struct hi3110_priv *priv = container_of(ws, struct hi3110_priv,
|
|
tx_work);
|
|
struct spi_device *spi = priv->spi;
|
|
struct net_device *net = priv->net;
|
|
struct can_frame *frame;
|
|
|
|
mutex_lock(&priv->hi3110_lock);
|
|
if (priv->tx_skb) {
|
|
if (priv->can.state == CAN_STATE_BUS_OFF) {
|
|
hi3110_clean(net);
|
|
} else {
|
|
frame = (struct can_frame *)priv->tx_skb->data;
|
|
hi3110_hw_tx(spi, frame);
|
|
priv->tx_len = 1 + frame->can_dlc;
|
|
can_put_echo_skb(priv->tx_skb, net, 0);
|
|
priv->tx_skb = NULL;
|
|
}
|
|
}
|
|
mutex_unlock(&priv->hi3110_lock);
|
|
}
|
|
|
|
static void hi3110_restart_work_handler(struct work_struct *ws)
|
|
{
|
|
struct hi3110_priv *priv = container_of(ws, struct hi3110_priv,
|
|
restart_work);
|
|
struct spi_device *spi = priv->spi;
|
|
struct net_device *net = priv->net;
|
|
|
|
mutex_lock(&priv->hi3110_lock);
|
|
if (priv->after_suspend) {
|
|
hi3110_hw_reset(spi);
|
|
hi3110_setup(net);
|
|
if (priv->after_suspend & HI3110_AFTER_SUSPEND_RESTART) {
|
|
hi3110_set_normal_mode(spi);
|
|
} else if (priv->after_suspend & HI3110_AFTER_SUSPEND_UP) {
|
|
netif_device_attach(net);
|
|
hi3110_clean(net);
|
|
hi3110_set_normal_mode(spi);
|
|
netif_wake_queue(net);
|
|
} else {
|
|
hi3110_hw_sleep(spi);
|
|
}
|
|
priv->after_suspend = 0;
|
|
priv->force_quit = 0;
|
|
}
|
|
|
|
if (priv->restart_tx) {
|
|
priv->restart_tx = 0;
|
|
hi3110_hw_reset(spi);
|
|
hi3110_setup(net);
|
|
hi3110_clean(net);
|
|
hi3110_set_normal_mode(spi);
|
|
netif_wake_queue(net);
|
|
}
|
|
mutex_unlock(&priv->hi3110_lock);
|
|
}
|
|
|
|
static irqreturn_t hi3110_can_ist(int irq, void *dev_id)
|
|
{
|
|
struct hi3110_priv *priv = dev_id;
|
|
struct spi_device *spi = priv->spi;
|
|
struct net_device *net = priv->net;
|
|
|
|
mutex_lock(&priv->hi3110_lock);
|
|
|
|
while (!priv->force_quit) {
|
|
enum can_state new_state;
|
|
u8 intf, eflag, statf;
|
|
|
|
while (!(HI3110_STAT_RXFMTY &
|
|
(statf = hi3110_read(spi, HI3110_READ_STATF)))) {
|
|
hi3110_hw_rx(spi);
|
|
}
|
|
|
|
intf = hi3110_read(spi, HI3110_READ_INTF);
|
|
eflag = hi3110_read(spi, HI3110_READ_ERR);
|
|
/* Update can state */
|
|
if (eflag & HI3110_ERR_BUSOFF)
|
|
new_state = CAN_STATE_BUS_OFF;
|
|
else if (eflag & HI3110_ERR_PASSIVE_MASK)
|
|
new_state = CAN_STATE_ERROR_PASSIVE;
|
|
else if (statf & HI3110_STAT_ERRW)
|
|
new_state = CAN_STATE_ERROR_WARNING;
|
|
else
|
|
new_state = CAN_STATE_ERROR_ACTIVE;
|
|
|
|
if (new_state != priv->can.state) {
|
|
struct can_frame *cf;
|
|
struct sk_buff *skb;
|
|
enum can_state rx_state, tx_state;
|
|
u8 rxerr, txerr;
|
|
|
|
skb = alloc_can_err_skb(net, &cf);
|
|
if (!skb)
|
|
break;
|
|
|
|
txerr = hi3110_read(spi, HI3110_READ_TEC);
|
|
rxerr = hi3110_read(spi, HI3110_READ_REC);
|
|
cf->data[6] = txerr;
|
|
cf->data[7] = rxerr;
|
|
tx_state = txerr >= rxerr ? new_state : 0;
|
|
rx_state = txerr <= rxerr ? new_state : 0;
|
|
can_change_state(net, cf, tx_state, rx_state);
|
|
netif_rx_ni(skb);
|
|
|
|
if (new_state == CAN_STATE_BUS_OFF) {
|
|
can_bus_off(net);
|
|
if (priv->can.restart_ms == 0) {
|
|
priv->force_quit = 1;
|
|
hi3110_hw_sleep(spi);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Update bus errors */
|
|
if ((intf & HI3110_INT_BUSERR) &&
|
|
(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
|
|
struct can_frame *cf;
|
|
struct sk_buff *skb;
|
|
|
|
/* Check for protocol errors */
|
|
if (eflag & HI3110_ERR_PROTOCOL_MASK) {
|
|
skb = alloc_can_err_skb(net, &cf);
|
|
if (!skb)
|
|
break;
|
|
|
|
cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
|
|
priv->can.can_stats.bus_error++;
|
|
priv->net->stats.rx_errors++;
|
|
if (eflag & HI3110_ERR_BITERR)
|
|
cf->data[2] |= CAN_ERR_PROT_BIT;
|
|
else if (eflag & HI3110_ERR_FRMERR)
|
|
cf->data[2] |= CAN_ERR_PROT_FORM;
|
|
else if (eflag & HI3110_ERR_STUFERR)
|
|
cf->data[2] |= CAN_ERR_PROT_STUFF;
|
|
else if (eflag & HI3110_ERR_CRCERR)
|
|
cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
|
|
else if (eflag & HI3110_ERR_ACKERR)
|
|
cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
|
|
|
|
cf->data[6] = hi3110_read(spi, HI3110_READ_TEC);
|
|
cf->data[7] = hi3110_read(spi, HI3110_READ_REC);
|
|
netdev_dbg(priv->net, "Bus Error\n");
|
|
netif_rx_ni(skb);
|
|
}
|
|
}
|
|
|
|
if (priv->tx_len && statf & HI3110_STAT_TXMTY) {
|
|
net->stats.tx_packets++;
|
|
net->stats.tx_bytes += priv->tx_len - 1;
|
|
can_led_event(net, CAN_LED_EVENT_TX);
|
|
if (priv->tx_len) {
|
|
can_get_echo_skb(net, 0);
|
|
priv->tx_len = 0;
|
|
}
|
|
netif_wake_queue(net);
|
|
}
|
|
|
|
if (intf == 0)
|
|
break;
|
|
}
|
|
mutex_unlock(&priv->hi3110_lock);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int hi3110_open(struct net_device *net)
|
|
{
|
|
struct hi3110_priv *priv = netdev_priv(net);
|
|
struct spi_device *spi = priv->spi;
|
|
unsigned long flags = IRQF_ONESHOT | IRQF_TRIGGER_HIGH;
|
|
int ret;
|
|
|
|
ret = open_candev(net);
|
|
if (ret)
|
|
return ret;
|
|
|
|
mutex_lock(&priv->hi3110_lock);
|
|
hi3110_power_enable(priv->transceiver, 1);
|
|
|
|
priv->force_quit = 0;
|
|
priv->tx_skb = NULL;
|
|
priv->tx_len = 0;
|
|
|
|
ret = request_threaded_irq(spi->irq, NULL, hi3110_can_ist,
|
|
flags, DEVICE_NAME, priv);
|
|
if (ret) {
|
|
dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
|
|
goto out_close;
|
|
}
|
|
|
|
priv->wq = alloc_workqueue("hi3110_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM,
|
|
0);
|
|
if (!priv->wq) {
|
|
ret = -ENOMEM;
|
|
goto out_free_irq;
|
|
}
|
|
INIT_WORK(&priv->tx_work, hi3110_tx_work_handler);
|
|
INIT_WORK(&priv->restart_work, hi3110_restart_work_handler);
|
|
|
|
ret = hi3110_hw_reset(spi);
|
|
if (ret)
|
|
goto out_free_wq;
|
|
|
|
ret = hi3110_setup(net);
|
|
if (ret)
|
|
goto out_free_wq;
|
|
|
|
ret = hi3110_set_normal_mode(spi);
|
|
if (ret)
|
|
goto out_free_wq;
|
|
|
|
can_led_event(net, CAN_LED_EVENT_OPEN);
|
|
netif_wake_queue(net);
|
|
mutex_unlock(&priv->hi3110_lock);
|
|
|
|
return 0;
|
|
|
|
out_free_wq:
|
|
destroy_workqueue(priv->wq);
|
|
out_free_irq:
|
|
free_irq(spi->irq, priv);
|
|
hi3110_hw_sleep(spi);
|
|
out_close:
|
|
hi3110_power_enable(priv->transceiver, 0);
|
|
close_candev(net);
|
|
mutex_unlock(&priv->hi3110_lock);
|
|
return ret;
|
|
}
|
|
|
|
static const struct net_device_ops hi3110_netdev_ops = {
|
|
.ndo_open = hi3110_open,
|
|
.ndo_stop = hi3110_stop,
|
|
.ndo_start_xmit = hi3110_hard_start_xmit,
|
|
};
|
|
|
|
static const struct of_device_id hi3110_of_match[] = {
|
|
{
|
|
.compatible = "holt,hi3110",
|
|
.data = (void *)CAN_HI3110_HI3110,
|
|
},
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, hi3110_of_match);
|
|
|
|
static const struct spi_device_id hi3110_id_table[] = {
|
|
{
|
|
.name = "hi3110",
|
|
.driver_data = (kernel_ulong_t)CAN_HI3110_HI3110,
|
|
},
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(spi, hi3110_id_table);
|
|
|
|
static int hi3110_can_probe(struct spi_device *spi)
|
|
{
|
|
const struct of_device_id *of_id = of_match_device(hi3110_of_match,
|
|
&spi->dev);
|
|
struct net_device *net;
|
|
struct hi3110_priv *priv;
|
|
struct clk *clk;
|
|
int freq, ret;
|
|
|
|
clk = devm_clk_get(&spi->dev, NULL);
|
|
if (IS_ERR(clk)) {
|
|
dev_err(&spi->dev, "no CAN clock source defined\n");
|
|
return PTR_ERR(clk);
|
|
}
|
|
freq = clk_get_rate(clk);
|
|
|
|
/* Sanity check */
|
|
if (freq > 40000000)
|
|
return -ERANGE;
|
|
|
|
/* Allocate can/net device */
|
|
net = alloc_candev(sizeof(struct hi3110_priv), HI3110_TX_ECHO_SKB_MAX);
|
|
if (!net)
|
|
return -ENOMEM;
|
|
|
|
if (!IS_ERR(clk)) {
|
|
ret = clk_prepare_enable(clk);
|
|
if (ret)
|
|
goto out_free;
|
|
}
|
|
|
|
net->netdev_ops = &hi3110_netdev_ops;
|
|
net->flags |= IFF_ECHO;
|
|
|
|
priv = netdev_priv(net);
|
|
priv->can.bittiming_const = &hi3110_bittiming_const;
|
|
priv->can.do_set_mode = hi3110_do_set_mode;
|
|
priv->can.do_get_berr_counter = hi3110_get_berr_counter;
|
|
priv->can.clock.freq = freq / 2;
|
|
priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
|
|
CAN_CTRLMODE_LOOPBACK |
|
|
CAN_CTRLMODE_LISTENONLY |
|
|
CAN_CTRLMODE_BERR_REPORTING;
|
|
|
|
if (of_id)
|
|
priv->model = (enum hi3110_model)of_id->data;
|
|
else
|
|
priv->model = spi_get_device_id(spi)->driver_data;
|
|
priv->net = net;
|
|
priv->clk = clk;
|
|
|
|
spi_set_drvdata(spi, priv);
|
|
|
|
/* Configure the SPI bus */
|
|
spi->bits_per_word = 8;
|
|
ret = spi_setup(spi);
|
|
if (ret)
|
|
goto out_clk;
|
|
|
|
priv->power = devm_regulator_get_optional(&spi->dev, "vdd");
|
|
priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
|
|
if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
|
|
(PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
|
|
ret = -EPROBE_DEFER;
|
|
goto out_clk;
|
|
}
|
|
|
|
ret = hi3110_power_enable(priv->power, 1);
|
|
if (ret)
|
|
goto out_clk;
|
|
|
|
priv->spi = spi;
|
|
mutex_init(&priv->hi3110_lock);
|
|
|
|
priv->spi_tx_buf = devm_kzalloc(&spi->dev, HI3110_RX_BUF_LEN,
|
|
GFP_KERNEL);
|
|
if (!priv->spi_tx_buf) {
|
|
ret = -ENOMEM;
|
|
goto error_probe;
|
|
}
|
|
priv->spi_rx_buf = devm_kzalloc(&spi->dev, HI3110_RX_BUF_LEN,
|
|
GFP_KERNEL);
|
|
|
|
if (!priv->spi_rx_buf) {
|
|
ret = -ENOMEM;
|
|
goto error_probe;
|
|
}
|
|
|
|
SET_NETDEV_DEV(net, &spi->dev);
|
|
|
|
ret = hi3110_hw_probe(spi);
|
|
if (ret) {
|
|
if (ret == -ENODEV)
|
|
dev_err(&spi->dev, "Cannot initialize %x. Wrong wiring?\n",
|
|
priv->model);
|
|
goto error_probe;
|
|
}
|
|
hi3110_hw_sleep(spi);
|
|
|
|
ret = register_candev(net);
|
|
if (ret)
|
|
goto error_probe;
|
|
|
|
devm_can_led_init(net);
|
|
netdev_info(net, "%x successfully initialized.\n", priv->model);
|
|
|
|
return 0;
|
|
|
|
error_probe:
|
|
hi3110_power_enable(priv->power, 0);
|
|
|
|
out_clk:
|
|
if (!IS_ERR(clk))
|
|
clk_disable_unprepare(clk);
|
|
|
|
out_free:
|
|
free_candev(net);
|
|
|
|
dev_err(&spi->dev, "Probe failed, err=%d\n", -ret);
|
|
return ret;
|
|
}
|
|
|
|
static int hi3110_can_remove(struct spi_device *spi)
|
|
{
|
|
struct hi3110_priv *priv = spi_get_drvdata(spi);
|
|
struct net_device *net = priv->net;
|
|
|
|
unregister_candev(net);
|
|
|
|
hi3110_power_enable(priv->power, 0);
|
|
|
|
if (!IS_ERR(priv->clk))
|
|
clk_disable_unprepare(priv->clk);
|
|
|
|
free_candev(net);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused hi3110_can_suspend(struct device *dev)
|
|
{
|
|
struct spi_device *spi = to_spi_device(dev);
|
|
struct hi3110_priv *priv = spi_get_drvdata(spi);
|
|
struct net_device *net = priv->net;
|
|
|
|
priv->force_quit = 1;
|
|
disable_irq(spi->irq);
|
|
|
|
/* Note: at this point neither IST nor workqueues are running.
|
|
* open/stop cannot be called anyway so locking is not needed
|
|
*/
|
|
if (netif_running(net)) {
|
|
netif_device_detach(net);
|
|
|
|
hi3110_hw_sleep(spi);
|
|
hi3110_power_enable(priv->transceiver, 0);
|
|
priv->after_suspend = HI3110_AFTER_SUSPEND_UP;
|
|
} else {
|
|
priv->after_suspend = HI3110_AFTER_SUSPEND_DOWN;
|
|
}
|
|
|
|
if (!IS_ERR_OR_NULL(priv->power)) {
|
|
regulator_disable(priv->power);
|
|
priv->after_suspend |= HI3110_AFTER_SUSPEND_POWER;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused hi3110_can_resume(struct device *dev)
|
|
{
|
|
struct spi_device *spi = to_spi_device(dev);
|
|
struct hi3110_priv *priv = spi_get_drvdata(spi);
|
|
|
|
if (priv->after_suspend & HI3110_AFTER_SUSPEND_POWER)
|
|
hi3110_power_enable(priv->power, 1);
|
|
|
|
if (priv->after_suspend & HI3110_AFTER_SUSPEND_UP) {
|
|
hi3110_power_enable(priv->transceiver, 1);
|
|
queue_work(priv->wq, &priv->restart_work);
|
|
} else {
|
|
priv->after_suspend = 0;
|
|
}
|
|
|
|
priv->force_quit = 0;
|
|
enable_irq(spi->irq);
|
|
return 0;
|
|
}
|
|
|
|
static SIMPLE_DEV_PM_OPS(hi3110_can_pm_ops, hi3110_can_suspend, hi3110_can_resume);
|
|
|
|
static struct spi_driver hi3110_can_driver = {
|
|
.driver = {
|
|
.name = DEVICE_NAME,
|
|
.of_match_table = hi3110_of_match,
|
|
.pm = &hi3110_can_pm_ops,
|
|
},
|
|
.id_table = hi3110_id_table,
|
|
.probe = hi3110_can_probe,
|
|
.remove = hi3110_can_remove,
|
|
};
|
|
|
|
module_spi_driver(hi3110_can_driver);
|
|
|
|
MODULE_AUTHOR("Akshay Bhat <akshay.bhat@timesys.com>");
|
|
MODULE_AUTHOR("Casey Fitzpatrick <casey.fitzpatrick@timesys.com>");
|
|
MODULE_DESCRIPTION("Holt HI-3110 CAN driver");
|
|
MODULE_LICENSE("GPL v2");
|