57e3cebd02
In order to reduce the impact of the VPT parsing happening on the GIC, we can split the vcpu reseidency in two phases: - programming GICR_VPENDBASER: this still happens in vcpu_load() - checking for the VPT parsing to be complete: this can happen on vcpu entry (in kvm_vgic_flush_hwstate()) This allows the GIC and the CPU to work in parallel, rewmoving some of the entry overhead. Suggested-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Shenming Lu <lushenming@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20201128141857.983-3-lushenming@huawei.com |
||
|---|---|---|
| .. | ||
| arm-gic-common.h | ||
| arm-gic-v3.h | ||
| arm-gic-v4.h | ||
| arm-gic.h | ||
| arm-vic.h | ||
| chained_irq.h | ||
| irq-bcm2836.h | ||
| irq-davinci-aintc.h | ||
| irq-davinci-cp-intc.h | ||
| irq-ixp4xx.h | ||
| irq-madera.h | ||
| irq-omap-intc.h | ||
| irq-partition-percpu.h | ||
| irq-sa11x0.h | ||
| mmp.h | ||
| mxs.h | ||
| versatile-fpga.h | ||
| xtensa-mx.h | ||
| xtensa-pic.h | ||