721 строка
19 KiB
C
721 строка
19 KiB
C
/*
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* Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
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* Copyright(c) 2006 Chris Snook <csnook@redhat.com>
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* Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
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*
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* Derived from Intel e1000 driver
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* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/if_vlan.h>
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#include <linux/etherdevice.h>
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#include <linux/crc32.h>
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#include <asm/byteorder.h>
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#include "atl1.h"
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/*
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* Reset the transmit and receive units; mask and clear all interrupts.
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* hw - Struct containing variables accessed by shared code
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* return : ATL1_SUCCESS or idle status (if error)
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*/
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s32 atl1_reset_hw(struct atl1_hw *hw)
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{
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struct pci_dev *pdev = hw->back->pdev;
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u32 icr;
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int i;
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/*
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* Clear Interrupt mask to stop board from generating
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* interrupts & Clear any pending interrupt events
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*/
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/*
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* iowrite32(0, hw->hw_addr + REG_IMR);
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* iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
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*/
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/*
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* Issue Soft Reset to the MAC. This will reset the chip's
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* transmit, receive, DMA. It will not effect
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* the current PCI configuration. The global reset bit is self-
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* clearing, and should clear within a microsecond.
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*/
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iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
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ioread32(hw->hw_addr + REG_MASTER_CTRL);
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iowrite16(1, hw->hw_addr + REG_GPHY_ENABLE);
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ioread16(hw->hw_addr + REG_GPHY_ENABLE);
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msleep(1); /* delay about 1ms */
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/* Wait at least 10ms for All module to be Idle */
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for (i = 0; i < 10; i++) {
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icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
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if (!icr)
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break;
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msleep(1); /* delay 1 ms */
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cpu_relax(); /* FIXME: is this still the right way to do this? */
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}
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if (icr) {
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dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr);
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return icr;
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}
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return ATL1_SUCCESS;
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}
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/* function about EEPROM
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*
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* check_eeprom_exist
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* return 0 if eeprom exist
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*/
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static int atl1_check_eeprom_exist(struct atl1_hw *hw)
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{
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u32 value;
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value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
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if (value & SPI_FLASH_CTRL_EN_VPD) {
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value &= ~SPI_FLASH_CTRL_EN_VPD;
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iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
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}
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value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
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return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
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}
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static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
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{
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int i;
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u32 control;
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if (offset & 3)
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return false; /* address do not align */
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iowrite32(0, hw->hw_addr + REG_VPD_DATA);
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control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
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iowrite32(control, hw->hw_addr + REG_VPD_CAP);
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ioread32(hw->hw_addr + REG_VPD_CAP);
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for (i = 0; i < 10; i++) {
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msleep(2);
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control = ioread32(hw->hw_addr + REG_VPD_CAP);
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if (control & VPD_CAP_VPD_FLAG)
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break;
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}
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if (control & VPD_CAP_VPD_FLAG) {
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*p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
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return true;
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}
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return false; /* timeout */
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}
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/*
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* Reads the value from a PHY register
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* hw - Struct containing variables accessed by shared code
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* reg_addr - address of the PHY register to read
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*/
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s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
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{
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u32 val;
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int i;
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val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
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MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
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MDIO_CLK_SEL_SHIFT;
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iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
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ioread32(hw->hw_addr + REG_MDIO_CTRL);
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for (i = 0; i < MDIO_WAIT_TIMES; i++) {
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udelay(2);
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val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
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if (!(val & (MDIO_START | MDIO_BUSY)))
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break;
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}
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if (!(val & (MDIO_START | MDIO_BUSY))) {
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*phy_data = (u16) val;
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return ATL1_SUCCESS;
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}
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return ATL1_ERR_PHY;
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}
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#define CUSTOM_SPI_CS_SETUP 2
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#define CUSTOM_SPI_CLK_HI 2
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#define CUSTOM_SPI_CLK_LO 2
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#define CUSTOM_SPI_CS_HOLD 2
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#define CUSTOM_SPI_CS_HI 3
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static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
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{
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int i;
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u32 value;
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iowrite32(0, hw->hw_addr + REG_SPI_DATA);
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iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
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value = SPI_FLASH_CTRL_WAIT_READY |
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(CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
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SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
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SPI_FLASH_CTRL_CLK_HI_MASK) <<
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SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
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SPI_FLASH_CTRL_CLK_LO_MASK) <<
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SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
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SPI_FLASH_CTRL_CS_HOLD_MASK) <<
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SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
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SPI_FLASH_CTRL_CS_HI_MASK) <<
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SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
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SPI_FLASH_CTRL_INS_SHIFT;
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iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
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value |= SPI_FLASH_CTRL_START;
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iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
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ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
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for (i = 0; i < 10; i++) {
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msleep(1); /* 1ms */
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value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
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if (!(value & SPI_FLASH_CTRL_START))
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break;
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}
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if (value & SPI_FLASH_CTRL_START)
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return false;
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*buf = ioread32(hw->hw_addr + REG_SPI_DATA);
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return true;
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}
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/*
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* get_permanent_address
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* return 0 if get valid mac address,
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*/
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static int atl1_get_permanent_address(struct atl1_hw *hw)
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{
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u32 addr[2];
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u32 i, control;
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u16 reg;
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u8 eth_addr[ETH_ALEN];
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bool key_valid;
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if (is_valid_ether_addr(hw->perm_mac_addr))
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return 0;
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/* init */
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addr[0] = addr[1] = 0;
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if (!atl1_check_eeprom_exist(hw)) { /* eeprom exist */
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reg = 0;
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key_valid = false;
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/* Read out all EEPROM content */
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i = 0;
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while (1) {
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if (atl1_read_eeprom(hw, i + 0x100, &control)) {
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if (key_valid) {
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if (reg == REG_MAC_STA_ADDR)
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addr[0] = control;
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else if (reg == (REG_MAC_STA_ADDR + 4))
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addr[1] = control;
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key_valid = false;
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} else if ((control & 0xff) == 0x5A) {
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key_valid = true;
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reg = (u16) (control >> 16);
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} else
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break; /* assume data end while encount an invalid KEYWORD */
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} else
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break; /* read error */
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i += 4;
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}
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*(u32 *) ð_addr[2] = swab32(addr[0]);
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*(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]);
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if (is_valid_ether_addr(eth_addr)) {
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memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
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return 0;
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}
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return 1;
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}
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/* see if SPI FLAGS exist ? */
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addr[0] = addr[1] = 0;
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reg = 0;
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key_valid = false;
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i = 0;
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while (1) {
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if (atl1_spi_read(hw, i + 0x1f000, &control)) {
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if (key_valid) {
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if (reg == REG_MAC_STA_ADDR)
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addr[0] = control;
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else if (reg == (REG_MAC_STA_ADDR + 4))
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addr[1] = control;
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key_valid = false;
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} else if ((control & 0xff) == 0x5A) {
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key_valid = true;
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reg = (u16) (control >> 16);
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} else
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break; /* data end */
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} else
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break; /* read error */
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i += 4;
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}
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*(u32 *) ð_addr[2] = swab32(addr[0]);
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*(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]);
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if (is_valid_ether_addr(eth_addr)) {
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memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
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return 0;
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}
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/*
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* On some motherboards, the MAC address is written by the
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* BIOS directly to the MAC register during POST, and is
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* not stored in eeprom. If all else thus far has failed
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* to fetch the permanent MAC address, try reading it directly.
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*/
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addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
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addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
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*(u32 *) ð_addr[2] = swab32(addr[0]);
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*(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]);
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if (is_valid_ether_addr(eth_addr)) {
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memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
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return 0;
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}
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return 1;
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}
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/*
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* Reads the adapter's MAC address from the EEPROM
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* hw - Struct containing variables accessed by shared code
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*/
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s32 atl1_read_mac_addr(struct atl1_hw *hw)
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{
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u16 i;
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if (atl1_get_permanent_address(hw))
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random_ether_addr(hw->perm_mac_addr);
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for (i = 0; i < ETH_ALEN; i++)
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hw->mac_addr[i] = hw->perm_mac_addr[i];
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return ATL1_SUCCESS;
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}
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/*
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* Hashes an address to determine its location in the multicast table
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* hw - Struct containing variables accessed by shared code
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* mc_addr - the multicast address to hash
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*
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* atl1_hash_mc_addr
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* purpose
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* set hash value for a multicast address
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* hash calcu processing :
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* 1. calcu 32bit CRC for multicast address
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* 2. reverse crc with MSB to LSB
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*/
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u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
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{
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u32 crc32, value = 0;
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int i;
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crc32 = ether_crc_le(6, mc_addr);
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for (i = 0; i < 32; i++)
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value |= (((crc32 >> i) & 1) << (31 - i));
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return value;
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}
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/*
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* Sets the bit in the multicast table corresponding to the hash value.
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* hw - Struct containing variables accessed by shared code
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* hash_value - Multicast address hash value
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*/
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void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
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{
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u32 hash_bit, hash_reg;
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u32 mta;
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/*
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* The HASH Table is a register array of 2 32-bit registers.
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* It is treated like an array of 64 bits. We want to set
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* bit BitArray[hash_value]. So we figure out what register
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* the bit is in, read it, OR in the new bit, then write
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* back the new value. The register is determined by the
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* upper 7 bits of the hash value and the bit within that
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* register are determined by the lower 5 bits of the value.
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*/
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hash_reg = (hash_value >> 31) & 0x1;
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hash_bit = (hash_value >> 26) & 0x1F;
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mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
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mta |= (1 << hash_bit);
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iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
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}
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/*
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* Writes a value to a PHY register
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* hw - Struct containing variables accessed by shared code
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* reg_addr - address of the PHY register to write
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* data - data to write to the PHY
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*/
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s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
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{
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int i;
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u32 val;
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val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
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(reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
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MDIO_SUP_PREAMBLE |
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MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
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iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
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ioread32(hw->hw_addr + REG_MDIO_CTRL);
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for (i = 0; i < MDIO_WAIT_TIMES; i++) {
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udelay(2);
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val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
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if (!(val & (MDIO_START | MDIO_BUSY)))
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break;
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}
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if (!(val & (MDIO_START | MDIO_BUSY)))
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return ATL1_SUCCESS;
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return ATL1_ERR_PHY;
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}
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/*
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* Make L001's PHY out of Power Saving State (bug)
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* hw - Struct containing variables accessed by shared code
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* when power on, L001's PHY always on Power saving State
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* (Gigabit Link forbidden)
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*/
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static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
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{
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s32 ret;
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ret = atl1_write_phy_reg(hw, 29, 0x0029);
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if (ret)
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return ret;
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return atl1_write_phy_reg(hw, 30, 0);
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}
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/*
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*TODO: do something or get rid of this
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*/
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s32 atl1_phy_enter_power_saving(struct atl1_hw *hw)
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{
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/* s32 ret_val;
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* u16 phy_data;
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*/
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/*
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ret_val = atl1_write_phy_reg(hw, ...);
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ret_val = atl1_write_phy_reg(hw, ...);
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....
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*/
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return ATL1_SUCCESS;
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}
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/*
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* Resets the PHY and make all config validate
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* hw - Struct containing variables accessed by shared code
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*
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* Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
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*/
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static s32 atl1_phy_reset(struct atl1_hw *hw)
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{
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struct pci_dev *pdev = hw->back->pdev;
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s32 ret_val;
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u16 phy_data;
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if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
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hw->media_type == MEDIA_TYPE_1000M_FULL)
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phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
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else {
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switch (hw->media_type) {
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case MEDIA_TYPE_100M_FULL:
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phy_data =
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MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
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MII_CR_RESET;
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break;
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case MEDIA_TYPE_100M_HALF:
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phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
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break;
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case MEDIA_TYPE_10M_FULL:
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phy_data =
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MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
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break;
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default: /* MEDIA_TYPE_10M_HALF: */
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phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
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break;
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}
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}
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ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
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if (ret_val) {
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u32 val;
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int i;
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/* pcie serdes link may be down! */
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dev_dbg(&pdev->dev, "pcie phy link down\n");
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for (i = 0; i < 25; i++) {
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msleep(1);
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val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
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if (!(val & (MDIO_START | MDIO_BUSY)))
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break;
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}
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if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
|
|
dev_warn(&pdev->dev, "pcie link down at least 25ms\n");
|
|
return ret_val;
|
|
}
|
|
}
|
|
return ATL1_SUCCESS;
|
|
}
|
|
|
|
/*
|
|
* Configures PHY autoneg and flow control advertisement settings
|
|
* hw - Struct containing variables accessed by shared code
|
|
*/
|
|
s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
|
|
{
|
|
s32 ret_val;
|
|
s16 mii_autoneg_adv_reg;
|
|
s16 mii_1000t_ctrl_reg;
|
|
|
|
/* Read the MII Auto-Neg Advertisement Register (Address 4). */
|
|
mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
|
|
|
|
/* Read the MII 1000Base-T Control Register (Address 9). */
|
|
mii_1000t_ctrl_reg = MII_AT001_CR_1000T_DEFAULT_CAP_MASK;
|
|
|
|
/*
|
|
* First we clear all the 10/100 mb speed bits in the Auto-Neg
|
|
* Advertisement Register (Address 4) and the 1000 mb speed bits in
|
|
* the 1000Base-T Control Register (Address 9).
|
|
*/
|
|
mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
|
|
mii_1000t_ctrl_reg &= ~MII_AT001_CR_1000T_SPEED_MASK;
|
|
|
|
/*
|
|
* Need to parse media_type and set up
|
|
* the appropriate PHY registers.
|
|
*/
|
|
switch (hw->media_type) {
|
|
case MEDIA_TYPE_AUTO_SENSOR:
|
|
mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
|
|
MII_AR_10T_FD_CAPS |
|
|
MII_AR_100TX_HD_CAPS |
|
|
MII_AR_100TX_FD_CAPS);
|
|
mii_1000t_ctrl_reg |= MII_AT001_CR_1000T_FD_CAPS;
|
|
break;
|
|
|
|
case MEDIA_TYPE_1000M_FULL:
|
|
mii_1000t_ctrl_reg |= MII_AT001_CR_1000T_FD_CAPS;
|
|
break;
|
|
|
|
case MEDIA_TYPE_100M_FULL:
|
|
mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
|
|
break;
|
|
|
|
case MEDIA_TYPE_100M_HALF:
|
|
mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
|
|
break;
|
|
|
|
case MEDIA_TYPE_10M_FULL:
|
|
mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
|
|
break;
|
|
|
|
default:
|
|
mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
|
|
break;
|
|
}
|
|
|
|
/* flow control fixed to enable all */
|
|
mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
|
|
|
|
hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
|
|
hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
|
|
|
|
ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
|
|
if (ret_val)
|
|
return ret_val;
|
|
|
|
ret_val = atl1_write_phy_reg(hw, MII_AT001_CR, mii_1000t_ctrl_reg);
|
|
if (ret_val)
|
|
return ret_val;
|
|
|
|
return ATL1_SUCCESS;
|
|
}
|
|
|
|
/*
|
|
* Configures link settings.
|
|
* hw - Struct containing variables accessed by shared code
|
|
* Assumes the hardware has previously been reset and the
|
|
* transmitter and receiver are not enabled.
|
|
*/
|
|
static s32 atl1_setup_link(struct atl1_hw *hw)
|
|
{
|
|
struct pci_dev *pdev = hw->back->pdev;
|
|
s32 ret_val;
|
|
|
|
/*
|
|
* Options:
|
|
* PHY will advertise value(s) parsed from
|
|
* autoneg_advertised and fc
|
|
* no matter what autoneg is , We will not wait link result.
|
|
*/
|
|
ret_val = atl1_phy_setup_autoneg_adv(hw);
|
|
if (ret_val) {
|
|
dev_dbg(&pdev->dev, "error setting up autonegotiation\n");
|
|
return ret_val;
|
|
}
|
|
/* SW.Reset , En-Auto-Neg if needed */
|
|
ret_val = atl1_phy_reset(hw);
|
|
if (ret_val) {
|
|
dev_dbg(&pdev->dev, "error resetting phy\n");
|
|
return ret_val;
|
|
}
|
|
hw->phy_configured = true;
|
|
return ret_val;
|
|
}
|
|
|
|
static struct atl1_spi_flash_dev flash_table[] = {
|
|
/* MFR_NAME WRSR READ PRGM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
|
|
{"Atmel", 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62},
|
|
{"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60},
|
|
{"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7},
|
|
};
|
|
|
|
static void atl1_init_flash_opcode(struct atl1_hw *hw)
|
|
{
|
|
if (hw->flash_vendor >= sizeof(flash_table) / sizeof(flash_table[0]))
|
|
hw->flash_vendor = 0; /* ATMEL */
|
|
|
|
/* Init OP table */
|
|
iowrite8(flash_table[hw->flash_vendor].cmd_program,
|
|
hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
|
|
iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
|
|
hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
|
|
iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
|
|
hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
|
|
iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
|
|
hw->hw_addr + REG_SPI_FLASH_OP_RDID);
|
|
iowrite8(flash_table[hw->flash_vendor].cmd_wren,
|
|
hw->hw_addr + REG_SPI_FLASH_OP_WREN);
|
|
iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
|
|
hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
|
|
iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
|
|
hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
|
|
iowrite8(flash_table[hw->flash_vendor].cmd_read,
|
|
hw->hw_addr + REG_SPI_FLASH_OP_READ);
|
|
}
|
|
|
|
/*
|
|
* Performs basic configuration of the adapter.
|
|
* hw - Struct containing variables accessed by shared code
|
|
* Assumes that the controller has previously been reset and is in a
|
|
* post-reset uninitialized state. Initializes multicast table,
|
|
* and Calls routines to setup link
|
|
* Leaves the transmit and receive units disabled and uninitialized.
|
|
*/
|
|
s32 atl1_init_hw(struct atl1_hw *hw)
|
|
{
|
|
u32 ret_val = 0;
|
|
|
|
/* Zero out the Multicast HASH table */
|
|
iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
|
|
/* clear the old settings from the multicast hash table */
|
|
iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
|
|
|
|
atl1_init_flash_opcode(hw);
|
|
|
|
if (!hw->phy_configured) {
|
|
/* enable GPHY LinkChange Interrrupt */
|
|
ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
|
|
if (ret_val)
|
|
return ret_val;
|
|
/* make PHY out of power-saving state */
|
|
ret_val = atl1_phy_leave_power_saving(hw);
|
|
if (ret_val)
|
|
return ret_val;
|
|
/* Call a subroutine to configure the link */
|
|
ret_val = atl1_setup_link(hw);
|
|
}
|
|
return ret_val;
|
|
}
|
|
|
|
/*
|
|
* Detects the current speed and duplex settings of the hardware.
|
|
* hw - Struct containing variables accessed by shared code
|
|
* speed - Speed of the connection
|
|
* duplex - Duplex setting of the connection
|
|
*/
|
|
s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
|
|
{
|
|
struct pci_dev *pdev = hw->back->pdev;
|
|
s32 ret_val;
|
|
u16 phy_data;
|
|
|
|
/* ; --- Read PHY Specific Status Register (17) */
|
|
ret_val = atl1_read_phy_reg(hw, MII_AT001_PSSR, &phy_data);
|
|
if (ret_val)
|
|
return ret_val;
|
|
|
|
if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED))
|
|
return ATL1_ERR_PHY_RES;
|
|
|
|
switch (phy_data & MII_AT001_PSSR_SPEED) {
|
|
case MII_AT001_PSSR_1000MBS:
|
|
*speed = SPEED_1000;
|
|
break;
|
|
case MII_AT001_PSSR_100MBS:
|
|
*speed = SPEED_100;
|
|
break;
|
|
case MII_AT001_PSSR_10MBS:
|
|
*speed = SPEED_10;
|
|
break;
|
|
default:
|
|
dev_dbg(&pdev->dev, "error getting speed\n");
|
|
return ATL1_ERR_PHY_SPEED;
|
|
break;
|
|
}
|
|
if (phy_data & MII_AT001_PSSR_DPLX)
|
|
*duplex = FULL_DUPLEX;
|
|
else
|
|
*duplex = HALF_DUPLEX;
|
|
|
|
return ATL1_SUCCESS;
|
|
}
|
|
|
|
void atl1_set_mac_addr(struct atl1_hw *hw)
|
|
{
|
|
u32 value;
|
|
/*
|
|
* 00-0B-6A-F6-00-DC
|
|
* 0: 6AF600DC 1: 000B
|
|
* low dword
|
|
*/
|
|
value = (((u32) hw->mac_addr[2]) << 24) |
|
|
(((u32) hw->mac_addr[3]) << 16) |
|
|
(((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
|
|
iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
|
|
/* high dword */
|
|
value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
|
|
iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
|
|
}
|