609 строки
16 KiB
C
609 строки
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* PCIe host controller driver for Xilinx Versal CPM DMA Bridge
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*
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* (C) Copyright 2019 - 2020, Xilinx, Inc.
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*/
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#include <linux/bitfield.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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#include <linux/of_irq.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/pci-ecam.h>
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#include "../pci.h"
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/* Register definitions */
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#define XILINX_CPM_PCIE_REG_IDR 0x00000E10
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#define XILINX_CPM_PCIE_REG_IMR 0x00000E14
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#define XILINX_CPM_PCIE_REG_PSCR 0x00000E1C
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#define XILINX_CPM_PCIE_REG_RPSC 0x00000E20
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#define XILINX_CPM_PCIE_REG_RPEFR 0x00000E2C
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#define XILINX_CPM_PCIE_REG_IDRN 0x00000E38
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#define XILINX_CPM_PCIE_REG_IDRN_MASK 0x00000E3C
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#define XILINX_CPM_PCIE_MISC_IR_STATUS 0x00000340
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#define XILINX_CPM_PCIE_MISC_IR_ENABLE 0x00000348
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#define XILINX_CPM_PCIE_MISC_IR_LOCAL BIT(1)
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/* Interrupt registers definitions */
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#define XILINX_CPM_PCIE_INTR_LINK_DOWN 0
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#define XILINX_CPM_PCIE_INTR_HOT_RESET 3
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#define XILINX_CPM_PCIE_INTR_CFG_PCIE_TIMEOUT 4
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#define XILINX_CPM_PCIE_INTR_CFG_TIMEOUT 8
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#define XILINX_CPM_PCIE_INTR_CORRECTABLE 9
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#define XILINX_CPM_PCIE_INTR_NONFATAL 10
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#define XILINX_CPM_PCIE_INTR_FATAL 11
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#define XILINX_CPM_PCIE_INTR_CFG_ERR_POISON 12
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#define XILINX_CPM_PCIE_INTR_PME_TO_ACK_RCVD 15
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#define XILINX_CPM_PCIE_INTR_INTX 16
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#define XILINX_CPM_PCIE_INTR_PM_PME_RCVD 17
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#define XILINX_CPM_PCIE_INTR_SLV_UNSUPP 20
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#define XILINX_CPM_PCIE_INTR_SLV_UNEXP 21
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#define XILINX_CPM_PCIE_INTR_SLV_COMPL 22
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#define XILINX_CPM_PCIE_INTR_SLV_ERRP 23
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#define XILINX_CPM_PCIE_INTR_SLV_CMPABT 24
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#define XILINX_CPM_PCIE_INTR_SLV_ILLBUR 25
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#define XILINX_CPM_PCIE_INTR_MST_DECERR 26
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#define XILINX_CPM_PCIE_INTR_MST_SLVERR 27
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#define XILINX_CPM_PCIE_INTR_SLV_PCIE_TIMEOUT 28
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#define IMR(x) BIT(XILINX_CPM_PCIE_INTR_ ##x)
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#define XILINX_CPM_PCIE_IMR_ALL_MASK \
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( \
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IMR(LINK_DOWN) | \
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IMR(HOT_RESET) | \
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IMR(CFG_PCIE_TIMEOUT) | \
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IMR(CFG_TIMEOUT) | \
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IMR(CORRECTABLE) | \
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IMR(NONFATAL) | \
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IMR(FATAL) | \
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IMR(CFG_ERR_POISON) | \
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IMR(PME_TO_ACK_RCVD) | \
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IMR(INTX) | \
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IMR(PM_PME_RCVD) | \
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IMR(SLV_UNSUPP) | \
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IMR(SLV_UNEXP) | \
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IMR(SLV_COMPL) | \
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IMR(SLV_ERRP) | \
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IMR(SLV_CMPABT) | \
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IMR(SLV_ILLBUR) | \
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IMR(MST_DECERR) | \
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IMR(MST_SLVERR) | \
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IMR(SLV_PCIE_TIMEOUT) \
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)
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#define XILINX_CPM_PCIE_IDR_ALL_MASK 0xFFFFFFFF
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#define XILINX_CPM_PCIE_IDRN_MASK GENMASK(19, 16)
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#define XILINX_CPM_PCIE_IDRN_SHIFT 16
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/* Root Port Error FIFO Read Register definitions */
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#define XILINX_CPM_PCIE_RPEFR_ERR_VALID BIT(18)
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#define XILINX_CPM_PCIE_RPEFR_REQ_ID GENMASK(15, 0)
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#define XILINX_CPM_PCIE_RPEFR_ALL_MASK 0xFFFFFFFF
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/* Root Port Status/control Register definitions */
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#define XILINX_CPM_PCIE_REG_RPSC_BEN BIT(0)
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/* Phy Status/Control Register definitions */
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#define XILINX_CPM_PCIE_REG_PSCR_LNKUP BIT(11)
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/**
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* struct xilinx_cpm_pcie - PCIe port information
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* @dev: Device pointer
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* @reg_base: Bridge Register Base
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* @cpm_base: CPM System Level Control and Status Register(SLCR) Base
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* @intx_domain: Legacy IRQ domain pointer
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* @cpm_domain: CPM IRQ domain pointer
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* @cfg: Holds mappings of config space window
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* @intx_irq: legacy interrupt number
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* @irq: Error interrupt number
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* @lock: lock protecting shared register access
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*/
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struct xilinx_cpm_pcie {
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struct device *dev;
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void __iomem *reg_base;
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void __iomem *cpm_base;
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struct irq_domain *intx_domain;
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struct irq_domain *cpm_domain;
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struct pci_config_window *cfg;
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int intx_irq;
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int irq;
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raw_spinlock_t lock;
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};
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static u32 pcie_read(struct xilinx_cpm_pcie *port, u32 reg)
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{
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return readl_relaxed(port->reg_base + reg);
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}
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static void pcie_write(struct xilinx_cpm_pcie *port,
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u32 val, u32 reg)
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{
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writel_relaxed(val, port->reg_base + reg);
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}
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static bool cpm_pcie_link_up(struct xilinx_cpm_pcie *port)
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{
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return (pcie_read(port, XILINX_CPM_PCIE_REG_PSCR) &
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XILINX_CPM_PCIE_REG_PSCR_LNKUP);
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}
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static void cpm_pcie_clear_err_interrupts(struct xilinx_cpm_pcie *port)
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{
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unsigned long val = pcie_read(port, XILINX_CPM_PCIE_REG_RPEFR);
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if (val & XILINX_CPM_PCIE_RPEFR_ERR_VALID) {
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dev_dbg(port->dev, "Requester ID %lu\n",
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val & XILINX_CPM_PCIE_RPEFR_REQ_ID);
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pcie_write(port, XILINX_CPM_PCIE_RPEFR_ALL_MASK,
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XILINX_CPM_PCIE_REG_RPEFR);
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}
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}
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static void xilinx_cpm_mask_leg_irq(struct irq_data *data)
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{
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struct xilinx_cpm_pcie *port = irq_data_get_irq_chip_data(data);
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unsigned long flags;
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u32 mask;
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u32 val;
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mask = BIT(data->hwirq + XILINX_CPM_PCIE_IDRN_SHIFT);
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raw_spin_lock_irqsave(&port->lock, flags);
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val = pcie_read(port, XILINX_CPM_PCIE_REG_IDRN_MASK);
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pcie_write(port, (val & (~mask)), XILINX_CPM_PCIE_REG_IDRN_MASK);
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raw_spin_unlock_irqrestore(&port->lock, flags);
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}
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static void xilinx_cpm_unmask_leg_irq(struct irq_data *data)
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{
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struct xilinx_cpm_pcie *port = irq_data_get_irq_chip_data(data);
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unsigned long flags;
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u32 mask;
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u32 val;
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mask = BIT(data->hwirq + XILINX_CPM_PCIE_IDRN_SHIFT);
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raw_spin_lock_irqsave(&port->lock, flags);
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val = pcie_read(port, XILINX_CPM_PCIE_REG_IDRN_MASK);
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pcie_write(port, (val | mask), XILINX_CPM_PCIE_REG_IDRN_MASK);
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raw_spin_unlock_irqrestore(&port->lock, flags);
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}
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static struct irq_chip xilinx_cpm_leg_irq_chip = {
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.name = "INTx",
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.irq_mask = xilinx_cpm_mask_leg_irq,
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.irq_unmask = xilinx_cpm_unmask_leg_irq,
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};
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/**
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* xilinx_cpm_pcie_intx_map - Set the handler for the INTx and mark IRQ as valid
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* @domain: IRQ domain
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* @irq: Virtual IRQ number
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* @hwirq: HW interrupt number
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*
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* Return: Always returns 0.
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*/
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static int xilinx_cpm_pcie_intx_map(struct irq_domain *domain,
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unsigned int irq, irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &xilinx_cpm_leg_irq_chip,
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handle_level_irq);
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irq_set_chip_data(irq, domain->host_data);
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irq_set_status_flags(irq, IRQ_LEVEL);
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return 0;
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}
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/* INTx IRQ Domain operations */
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static const struct irq_domain_ops intx_domain_ops = {
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.map = xilinx_cpm_pcie_intx_map,
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};
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static void xilinx_cpm_pcie_intx_flow(struct irq_desc *desc)
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{
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struct xilinx_cpm_pcie *port = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned long val;
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int i;
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chained_irq_enter(chip, desc);
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val = FIELD_GET(XILINX_CPM_PCIE_IDRN_MASK,
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pcie_read(port, XILINX_CPM_PCIE_REG_IDRN));
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for_each_set_bit(i, &val, PCI_NUM_INTX)
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generic_handle_domain_irq(port->intx_domain, i);
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chained_irq_exit(chip, desc);
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}
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static void xilinx_cpm_mask_event_irq(struct irq_data *d)
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{
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struct xilinx_cpm_pcie *port = irq_data_get_irq_chip_data(d);
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u32 val;
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raw_spin_lock(&port->lock);
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val = pcie_read(port, XILINX_CPM_PCIE_REG_IMR);
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val &= ~BIT(d->hwirq);
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pcie_write(port, val, XILINX_CPM_PCIE_REG_IMR);
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raw_spin_unlock(&port->lock);
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}
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static void xilinx_cpm_unmask_event_irq(struct irq_data *d)
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{
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struct xilinx_cpm_pcie *port = irq_data_get_irq_chip_data(d);
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u32 val;
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raw_spin_lock(&port->lock);
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val = pcie_read(port, XILINX_CPM_PCIE_REG_IMR);
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val |= BIT(d->hwirq);
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pcie_write(port, val, XILINX_CPM_PCIE_REG_IMR);
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raw_spin_unlock(&port->lock);
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}
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static struct irq_chip xilinx_cpm_event_irq_chip = {
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.name = "RC-Event",
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.irq_mask = xilinx_cpm_mask_event_irq,
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.irq_unmask = xilinx_cpm_unmask_event_irq,
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};
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static int xilinx_cpm_pcie_event_map(struct irq_domain *domain,
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unsigned int irq, irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &xilinx_cpm_event_irq_chip,
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handle_level_irq);
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irq_set_chip_data(irq, domain->host_data);
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irq_set_status_flags(irq, IRQ_LEVEL);
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return 0;
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}
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static const struct irq_domain_ops event_domain_ops = {
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.map = xilinx_cpm_pcie_event_map,
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};
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static void xilinx_cpm_pcie_event_flow(struct irq_desc *desc)
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{
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struct xilinx_cpm_pcie *port = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned long val;
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int i;
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chained_irq_enter(chip, desc);
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val = pcie_read(port, XILINX_CPM_PCIE_REG_IDR);
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val &= pcie_read(port, XILINX_CPM_PCIE_REG_IMR);
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for_each_set_bit(i, &val, 32)
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generic_handle_domain_irq(port->cpm_domain, i);
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pcie_write(port, val, XILINX_CPM_PCIE_REG_IDR);
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/*
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* XILINX_CPM_PCIE_MISC_IR_STATUS register is mapped to
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* CPM SLCR block.
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*/
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val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE_MISC_IR_STATUS);
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if (val)
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writel_relaxed(val,
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port->cpm_base + XILINX_CPM_PCIE_MISC_IR_STATUS);
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chained_irq_exit(chip, desc);
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}
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#define _IC(x, s) \
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[XILINX_CPM_PCIE_INTR_ ## x] = { __stringify(x), s }
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static const struct {
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const char *sym;
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const char *str;
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} intr_cause[32] = {
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_IC(LINK_DOWN, "Link Down"),
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_IC(HOT_RESET, "Hot reset"),
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_IC(CFG_TIMEOUT, "ECAM access timeout"),
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_IC(CORRECTABLE, "Correctable error message"),
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_IC(NONFATAL, "Non fatal error message"),
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_IC(FATAL, "Fatal error message"),
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_IC(SLV_UNSUPP, "Slave unsupported request"),
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_IC(SLV_UNEXP, "Slave unexpected completion"),
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_IC(SLV_COMPL, "Slave completion timeout"),
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_IC(SLV_ERRP, "Slave Error Poison"),
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_IC(SLV_CMPABT, "Slave Completer Abort"),
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_IC(SLV_ILLBUR, "Slave Illegal Burst"),
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_IC(MST_DECERR, "Master decode error"),
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_IC(MST_SLVERR, "Master slave error"),
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_IC(CFG_PCIE_TIMEOUT, "PCIe ECAM access timeout"),
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_IC(CFG_ERR_POISON, "ECAM poisoned completion received"),
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_IC(PME_TO_ACK_RCVD, "PME_TO_ACK message received"),
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_IC(PM_PME_RCVD, "PM_PME message received"),
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_IC(SLV_PCIE_TIMEOUT, "PCIe completion timeout received"),
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};
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static irqreturn_t xilinx_cpm_pcie_intr_handler(int irq, void *dev_id)
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{
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struct xilinx_cpm_pcie *port = dev_id;
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struct device *dev = port->dev;
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struct irq_data *d;
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d = irq_domain_get_irq_data(port->cpm_domain, irq);
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switch (d->hwirq) {
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case XILINX_CPM_PCIE_INTR_CORRECTABLE:
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case XILINX_CPM_PCIE_INTR_NONFATAL:
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case XILINX_CPM_PCIE_INTR_FATAL:
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cpm_pcie_clear_err_interrupts(port);
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fallthrough;
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default:
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if (intr_cause[d->hwirq].str)
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dev_warn(dev, "%s\n", intr_cause[d->hwirq].str);
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else
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dev_warn(dev, "Unknown IRQ %ld\n", d->hwirq);
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}
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return IRQ_HANDLED;
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}
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static void xilinx_cpm_free_irq_domains(struct xilinx_cpm_pcie *port)
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{
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if (port->intx_domain) {
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irq_domain_remove(port->intx_domain);
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port->intx_domain = NULL;
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}
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if (port->cpm_domain) {
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irq_domain_remove(port->cpm_domain);
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port->cpm_domain = NULL;
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}
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}
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/**
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* xilinx_cpm_pcie_init_irq_domain - Initialize IRQ domain
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* @port: PCIe port information
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*
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* Return: '0' on success and error value on failure
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*/
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static int xilinx_cpm_pcie_init_irq_domain(struct xilinx_cpm_pcie *port)
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{
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struct device *dev = port->dev;
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struct device_node *node = dev->of_node;
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struct device_node *pcie_intc_node;
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/* Setup INTx */
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pcie_intc_node = of_get_next_child(node, NULL);
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if (!pcie_intc_node) {
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dev_err(dev, "No PCIe Intc node found\n");
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return -EINVAL;
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}
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port->cpm_domain = irq_domain_add_linear(pcie_intc_node, 32,
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&event_domain_ops,
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port);
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if (!port->cpm_domain)
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goto out;
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irq_domain_update_bus_token(port->cpm_domain, DOMAIN_BUS_NEXUS);
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port->intx_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
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&intx_domain_ops,
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port);
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if (!port->intx_domain)
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goto out;
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irq_domain_update_bus_token(port->intx_domain, DOMAIN_BUS_WIRED);
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of_node_put(pcie_intc_node);
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raw_spin_lock_init(&port->lock);
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return 0;
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out:
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xilinx_cpm_free_irq_domains(port);
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of_node_put(pcie_intc_node);
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dev_err(dev, "Failed to allocate IRQ domains\n");
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return -ENOMEM;
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}
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static int xilinx_cpm_setup_irq(struct xilinx_cpm_pcie *port)
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{
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struct device *dev = port->dev;
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struct platform_device *pdev = to_platform_device(dev);
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int i, irq;
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port->irq = platform_get_irq(pdev, 0);
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if (port->irq < 0)
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return port->irq;
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for (i = 0; i < ARRAY_SIZE(intr_cause); i++) {
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int err;
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if (!intr_cause[i].str)
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continue;
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irq = irq_create_mapping(port->cpm_domain, i);
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if (!irq) {
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dev_err(dev, "Failed to map interrupt\n");
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return -ENXIO;
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}
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err = devm_request_irq(dev, irq, xilinx_cpm_pcie_intr_handler,
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0, intr_cause[i].sym, port);
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|
if (err) {
|
|
dev_err(dev, "Failed to request IRQ %d\n", irq);
|
|
return err;
|
|
}
|
|
}
|
|
|
|
port->intx_irq = irq_create_mapping(port->cpm_domain,
|
|
XILINX_CPM_PCIE_INTR_INTX);
|
|
if (!port->intx_irq) {
|
|
dev_err(dev, "Failed to map INTx interrupt\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
/* Plug the INTx chained handler */
|
|
irq_set_chained_handler_and_data(port->intx_irq,
|
|
xilinx_cpm_pcie_intx_flow, port);
|
|
|
|
/* Plug the main event chained handler */
|
|
irq_set_chained_handler_and_data(port->irq,
|
|
xilinx_cpm_pcie_event_flow, port);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* xilinx_cpm_pcie_init_port - Initialize hardware
|
|
* @port: PCIe port information
|
|
*/
|
|
static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port)
|
|
{
|
|
if (cpm_pcie_link_up(port))
|
|
dev_info(port->dev, "PCIe Link is UP\n");
|
|
else
|
|
dev_info(port->dev, "PCIe Link is DOWN\n");
|
|
|
|
/* Disable all interrupts */
|
|
pcie_write(port, ~XILINX_CPM_PCIE_IDR_ALL_MASK,
|
|
XILINX_CPM_PCIE_REG_IMR);
|
|
|
|
/* Clear pending interrupts */
|
|
pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_IDR) &
|
|
XILINX_CPM_PCIE_IMR_ALL_MASK,
|
|
XILINX_CPM_PCIE_REG_IDR);
|
|
|
|
/*
|
|
* XILINX_CPM_PCIE_MISC_IR_ENABLE register is mapped to
|
|
* CPM SLCR block.
|
|
*/
|
|
writel(XILINX_CPM_PCIE_MISC_IR_LOCAL,
|
|
port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE);
|
|
/* Enable the Bridge enable bit */
|
|
pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_RPSC) |
|
|
XILINX_CPM_PCIE_REG_RPSC_BEN,
|
|
XILINX_CPM_PCIE_REG_RPSC);
|
|
}
|
|
|
|
/**
|
|
* xilinx_cpm_pcie_parse_dt - Parse Device tree
|
|
* @port: PCIe port information
|
|
* @bus_range: Bus resource
|
|
*
|
|
* Return: '0' on success and error value on failure
|
|
*/
|
|
static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port,
|
|
struct resource *bus_range)
|
|
{
|
|
struct device *dev = port->dev;
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct resource *res;
|
|
|
|
port->cpm_base = devm_platform_ioremap_resource_byname(pdev,
|
|
"cpm_slcr");
|
|
if (IS_ERR(port->cpm_base))
|
|
return PTR_ERR(port->cpm_base);
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
|
|
if (!res)
|
|
return -ENXIO;
|
|
|
|
port->cfg = pci_ecam_create(dev, res, bus_range,
|
|
&pci_generic_ecam_ops);
|
|
if (IS_ERR(port->cfg))
|
|
return PTR_ERR(port->cfg);
|
|
|
|
port->reg_base = port->cfg->win;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void xilinx_cpm_free_interrupts(struct xilinx_cpm_pcie *port)
|
|
{
|
|
irq_set_chained_handler_and_data(port->intx_irq, NULL, NULL);
|
|
irq_set_chained_handler_and_data(port->irq, NULL, NULL);
|
|
}
|
|
|
|
/**
|
|
* xilinx_cpm_pcie_probe - Probe function
|
|
* @pdev: Platform device pointer
|
|
*
|
|
* Return: '0' on success and error value on failure
|
|
*/
|
|
static int xilinx_cpm_pcie_probe(struct platform_device *pdev)
|
|
{
|
|
struct xilinx_cpm_pcie *port;
|
|
struct device *dev = &pdev->dev;
|
|
struct pci_host_bridge *bridge;
|
|
struct resource_entry *bus;
|
|
int err;
|
|
|
|
bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port));
|
|
if (!bridge)
|
|
return -ENODEV;
|
|
|
|
port = pci_host_bridge_priv(bridge);
|
|
|
|
port->dev = dev;
|
|
|
|
err = xilinx_cpm_pcie_init_irq_domain(port);
|
|
if (err)
|
|
return err;
|
|
|
|
bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS);
|
|
if (!bus)
|
|
return -ENODEV;
|
|
|
|
err = xilinx_cpm_pcie_parse_dt(port, bus->res);
|
|
if (err) {
|
|
dev_err(dev, "Parsing DT failed\n");
|
|
goto err_parse_dt;
|
|
}
|
|
|
|
xilinx_cpm_pcie_init_port(port);
|
|
|
|
err = xilinx_cpm_setup_irq(port);
|
|
if (err) {
|
|
dev_err(dev, "Failed to set up interrupts\n");
|
|
goto err_setup_irq;
|
|
}
|
|
|
|
bridge->sysdata = port->cfg;
|
|
bridge->ops = (struct pci_ops *)&pci_generic_ecam_ops.pci_ops;
|
|
|
|
err = pci_host_probe(bridge);
|
|
if (err < 0)
|
|
goto err_host_bridge;
|
|
|
|
return 0;
|
|
|
|
err_host_bridge:
|
|
xilinx_cpm_free_interrupts(port);
|
|
err_setup_irq:
|
|
pci_ecam_free(port->cfg);
|
|
err_parse_dt:
|
|
xilinx_cpm_free_irq_domains(port);
|
|
return err;
|
|
}
|
|
|
|
static const struct of_device_id xilinx_cpm_pcie_of_match[] = {
|
|
{ .compatible = "xlnx,versal-cpm-host-1.00", },
|
|
{}
|
|
};
|
|
|
|
static struct platform_driver xilinx_cpm_pcie_driver = {
|
|
.driver = {
|
|
.name = "xilinx-cpm-pcie",
|
|
.of_match_table = xilinx_cpm_pcie_of_match,
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
.probe = xilinx_cpm_pcie_probe,
|
|
};
|
|
|
|
builtin_platform_driver(xilinx_cpm_pcie_driver);
|